arch/arm/mach-s3c/s3c64xx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Copyright (c) 2011 Samsung Electronics Co., Ltd.
   4 //              http://www.samsung.com
   5 //
   6 // Copyright 2008 Openmoko, Inc.
   7 // Copyright 2008 Simtec Electronics
   8 //      Ben Dooks <ben@simtec.co.uk>
   9 //      http://armlinux.simtec.co.uk/
  10 //
  11 // Common Codes for S3C64XX machines
  12
  13 /*
  14  * NOTE: Code in this file is not used when booting with Device Tree support.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/module.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/ioport.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/serial_s3c.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/reboot.h>
  26 #include <linux/io.h>
  27 #include <linux/clk/samsung.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/irq.h>
  30 #include <linux/gpio.h>
  31 #include <linux/irqchip/arm-vic.h>
  32 #include <clocksource/samsung_pwm.h>
  33
  34 #include <asm/mach/arch.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/system_misc.h>
  37
  38 #include <mach/map.h>
  39 #include <mach/irqs.h>
  40 #include <mach/regs-gpio.h>
  41 #include <mach/gpio-samsung.h>
  42
  43 #include <plat/cpu.h>
  44 #include <plat/devs.h>
  45 #include <plat/pm.h>
  46 #include <plat/gpio-cfg.h>
  47 #include <plat/pwm-core.h>
  48 #include <plat/regs-irqtype.h>
  49
  50 #include "s3c64xx.h"
  51 #include "irq-uart-s3c64xx.h"
  52
  53 /* External clock frequency */
  54 static unsigned long xtal_f __ro_after_init = 12000000;
  55 static unsigned long xusbxti_f __ro_after_init = 48000000;
  56
  57 void __init s3c64xx_set_xtal_freq(unsigned long freq)
  58 {
  59         xtal_f = freq;
  60 }
  61
  62 void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
  63 {
  64         xusbxti_f = freq;
  65 }
  66
  67 /* uart registration process */
  68
  69 static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  70 {
  71         s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
  72 }
  73
  74 /* table of supported CPUs */
  75
  76 static const char name_s3c6400[] = "S3C6400";
  77 static const char name_s3c6410[] = "S3C6410";
  78
  79 static struct cpu_table cpu_ids[] __initdata = {
  80         {
  81                 .idcode         = S3C6400_CPU_ID,
  82                 .idmask         = S3C64XX_CPU_MASK,
  83                 .map_io         = s3c6400_map_io,
  84                 .init_uarts     = s3c64xx_init_uarts,
  85                 .init           = s3c6400_init,
  86                 .name           = name_s3c6400,
  87         }, {
  88                 .idcode         = S3C6410_CPU_ID,
  89                 .idmask         = S3C64XX_CPU_MASK,
  90                 .map_io         = s3c6410_map_io,
  91                 .init_uarts     = s3c64xx_init_uarts,
  92                 .init           = s3c6410_init,
  93                 .name           = name_s3c6410,
  94         },
  95 };
  96
  97 /* minimal IO mapping */
  98
  99 /* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
 100 #define UART_OFFS (S3C_PA_UART & 0xfffff)
 101
 102 static struct map_desc s3c_iodesc[] __initdata = {
 103         {
 104                 .virtual        = (unsigned long)S3C_VA_SYS,
 105                 .pfn            = __phys_to_pfn(S3C64XX_PA_SYSCON),
 106                 .length         = SZ_4K,
 107                 .type           = MT_DEVICE,
 108         }, {
 109                 .virtual        = (unsigned long)S3C_VA_MEM,
 110                 .pfn            = __phys_to_pfn(S3C64XX_PA_SROM),
 111                 .length         = SZ_4K,
 112                 .type           = MT_DEVICE,
 113         }, {
 114                 .virtual        = (unsigned long)(S3C_VA_UART + UART_OFFS),
 115                 .pfn            = __phys_to_pfn(S3C_PA_UART),
 116                 .length         = SZ_4K,
 117                 .type           = MT_DEVICE,
 118         }, {
 119                 .virtual        = (unsigned long)VA_VIC0,
 120                 .pfn            = __phys_to_pfn(S3C64XX_PA_VIC0),
 121                 .length         = SZ_16K,
 122                 .type           = MT_DEVICE,
 123         }, {
 124                 .virtual        = (unsigned long)VA_VIC1,
 125                 .pfn            = __phys_to_pfn(S3C64XX_PA_VIC1),
 126                 .length         = SZ_16K,
 127                 .type           = MT_DEVICE,
 128         }, {
 129                 .virtual        = (unsigned long)S3C_VA_TIMER,
 130                 .pfn            = __phys_to_pfn(S3C_PA_TIMER),
 131                 .length         = SZ_16K,
 132                 .type           = MT_DEVICE,
 133         }, {
 134                 .virtual        = (unsigned long)S3C64XX_VA_GPIO,
 135                 .pfn            = __phys_to_pfn(S3C64XX_PA_GPIO),
 136                 .length         = SZ_4K,
 137                 .type           = MT_DEVICE,
 138         }, {
 139                 .virtual        = (unsigned long)S3C64XX_VA_MODEM,
 140                 .pfn            = __phys_to_pfn(S3C64XX_PA_MODEM),
 141                 .length         = SZ_4K,
 142                 .type           = MT_DEVICE,
 143         }, {
 144                 .virtual        = (unsigned long)S3C_VA_WATCHDOG,
 145                 .pfn            = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
 146                 .length         = SZ_4K,
 147                 .type           = MT_DEVICE,
 148         }, {
 149                 .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
 150                 .pfn            = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
 151                 .length         = SZ_1K,
 152                 .type           = MT_DEVICE,
 153         },
 154 };
 155
 156 static struct bus_type s3c64xx_subsys = {
 157         .name           = "s3c64xx-core",
 158         .dev_name       = "s3c64xx-core",
 159 };
 160
 161 static struct device s3c64xx_dev = {
 162         .bus    = &s3c64xx_subsys,
 163 };
 164
 165 static struct samsung_pwm_variant s3c64xx_pwm_variant = {
 166         .bits           = 32,
 167         .div_base       = 0,
 168         .has_tint_cstat = true,
 169         .tclk_mask      = (1 << 7) | (1 << 6) | (1 << 5),
 170 };
 171
 172 void __init samsung_set_timer_source(unsigned int event, unsigned int source)
 173 {
 174         s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
 175         s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
 176 }
 177
 178 void __init samsung_timer_init(void)
 179 {
 180         unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
 181                 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
 182                 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
 183         };
 184
 185         samsung_pwm_clocksource_init(S3C_VA_TIMER,
 186                                         timer_irqs, &s3c64xx_pwm_variant);
 187 }
 188
 189 /* read cpu identification code */
 190
 191 void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
 192 {
 193         /* initialise the io descriptors we need for initialisation */
 194         iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
 195         iotable_init(mach_desc, size);
 196
 197         /* detect cpu id */
 198         s3c64xx_init_cpu();
 199
 200         s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 201
 202         samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
 203 }
 204
 205 static __init int s3c64xx_dev_init(void)
 206 {
 207         /* Not applicable when using DT. */
 208         if (of_have_populated_dt() || !soc_is_s3c64xx())
 209                 return 0;
 210
 211         subsys_system_register(&s3c64xx_subsys, NULL);
 212         return device_register(&s3c64xx_dev);
 213 }
 214 core_initcall(s3c64xx_dev_init);
 215
 216 /*
 217  * setup the sources the vic should advertise resume
 218  * for, even though it is not doing the wake
 219  * (set_irq_wake needs to be valid)
 220  */
 221 #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
 222 #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
 223                          1 << (IRQ_PENDN - IRQ_VIC1_BASE) |     \
 224                          1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) |    \
 225                          1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) |    \
 226                          1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
 227
 228 void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 229 {
 230         s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
 231
 232         printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
 233
 234         /* initialise the pair of VICs */
 235         vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
 236         vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
 237 }
 238
 239 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
 240 #define eint_irq_to_bit(irq)    ((u32)(1 << eint_offset(irq)))
 241
 242 static inline void s3c_irq_eint_mask(struct irq_data *data)
 243 {
 244         u32 mask;
 245
 246         mask = __raw_readl(S3C64XX_EINT0MASK);
 247         mask |= (u32)data->chip_data;
 248         __raw_writel(mask, S3C64XX_EINT0MASK);
 249 }
 250
 251 static void s3c_irq_eint_unmask(struct irq_data *data)
 252 {
 253         u32 mask;
 254
 255         mask = __raw_readl(S3C64XX_EINT0MASK);
 256         mask &= ~((u32)data->chip_data);
 257         __raw_writel(mask, S3C64XX_EINT0MASK);
 258 }
 259
 260 static inline void s3c_irq_eint_ack(struct irq_data *data)
 261 {
 262         __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
 263 }
 264
 265 static void s3c_irq_eint_maskack(struct irq_data *data)
 266 {
 267         /* compiler should in-line these */
 268         s3c_irq_eint_mask(data);
 269         s3c_irq_eint_ack(data);
 270 }
 271
 272 static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
 273 {
 274         int offs = eint_offset(data->irq);
 275         int pin, pin_val;
 276         int shift;
 277         u32 ctrl, mask;
 278         u32 newvalue = 0;
 279         void __iomem *reg;
 280
 281         if (offs > 27)
 282                 return -EINVAL;
 283
 284         if (offs <= 15)
 285                 reg = S3C64XX_EINT0CON0;
 286         else
 287                 reg = S3C64XX_EINT0CON1;
 288
 289         switch (type) {
 290         case IRQ_TYPE_NONE:
 291                 printk(KERN_WARNING "No edge setting!\n");
 292                 break;
 293
 294         case IRQ_TYPE_EDGE_RISING:
 295                 newvalue = S3C2410_EXTINT_RISEEDGE;
 296                 break;
 297
 298         case IRQ_TYPE_EDGE_FALLING:
 299                 newvalue = S3C2410_EXTINT_FALLEDGE;
 300                 break;
 301
 302         case IRQ_TYPE_EDGE_BOTH:
 303                 newvalue = S3C2410_EXTINT_BOTHEDGE;
 304                 break;
 305
 306         case IRQ_TYPE_LEVEL_LOW:
 307                 newvalue = S3C2410_EXTINT_LOWLEV;
 308                 break;
 309
 310         case IRQ_TYPE_LEVEL_HIGH:
 311                 newvalue = S3C2410_EXTINT_HILEV;
 312                 break;
 313
 314         default:
 315                 printk(KERN_ERR "No such irq type %d", type);
 316                 return -1;
 317         }
 318
 319         if (offs <= 15)
 320                 shift = (offs / 2) * 4;
 321         else
 322                 shift = ((offs - 16) / 2) * 4;
 323         mask = 0x7 << shift;
 324
 325         ctrl = __raw_readl(reg);
 326         ctrl &= ~mask;
 327         ctrl |= newvalue << shift;
 328         __raw_writel(ctrl, reg);
 329
 330         /* set the GPIO pin appropriately */
 331
 332         if (offs < 16) {
 333                 pin = S3C64XX_GPN(offs);
 334                 pin_val = S3C_GPIO_SFN(2);
 335         } else if (offs < 23) {
 336                 pin = S3C64XX_GPL(offs + 8 - 16);
 337                 pin_val = S3C_GPIO_SFN(3);
 338         } else {
 339                 pin = S3C64XX_GPM(offs - 23);
 340                 pin_val = S3C_GPIO_SFN(3);
 341         }
 342
 343         s3c_gpio_cfgpin(pin, pin_val);
 344
 345         return 0;
 346 }
 347
 348 static struct irq_chip s3c_irq_eint = {
 349         .name           = "s3c-eint",
 350         .irq_mask       = s3c_irq_eint_mask,
 351         .irq_unmask     = s3c_irq_eint_unmask,
 352         .irq_mask_ack   = s3c_irq_eint_maskack,
 353         .irq_ack        = s3c_irq_eint_ack,
 354         .irq_set_type   = s3c_irq_eint_set_type,
 355         .irq_set_wake   = s3c_irqext_wake,
 356 };
 357
 358 /* s3c_irq_demux_eint
 359  *
 360  * This function demuxes the IRQ from the group0 external interrupts,
 361  * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
 362  * the specific handlers s3c_irq_demux_eintX_Y.
 363  */
 364 static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
 365 {
 366         u32 status = __raw_readl(S3C64XX_EINT0PEND);
 367         u32 mask = __raw_readl(S3C64XX_EINT0MASK);
 368         unsigned int irq;
 369
 370         status &= ~mask;
 371         status >>= start;
 372         status &= (1 << (end - start + 1)) - 1;
 373
 374         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
 375                 if (status & 1)
 376                         generic_handle_irq(irq);
 377
 378                 status >>= 1;
 379         }
 380 }
 381
 382 static void s3c_irq_demux_eint0_3(struct irq_desc *desc)
 383 {
 384         s3c_irq_demux_eint(0, 3);
 385 }
 386
 387 static void s3c_irq_demux_eint4_11(struct irq_desc *desc)
 388 {
 389         s3c_irq_demux_eint(4, 11);
 390 }
 391
 392 static void s3c_irq_demux_eint12_19(struct irq_desc *desc)
 393 {
 394         s3c_irq_demux_eint(12, 19);
 395 }
 396
 397 static void s3c_irq_demux_eint20_27(struct irq_desc *desc)
 398 {
 399         s3c_irq_demux_eint(20, 27);
 400 }
 401
 402 static int __init s3c64xx_init_irq_eint(void)
 403 {
 404         int irq;
 405
 406         /* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
 407         if (of_have_populated_dt() || !soc_is_s3c64xx())
 408                 return -ENODEV;
 409
 410         for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
 411                 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
 412                 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
 413                 irq_clear_status_flags(irq, IRQ_NOREQUEST);
 414         }
 415
 416         irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
 417         irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
 418         irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
 419         irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
 420
 421         return 0;
 422 }
 423 arch_initcall(s3c64xx_init_irq_eint);