1 // SPDX-License-Identifier: GPL-2.0
3 // Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 // http://www.samsung.com/
6 // Copyright 2008 Openmoko, Inc.
7 // Copyright 2008 Simtec Electronics
8 // Ben Dooks <ben@simtec.co.uk>
9 // http://armlinux.simtec.co.uk/
11 // Samsung - GPIOlib support
13 #include <linux/kernel.h>
14 #include <linux/irq.h>
16 #include <linux/gpio.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/interrupt.h>
21 #include <linux/device.h>
22 #include <linux/ioport.h>
24 #include <linux/slab.h>
25 #include <linux/of_address.h>
31 #include "regs-gpio.h"
32 #include "gpio-samsung.h"
35 #include "gpio-core.h"
37 #include "gpio-cfg-helpers.h"
38 #include "hardware-s3c24xx.h"
41 int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip,
42 unsigned int off, samsung_gpio_pull_t pull)
44 void __iomem *reg = chip->base + 0x08;
48 pup = __raw_readl(reg);
51 __raw_writel(pup, reg);
56 samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip,
59 void __iomem *reg = chip->base + 0x08;
61 u32 pup = __raw_readl(reg);
66 return (__force samsung_gpio_pull_t)pup;
69 int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip,
70 unsigned int off, samsung_gpio_pull_t pull)
73 case S3C_GPIO_PULL_NONE:
76 case S3C_GPIO_PULL_UP:
79 case S3C_GPIO_PULL_DOWN:
83 return samsung_gpio_setpull_updown(chip, off, pull);
86 samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip,
89 samsung_gpio_pull_t pull;
91 pull = samsung_gpio_getpull_updown(chip, off);
95 pull = S3C_GPIO_PULL_UP;
99 pull = S3C_GPIO_PULL_NONE;
102 pull = S3C_GPIO_PULL_DOWN;
109 static int s3c24xx_gpio_setpull_1(struct samsung_gpio_chip *chip,
110 unsigned int off, samsung_gpio_pull_t pull,
111 samsung_gpio_pull_t updown)
113 void __iomem *reg = chip->base + 0x08;
114 u32 pup = __raw_readl(reg);
118 else if (pull == S3C_GPIO_PULL_NONE)
123 __raw_writel(pup, reg);
127 static samsung_gpio_pull_t s3c24xx_gpio_getpull_1(struct samsung_gpio_chip *chip,
129 samsung_gpio_pull_t updown)
131 void __iomem *reg = chip->base + 0x08;
132 u32 pup = __raw_readl(reg);
135 return pup ? S3C_GPIO_PULL_NONE : updown;
138 samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip,
141 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP);
144 int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip,
145 unsigned int off, samsung_gpio_pull_t pull)
147 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP);
150 samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip,
153 return s3c24xx_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN);
156 int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
157 unsigned int off, samsung_gpio_pull_t pull)
159 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
163 * samsung_gpio_setcfg_2bit - Samsung 2bit style GPIO configuration.
164 * @chip: The gpio chip that is being configured.
165 * @off: The offset for the GPIO being configured.
166 * @cfg: The configuration value to set.
168 * This helper deal with the GPIO cases where the control register
169 * has two bits of configuration per gpio, which have the following
173 * 1x = special function
176 static int samsung_gpio_setcfg_2bit(struct samsung_gpio_chip *chip,
177 unsigned int off, unsigned int cfg)
179 void __iomem *reg = chip->base;
180 unsigned int shift = off * 2;
183 if (samsung_gpio_is_cfg_special(cfg)) {
191 con = __raw_readl(reg);
192 con &= ~(0x3 << shift);
194 __raw_writel(con, reg);
200 * samsung_gpio_getcfg_2bit - Samsung 2bit style GPIO configuration read.
201 * @chip: The gpio chip that is being configured.
202 * @off: The offset for the GPIO being configured.
204 * The reverse of samsung_gpio_setcfg_2bit(). Will return a value which
205 * could be directly passed back to samsung_gpio_setcfg_2bit(), from the
206 * S3C_GPIO_SPECIAL() macro.
209 static unsigned int samsung_gpio_getcfg_2bit(struct samsung_gpio_chip *chip,
214 con = __raw_readl(chip->base);
218 /* this conversion works for IN and OUT as well as special mode */
219 return S3C_GPIO_SPECIAL(con);
223 * samsung_gpio_setcfg_4bit - Samsung 4bit single register GPIO config.
224 * @chip: The gpio chip that is being configured.
225 * @off: The offset for the GPIO being configured.
226 * @cfg: The configuration value to set.
228 * This helper deal with the GPIO cases where the control register has 4 bits
229 * of control per GPIO, generally in the form of:
232 * others = Special functions (dependent on bank)
234 * Note, since the code to deal with the case where there are two control
235 * registers instead of one, we do not have a separate set of functions for
239 static int samsung_gpio_setcfg_4bit(struct samsung_gpio_chip *chip,
240 unsigned int off, unsigned int cfg)
242 void __iomem *reg = chip->base;
243 unsigned int shift = (off & 7) * 4;
246 if (off < 8 && chip->chip.ngpio > 8)
249 if (samsung_gpio_is_cfg_special(cfg)) {
254 con = __raw_readl(reg);
255 con &= ~(0xf << shift);
257 __raw_writel(con, reg);
263 * samsung_gpio_getcfg_4bit - Samsung 4bit single register GPIO config read.
264 * @chip: The gpio chip that is being configured.
265 * @off: The offset for the GPIO being configured.
267 * The reverse of samsung_gpio_setcfg_4bit(), turning a gpio configuration
268 * register setting into a value the software can use, such as could be passed
269 * to samsung_gpio_setcfg_4bit().
271 * @sa samsung_gpio_getcfg_2bit
274 static unsigned samsung_gpio_getcfg_4bit(struct samsung_gpio_chip *chip,
277 void __iomem *reg = chip->base;
278 unsigned int shift = (off & 7) * 4;
281 if (off < 8 && chip->chip.ngpio > 8)
284 con = __raw_readl(reg);
288 /* this conversion works for IN and OUT as well as special mode */
289 return S3C_GPIO_SPECIAL(con);
292 #ifdef CONFIG_PLAT_S3C24XX
294 * s3c24xx_gpio_setcfg_abank - S3C24XX style GPIO configuration (Bank A)
295 * @chip: The gpio chip that is being configured.
296 * @off: The offset for the GPIO being configured.
297 * @cfg: The configuration value to set.
299 * This helper deal with the GPIO cases where the control register
300 * has one bit of configuration for the gpio, where setting the bit
301 * means the pin is in special function mode and unset means output.
304 static int s3c24xx_gpio_setcfg_abank(struct samsung_gpio_chip *chip,
305 unsigned int off, unsigned int cfg)
307 void __iomem *reg = chip->base;
308 unsigned int shift = off;
311 if (samsung_gpio_is_cfg_special(cfg)) {
314 /* Map output to 0, and SFN2 to 1 */
322 con = __raw_readl(reg);
323 con &= ~(0x1 << shift);
325 __raw_writel(con, reg);
331 * s3c24xx_gpio_getcfg_abank - S3C24XX style GPIO configuration read (Bank A)
332 * @chip: The gpio chip that is being configured.
333 * @off: The offset for the GPIO being configured.
335 * The reverse of s3c24xx_gpio_setcfg_abank() turning an GPIO into a usable
336 * GPIO configuration value.
338 * @sa samsung_gpio_getcfg_2bit
339 * @sa samsung_gpio_getcfg_4bit
342 static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
347 con = __raw_readl(chip->base);
352 return S3C_GPIO_SFN(con);
356 static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
359 for (; nr_chips > 0; nr_chips--, chipcfg++) {
360 if (!chipcfg->set_config)
361 chipcfg->set_config = samsung_gpio_setcfg_4bit;
362 if (!chipcfg->get_config)
363 chipcfg->get_config = samsung_gpio_getcfg_4bit;
364 if (!chipcfg->set_pull)
365 chipcfg->set_pull = samsung_gpio_setpull_updown;
366 if (!chipcfg->get_pull)
367 chipcfg->get_pull = samsung_gpio_getpull_updown;
371 struct samsung_gpio_cfg s3c24xx_gpiocfg_default = {
372 .set_config = samsung_gpio_setcfg_2bit,
373 .get_config = samsung_gpio_getcfg_2bit,
376 #ifdef CONFIG_PLAT_S3C24XX
377 static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
378 .set_config = s3c24xx_gpio_setcfg_abank,
379 .get_config = s3c24xx_gpio_getcfg_abank,
383 static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
398 .set_config = samsung_gpio_setcfg_2bit,
399 .get_config = samsung_gpio_getcfg_2bit,
403 .set_config = samsung_gpio_setcfg_2bit,
404 .get_config = samsung_gpio_getcfg_2bit,
408 .set_config = samsung_gpio_setcfg_2bit,
409 .get_config = samsung_gpio_getcfg_2bit,
412 .set_config = samsung_gpio_setcfg_2bit,
413 .get_config = samsung_gpio_getcfg_2bit,
418 * Default routines for controlling GPIO, based on the original S3C24XX
419 * GPIO functions which deal with the case where each gpio bank of the
420 * chip is as following:
422 * base + 0x00: Control register, 2 bits per gpio
423 * gpio n: 2 bits starting at (2*n)
424 * 00 = input, 01 = output, others mean special-function
425 * base + 0x04: Data register, 1 bit per gpio
429 static int samsung_gpiolib_2bit_input(struct gpio_chip *chip, unsigned offset)
431 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
432 void __iomem *base = ourchip->base;
436 samsung_gpio_lock(ourchip, flags);
438 con = __raw_readl(base + 0x00);
439 con &= ~(3 << (offset * 2));
441 __raw_writel(con, base + 0x00);
443 samsung_gpio_unlock(ourchip, flags);
447 static int samsung_gpiolib_2bit_output(struct gpio_chip *chip,
448 unsigned offset, int value)
450 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
451 void __iomem *base = ourchip->base;
456 samsung_gpio_lock(ourchip, flags);
458 dat = __raw_readl(base + 0x04);
459 dat &= ~(1 << offset);
462 __raw_writel(dat, base + 0x04);
464 con = __raw_readl(base + 0x00);
465 con &= ~(3 << (offset * 2));
466 con |= 1 << (offset * 2);
468 __raw_writel(con, base + 0x00);
469 __raw_writel(dat, base + 0x04);
471 samsung_gpio_unlock(ourchip, flags);
476 * The samsung_gpiolib_4bit routines are to control the gpio banks where
477 * the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
480 * base + 0x00: Control register, 4 bits per gpio
481 * gpio n: 4 bits starting at (4*n)
482 * 0000 = input, 0001 = output, others mean special-function
483 * base + 0x04: Data register, 1 bit per gpio
486 * Note, since the data register is one bit per gpio and is at base + 0x4
487 * we can use samsung_gpiolib_get and samsung_gpiolib_set to change the
488 * state of the output.
491 static int samsung_gpiolib_4bit_input(struct gpio_chip *chip,
494 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
495 void __iomem *base = ourchip->base;
498 con = __raw_readl(base + GPIOCON_OFF);
499 if (ourchip->bitmap_gpio_int & BIT(offset))
500 con |= 0xf << con_4bit_shift(offset);
502 con &= ~(0xf << con_4bit_shift(offset));
503 __raw_writel(con, base + GPIOCON_OFF);
505 pr_debug("%s: %p: CON now %08lx\n", __func__, base, con);
510 static int samsung_gpiolib_4bit_output(struct gpio_chip *chip,
511 unsigned int offset, int value)
513 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
514 void __iomem *base = ourchip->base;
518 con = __raw_readl(base + GPIOCON_OFF);
519 con &= ~(0xf << con_4bit_shift(offset));
520 con |= 0x1 << con_4bit_shift(offset);
522 dat = __raw_readl(base + GPIODAT_OFF);
527 dat &= ~(1 << offset);
529 __raw_writel(dat, base + GPIODAT_OFF);
530 __raw_writel(con, base + GPIOCON_OFF);
531 __raw_writel(dat, base + GPIODAT_OFF);
533 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
539 * The next set of routines are for the case where the GPIO configuration
540 * registers are 4 bits per GPIO but there is more than one register (the
541 * bank has more than 8 GPIOs.
543 * This case is the similar to the 4 bit case, but the registers are as
546 * base + 0x00: Control register, 4 bits per gpio (lower 8 GPIOs)
547 * gpio n: 4 bits starting at (4*n)
548 * 0000 = input, 0001 = output, others mean special-function
549 * base + 0x04: Control register, 4 bits per gpio (up to 8 additions GPIOs)
550 * gpio n: 4 bits starting at (4*n)
551 * 0000 = input, 0001 = output, others mean special-function
552 * base + 0x08: Data register, 1 bit per gpio
555 * To allow us to use the samsung_gpiolib_get and samsung_gpiolib_set
556 * routines we store the 'base + 0x4' address so that these routines see
557 * the data register at ourchip->base + 0x04.
560 static int samsung_gpiolib_4bit2_input(struct gpio_chip *chip,
563 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
564 void __iomem *base = ourchip->base;
565 void __iomem *regcon = base;
573 con = __raw_readl(regcon);
574 con &= ~(0xf << con_4bit_shift(offset));
575 __raw_writel(con, regcon);
577 pr_debug("%s: %p: CON %08lx\n", __func__, base, con);
582 static int samsung_gpiolib_4bit2_output(struct gpio_chip *chip,
583 unsigned int offset, int value)
585 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
586 void __iomem *base = ourchip->base;
587 void __iomem *regcon = base;
590 unsigned con_offset = offset;
597 con = __raw_readl(regcon);
598 con &= ~(0xf << con_4bit_shift(con_offset));
599 con |= 0x1 << con_4bit_shift(con_offset);
601 dat = __raw_readl(base + GPIODAT_OFF);
606 dat &= ~(1 << offset);
608 __raw_writel(dat, base + GPIODAT_OFF);
609 __raw_writel(con, regcon);
610 __raw_writel(dat, base + GPIODAT_OFF);
612 pr_debug("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
617 #ifdef CONFIG_PLAT_S3C24XX
618 /* The next set of routines are for the case of s3c24xx bank a */
620 static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
625 static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
626 unsigned offset, int value)
628 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
629 void __iomem *base = ourchip->base;
634 local_irq_save(flags);
636 con = __raw_readl(base + 0x00);
637 dat = __raw_readl(base + 0x04);
639 dat &= ~(1 << offset);
643 __raw_writel(dat, base + 0x04);
645 con &= ~(1 << offset);
647 __raw_writel(con, base + 0x00);
648 __raw_writel(dat, base + 0x04);
650 local_irq_restore(flags);
655 static void samsung_gpiolib_set(struct gpio_chip *chip,
656 unsigned offset, int value)
658 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
659 void __iomem *base = ourchip->base;
663 samsung_gpio_lock(ourchip, flags);
665 dat = __raw_readl(base + 0x04);
666 dat &= ~(1 << offset);
669 __raw_writel(dat, base + 0x04);
671 samsung_gpio_unlock(ourchip, flags);
674 static int samsung_gpiolib_get(struct gpio_chip *chip, unsigned offset)
676 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
679 val = __raw_readl(ourchip->base + 0x04);
687 * CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios
688 * for use with the configuration calls, and other parts of the s3c gpiolib
691 * Not all s3c support code will need this, as some configurations of cpu
692 * may only support one or two different configuration options and have an
693 * easy gpio to samsung_gpio_chip mapping function. If this is the case, then
694 * the machine support file should provide its own samsung_gpiolib_getchip()
695 * and any other necessary functions.
698 #ifdef CONFIG_S3C_GPIO_TRACK
699 struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END];
701 static __init void s3c_gpiolib_track(struct samsung_gpio_chip *chip)
706 gpn = chip->chip.base;
707 for (i = 0; i < chip->chip.ngpio; i++, gpn++) {
708 BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios));
709 s3c_gpios[gpn] = chip;
712 #endif /* CONFIG_S3C_GPIO_TRACK */
715 * samsung_gpiolib_add() - add the Samsung gpio_chip.
716 * @chip: The chip to register
718 * This is a wrapper to gpiochip_add() that takes our specific gpio chip
719 * information and makes the necessary alterations for the platform and
720 * notes the information for use with the configuration systems and any
721 * other parts of the system.
724 static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip)
726 struct gpio_chip *gc = &chip->chip;
733 spin_lock_init(&chip->lock);
735 if (!gc->direction_input)
736 gc->direction_input = samsung_gpiolib_2bit_input;
737 if (!gc->direction_output)
738 gc->direction_output = samsung_gpiolib_2bit_output;
740 gc->set = samsung_gpiolib_set;
742 gc->get = samsung_gpiolib_get;
745 if (chip->pm != NULL) {
746 if (!chip->pm->save || !chip->pm->resume)
747 pr_err("gpio: %s has missing PM functions\n",
750 pr_err("gpio: %s has no PM function\n", gc->label);
753 /* gpiochip_add() prints own failure message on error. */
754 ret = gpiochip_add_data(gc, chip);
756 s3c_gpiolib_track(chip);
759 static void __init s3c24xx_gpiolib_add_chips(struct samsung_gpio_chip *chip,
760 int nr_chips, void __iomem *base)
763 struct gpio_chip *gc = &chip->chip;
765 for (i = 0 ; i < nr_chips; i++, chip++) {
766 /* skip banks not present on SoC */
767 if (chip->chip.base >= S3C_GPIO_END)
771 chip->config = &s3c24xx_gpiocfg_default;
773 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
774 if ((base != NULL) && (chip->base == NULL))
775 chip->base = base + ((i) * 0x10);
777 if (!gc->direction_input)
778 gc->direction_input = samsung_gpiolib_2bit_input;
779 if (!gc->direction_output)
780 gc->direction_output = samsung_gpiolib_2bit_output;
782 samsung_gpiolib_add(chip);
786 static void __init samsung_gpiolib_add_2bit_chips(struct samsung_gpio_chip *chip,
787 int nr_chips, void __iomem *base,
792 for (i = 0 ; i < nr_chips; i++, chip++) {
793 chip->chip.direction_input = samsung_gpiolib_2bit_input;
794 chip->chip.direction_output = samsung_gpiolib_2bit_output;
797 chip->config = &samsung_gpio_cfgs[7];
799 chip->pm = __gpio_pm(&samsung_gpio_pm_2bit);
800 if ((base != NULL) && (chip->base == NULL))
801 chip->base = base + ((i) * offset);
803 samsung_gpiolib_add(chip);
808 * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config.
809 * @chip: The gpio chip that is being configured.
810 * @nr_chips: The no of chips (gpio ports) for the GPIO being configured.
812 * This helper deal with the GPIO cases where the control register has 4 bits
813 * of control per GPIO, generally in the form of:
816 * others = Special functions (dependent on bank)
818 * Note, since the code to deal with the case where there are two control
819 * registers instead of one, we do not have a separate set of function
820 * (samsung_gpiolib_add_4bit2_chips)for each case.
823 static void __init samsung_gpiolib_add_4bit_chips(struct samsung_gpio_chip *chip,
824 int nr_chips, void __iomem *base)
828 for (i = 0 ; i < nr_chips; i++, chip++) {
829 chip->chip.direction_input = samsung_gpiolib_4bit_input;
830 chip->chip.direction_output = samsung_gpiolib_4bit_output;
833 chip->config = &samsung_gpio_cfgs[2];
835 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
836 if ((base != NULL) && (chip->base == NULL))
837 chip->base = base + ((i) * 0x20);
839 chip->bitmap_gpio_int = 0;
841 samsung_gpiolib_add(chip);
845 static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chip,
848 for (; nr_chips > 0; nr_chips--, chip++) {
849 chip->chip.direction_input = samsung_gpiolib_4bit2_input;
850 chip->chip.direction_output = samsung_gpiolib_4bit2_output;
853 chip->config = &samsung_gpio_cfgs[2];
855 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
857 samsung_gpiolib_add(chip);
861 int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
863 struct samsung_gpio_chip *samsung_chip = gpiochip_get_data(chip);
865 return samsung_chip->irq_base + offset;
868 #ifdef CONFIG_PLAT_S3C24XX
869 static int s3c24xx_gpiolib_fbank_to_irq(struct gpio_chip *chip, unsigned offset)
872 if (soc_is_s3c2412())
873 return IRQ_EINT0_2412 + offset;
875 return IRQ_EINT0 + offset;
879 return IRQ_EINT4 + offset - 4;
885 #ifdef CONFIG_ARCH_S3C64XX
886 static int s3c64xx_gpiolib_mbank_to_irq(struct gpio_chip *chip, unsigned pin)
888 return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
891 static int s3c64xx_gpiolib_lbank_to_irq(struct gpio_chip *chip, unsigned pin)
893 return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
897 struct samsung_gpio_chip s3c24xx_gpios[] = {
898 #ifdef CONFIG_PLAT_S3C24XX
900 .config = &s3c24xx_gpiocfg_banka,
902 .base = S3C2410_GPA(0),
903 .owner = THIS_MODULE,
906 .direction_input = s3c24xx_gpiolib_banka_input,
907 .direction_output = s3c24xx_gpiolib_banka_output,
911 .base = S3C2410_GPB(0),
912 .owner = THIS_MODULE,
918 .base = S3C2410_GPC(0),
919 .owner = THIS_MODULE,
925 .base = S3C2410_GPD(0),
926 .owner = THIS_MODULE,
932 .base = S3C2410_GPE(0),
934 .owner = THIS_MODULE,
939 .base = S3C2410_GPF(0),
940 .owner = THIS_MODULE,
943 .to_irq = s3c24xx_gpiolib_fbank_to_irq,
946 .irq_base = IRQ_EINT8,
948 .base = S3C2410_GPG(0),
949 .owner = THIS_MODULE,
952 .to_irq = samsung_gpiolib_to_irq,
956 .base = S3C2410_GPH(0),
957 .owner = THIS_MODULE,
962 /* GPIOS for the S3C2443 and later devices. */
964 .base = S3C2440_GPJCON,
966 .base = S3C2410_GPJ(0),
967 .owner = THIS_MODULE,
972 .base = S3C2443_GPKCON,
974 .base = S3C2410_GPK(0),
975 .owner = THIS_MODULE,
980 .base = S3C2443_GPLCON,
982 .base = S3C2410_GPL(0),
983 .owner = THIS_MODULE,
988 .base = S3C2443_GPMCON,
990 .base = S3C2410_GPM(0),
991 .owner = THIS_MODULE,
1000 * GPIO bank summary:
1002 * Bank GPIOs Style SlpCon ExtInt Group
1008 * F 16 2Bit Yes 4 [1]
1010 * H 10 4Bit[2] Yes 6
1011 * I 16 2Bit Yes None
1012 * J 12 2Bit Yes None
1013 * K 16 4Bit[2] No None
1014 * L 15 4Bit[2] No None
1015 * M 6 4Bit No IRQ_EINT
1016 * N 16 2Bit No IRQ_EINT
1021 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1022 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1025 static struct samsung_gpio_chip s3c64xx_gpios_4bit[] = {
1026 #ifdef CONFIG_ARCH_S3C64XX
1029 .base = S3C64XX_GPA(0),
1030 .ngpio = S3C64XX_GPIO_A_NR,
1035 .base = S3C64XX_GPB(0),
1036 .ngpio = S3C64XX_GPIO_B_NR,
1041 .base = S3C64XX_GPC(0),
1042 .ngpio = S3C64XX_GPIO_C_NR,
1047 .base = S3C64XX_GPD(0),
1048 .ngpio = S3C64XX_GPIO_D_NR,
1052 .config = &samsung_gpio_cfgs[0],
1054 .base = S3C64XX_GPE(0),
1055 .ngpio = S3C64XX_GPIO_E_NR,
1059 .base = S3C64XX_GPG_BASE,
1061 .base = S3C64XX_GPG(0),
1062 .ngpio = S3C64XX_GPIO_G_NR,
1066 .base = S3C64XX_GPM_BASE,
1067 .config = &samsung_gpio_cfgs[1],
1069 .base = S3C64XX_GPM(0),
1070 .ngpio = S3C64XX_GPIO_M_NR,
1072 .to_irq = s3c64xx_gpiolib_mbank_to_irq,
1078 static struct samsung_gpio_chip s3c64xx_gpios_4bit2[] = {
1079 #ifdef CONFIG_ARCH_S3C64XX
1081 .base = S3C64XX_GPH_BASE + 0x4,
1083 .base = S3C64XX_GPH(0),
1084 .ngpio = S3C64XX_GPIO_H_NR,
1088 .base = S3C64XX_GPK_BASE + 0x4,
1089 .config = &samsung_gpio_cfgs[0],
1091 .base = S3C64XX_GPK(0),
1092 .ngpio = S3C64XX_GPIO_K_NR,
1096 .base = S3C64XX_GPL_BASE + 0x4,
1097 .config = &samsung_gpio_cfgs[1],
1099 .base = S3C64XX_GPL(0),
1100 .ngpio = S3C64XX_GPIO_L_NR,
1102 .to_irq = s3c64xx_gpiolib_lbank_to_irq,
1108 static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1109 #ifdef CONFIG_ARCH_S3C64XX
1111 .base = S3C64XX_GPF_BASE,
1112 .config = &samsung_gpio_cfgs[6],
1114 .base = S3C64XX_GPF(0),
1115 .ngpio = S3C64XX_GPIO_F_NR,
1119 .config = &samsung_gpio_cfgs[7],
1121 .base = S3C64XX_GPI(0),
1122 .ngpio = S3C64XX_GPIO_I_NR,
1126 .config = &samsung_gpio_cfgs[7],
1128 .base = S3C64XX_GPJ(0),
1129 .ngpio = S3C64XX_GPIO_J_NR,
1133 .config = &samsung_gpio_cfgs[6],
1135 .base = S3C64XX_GPO(0),
1136 .ngpio = S3C64XX_GPIO_O_NR,
1140 .config = &samsung_gpio_cfgs[6],
1142 .base = S3C64XX_GPP(0),
1143 .ngpio = S3C64XX_GPIO_P_NR,
1147 .config = &samsung_gpio_cfgs[6],
1149 .base = S3C64XX_GPQ(0),
1150 .ngpio = S3C64XX_GPIO_Q_NR,
1154 .base = S3C64XX_GPN_BASE,
1155 .irq_base = IRQ_EINT(0),
1156 .config = &samsung_gpio_cfgs[5],
1158 .base = S3C64XX_GPN(0),
1159 .ngpio = S3C64XX_GPIO_N_NR,
1161 .to_irq = samsung_gpiolib_to_irq,
1167 /* TODO: cleanup soc_is_* */
1168 static __init int samsung_gpiolib_init(void)
1171 * Currently there are two drivers that can provide GPIO support for
1172 * Samsung SoCs. For device tree enabled platforms, the new
1173 * pinctrl-samsung driver is used, providing both GPIO and pin control
1174 * interfaces. For legacy (non-DT) platforms this driver is used.
1176 if (of_have_populated_dt())
1179 if (soc_is_s3c24xx()) {
1180 samsung_gpiolib_set_cfg(samsung_gpio_cfgs,
1181 ARRAY_SIZE(samsung_gpio_cfgs));
1182 s3c24xx_gpiolib_add_chips(s3c24xx_gpios,
1183 ARRAY_SIZE(s3c24xx_gpios), S3C24XX_VA_GPIO);
1184 } else if (soc_is_s3c64xx()) {
1185 samsung_gpiolib_set_cfg(samsung_gpio_cfgs,
1186 ARRAY_SIZE(samsung_gpio_cfgs));
1187 samsung_gpiolib_add_2bit_chips(s3c64xx_gpios_2bit,
1188 ARRAY_SIZE(s3c64xx_gpios_2bit),
1189 S3C64XX_VA_GPIO + 0xE0, 0x20);
1190 samsung_gpiolib_add_4bit_chips(s3c64xx_gpios_4bit,
1191 ARRAY_SIZE(s3c64xx_gpios_4bit),
1193 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
1194 ARRAY_SIZE(s3c64xx_gpios_4bit2));
1199 core_initcall(samsung_gpiolib_init);
1201 int s3c_gpio_cfgpin(unsigned int pin, unsigned int config)
1203 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1204 unsigned long flags;
1211 offset = pin - chip->chip.base;
1213 samsung_gpio_lock(chip, flags);
1214 ret = samsung_gpio_do_setcfg(chip, offset, config);
1215 samsung_gpio_unlock(chip, flags);
1219 EXPORT_SYMBOL(s3c_gpio_cfgpin);
1221 int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr,
1226 for (; nr > 0; nr--, start++) {
1227 ret = s3c_gpio_cfgpin(start, cfg);
1234 EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range);
1236 int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr,
1237 unsigned int cfg, samsung_gpio_pull_t pull)
1241 for (; nr > 0; nr--, start++) {
1242 s3c_gpio_setpull(start, pull);
1243 ret = s3c_gpio_cfgpin(start, cfg);
1250 EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range);
1252 unsigned s3c_gpio_getcfg(unsigned int pin)
1254 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1255 unsigned long flags;
1260 offset = pin - chip->chip.base;
1262 samsung_gpio_lock(chip, flags);
1263 ret = samsung_gpio_do_getcfg(chip, offset);
1264 samsung_gpio_unlock(chip, flags);
1269 EXPORT_SYMBOL(s3c_gpio_getcfg);
1271 int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull)
1273 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1274 unsigned long flags;
1280 offset = pin - chip->chip.base;
1282 samsung_gpio_lock(chip, flags);
1283 ret = samsung_gpio_do_setpull(chip, offset, pull);
1284 samsung_gpio_unlock(chip, flags);
1288 EXPORT_SYMBOL(s3c_gpio_setpull);
1290 samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
1292 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
1293 unsigned long flags;
1298 offset = pin - chip->chip.base;
1300 samsung_gpio_lock(chip, flags);
1301 pup = samsung_gpio_do_getpull(chip, offset);
1302 samsung_gpio_unlock(chip, flags);
1305 return (__force samsung_gpio_pull_t)pup;
1307 EXPORT_SYMBOL(s3c_gpio_getpull);
1309 #ifdef CONFIG_PLAT_S3C24XX
1310 unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
1312 unsigned long flags;
1313 unsigned long misccr;
1315 local_irq_save(flags);
1316 misccr = __raw_readl(S3C24XX_MISCCR);
1319 __raw_writel(misccr, S3C24XX_MISCCR);
1320 local_irq_restore(flags);
1324 EXPORT_SYMBOL(s3c2410_modify_misccr);