1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/pxa3xx.c
5 * code specific to pxa3xx aka Monahans
7 * Copyright (C) 2006 Marvell International Ltd.
9 * 2007-09-02: eric miao <eric.miao@marvell.com>
12 #include <linux/dmaengine.h>
13 #include <linux/dma/pxa-dma.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/gpio-pxa.h>
19 #include <linux/platform_device.h>
20 #include <linux/irq.h>
21 #include <linux/irqchip.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/platform_data/i2c-pxa.h>
26 #include <linux/platform_data/mmp_dma.h>
27 #include <linux/soc/pxa/cpu.h>
28 #include <linux/clk/pxa.h>
30 #include <asm/mach/map.h>
31 #include <asm/suspend.h>
32 #include "pxa3xx-regs.h"
34 #include <linux/platform_data/usb-ohci-pxa27x.h>
43 #define PECR_IE(n) ((1 << ((n) * 2)) << 28)
44 #define PECR_IS(n) ((1 << ((n) * 2)) << 29)
46 extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int));
49 * NAND NFC: DFI bus arbitration subset
51 #define NDCR (*(volatile u32 __iomem*)(NAND_VIRT + 0))
52 #define NDCR_ND_ARB_EN (1 << 12)
53 #define NDCR_ND_ARB_CNTL (1 << 19)
55 #define CKEN_BOOT 11 /* < Boot rom clock enable */
56 #define CKEN_TPM 19 /* < TPM clock enable */
57 #define CKEN_HSIO2 41 /* < HSIO2 clock enable */
61 #define ISRAM_START 0x5c000000
62 #define ISRAM_SIZE SZ_256K
64 static void __iomem *sram;
65 static unsigned long wakeup_src;
68 * Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
69 * memory controller has to be reinitialised, so we place some code
70 * in the SRAM to perform this function.
72 * We disable FIQs across the standby - otherwise, we might receive a
73 * FIQ while the SDRAM is unavailable.
75 static void pxa3xx_cpu_standby(unsigned int pwrmode)
77 void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
79 memcpy_toio(sram + 0x8000, pm_enter_standby_start,
80 pm_enter_standby_end - pm_enter_standby_start);
98 * NOTE: currently, the OBM (OEM Boot Module) binary comes along with
99 * PXA3xx development kits assumes that the resuming process continues
100 * with the address stored within the first 4 bytes of SDRAM. The PSPR
101 * register is used privately by BootROM and OBM, and _must_ be set to
102 * 0x5c014000 for the moment.
104 static void pxa3xx_cpu_pm_suspend(void)
106 volatile unsigned long *p = (volatile void *)0xc0000000;
107 unsigned long saved_data = *p;
108 #ifndef CONFIG_IWMMXT
111 #ifdef CONFIG_CC_IS_GCC
112 asm volatile(".arch_extension xscale\n\t"
113 "mra %Q0, %R0, acc0" : "=r" (acc0));
115 asm volatile("mrrc p0, 0, %Q0, %R0, c0" : "=r" (acc0));
119 /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
120 CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
121 CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
123 /* clear and setup wakeup source */
129 PCFR |= (1u << 13); /* L1_DIS */
130 PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
134 /* overwrite with the resume address */
135 *p = __pa_symbol(cpu_resume);
137 cpu_suspend(0, pxa3xx_finish_suspend);
143 #ifndef CONFIG_IWMMXT
144 #ifndef CONFIG_AS_IS_LLVM
145 asm volatile(".arch_extension xscale\n\t"
146 "mar acc0, %Q0, %R0" : "=r" (acc0));
148 asm volatile("mcrr p0, 0, %Q0, %R0, c0" :: "r" (acc0));
153 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
156 * Don't sleep if no wakeup sources are defined
158 if (wakeup_src == 0) {
159 printk(KERN_ERR "Not suspending: no wakeup sources\n");
164 case PM_SUSPEND_STANDBY:
165 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
169 pxa3xx_cpu_pm_suspend();
174 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
176 return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
179 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
180 .valid = pxa3xx_cpu_pm_valid,
181 .enter = pxa3xx_cpu_pm_enter,
184 static void __init pxa3xx_init_pm(void)
186 sram = ioremap(ISRAM_START, ISRAM_SIZE);
188 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
193 * Since we copy wakeup code into the SRAM, we need to ensure
194 * that it is preserved over the low power modes. Note: bit 8
195 * is undocumented in the developer manual, but must be set.
197 AD1R |= ADXR_L2 | ADXR_R0;
198 AD2R |= ADXR_L2 | ADXR_R0;
199 AD3R |= ADXR_L2 | ADXR_R0;
202 * Clear the resume enable registers.
209 pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
212 static int pxa3xx_set_wake(struct irq_data *d, unsigned int on)
214 unsigned long flags, mask = 0;
218 mask = ADXER_MFP_WSSP3;
231 mask = ADXER_MFP_WAC97;
237 mask = ADXER_MFP_WSSP2;
240 mask = ADXER_MFP_WI2C;
243 mask = ADXER_MFP_WUART3;
246 mask = ADXER_MFP_WUART2;
249 mask = ADXER_MFP_WUART1;
252 mask = ADXER_MFP_WMMC1;
255 mask = ADXER_MFP_WSSP1;
261 mask = ADXER_MFP_WSSP4;
270 mask = ADXER_MFP_WMMC2;
273 mask = ADXER_MFP_WFLASH;
279 mask = ADXER_WEXTWAKE0;
282 mask = ADXER_WEXTWAKE1;
285 mask = ADXER_MFP_GEN12;
291 local_irq_save(flags);
296 local_irq_restore(flags);
301 static inline void pxa3xx_init_pm(void) {}
302 #define pxa3xx_set_wake NULL
305 static void pxa_ack_ext_wakeup(struct irq_data *d)
307 PECR |= PECR_IS(d->irq - IRQ_WAKEUP0);
310 static void pxa_mask_ext_wakeup(struct irq_data *d)
313 PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
316 static void pxa_unmask_ext_wakeup(struct irq_data *d)
319 PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
322 static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type)
324 if (flow_type & IRQ_TYPE_EDGE_RISING)
325 PWER |= 1 << (d->irq - IRQ_WAKEUP0);
327 if (flow_type & IRQ_TYPE_EDGE_FALLING)
328 PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2);
333 static struct irq_chip pxa_ext_wakeup_chip = {
335 .irq_ack = pxa_ack_ext_wakeup,
336 .irq_mask = pxa_mask_ext_wakeup,
337 .irq_unmask = pxa_unmask_ext_wakeup,
338 .irq_set_type = pxa_set_ext_wakeup_type,
341 static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *,
346 for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
347 irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
349 irq_clear_status_flags(irq, IRQ_NOREQUEST);
352 pxa_ext_wakeup_chip.irq_set_wake = fn;
355 static void __init __pxa3xx_init_irq(void)
357 /* enable CP6 access */
359 __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
361 __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
363 pxa_init_ext_wakeup_irq(pxa3xx_set_wake);
366 static int __init __init
367 pxa3xx_dt_init_irq(struct device_node *node, struct device_node *parent)
370 pxa_dt_irq_init(pxa3xx_set_wake);
371 set_handle_irq(ichp_handle_irq);
375 IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq);
377 static struct map_desc pxa3xx_io_desc[] __initdata = {
379 .virtual = (unsigned long)SMEMC_VIRT,
380 .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE),
381 .length = SMEMC_SIZE,
384 .virtual = (unsigned long)NAND_VIRT,
385 .pfn = __phys_to_pfn(NAND_PHYS),
391 void __init pxa3xx_map_io(void)
394 iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc));
395 pxa3xx_get_clk_frequency_khz(1);
398 static int __init pxa3xx_init(void)
402 if (cpu_is_pxa3xx()) {
404 pxa_register_wdt(ARSR);
407 * clear RDH bit every time after reset
409 * Note: the last 3 bits DxS are write-1-to-clear so carefully
410 * preserve them here in case they will be referenced later
412 ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
415 * Disable DFI bus arbitration, to prevent a system bus lock if
416 * somebody disables the NAND clock (unused clock) while this
419 NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL;
423 enable_irq_wake(IRQ_WAKEUP0);
425 enable_irq_wake(IRQ_WAKEUP1);
427 register_syscore_ops(&pxa_irq_syscore_ops);
428 register_syscore_ops(&pxa3xx_mfp_syscore_ops);
434 postcore_initcall(pxa3xx_init);