arch/arm/mach-pxa/mainstone.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/mainstone.c
   3  *
   4  *  Support for the Intel HCDDBBVA0 Development Platform.
   5  *  (go figure how they came up with such name...)
   6  *
   7  *  Author:     Nicolas Pitre
   8  *  Created:    Nov 05, 2002
   9  *  Copyright:  MontaVista Software Inc.
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License version 2 as
  13  *  published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/sched.h>
  21 #include <linux/bitops.h>
  22 #include <linux/fb.h>
  23 #include <linux/ioport.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/partitions.h>
  26
  27 #include <asm/types.h>
  28 #include <asm/setup.h>
  29 #include <asm/memory.h>
  30 #include <asm/mach-types.h>
  31 #include <asm/hardware.h>
  32 #include <asm/irq.h>
  33 #include <asm/sizes.h>
  34
  35 #include <asm/mach/arch.h>
  36 #include <asm/mach/map.h>
  37 #include <asm/mach/irq.h>
  38 #include <asm/mach/flash.h>
  39
  40 #include <asm/arch/pxa-regs.h>
  41 #include <asm/arch/mainstone.h>
  42 #include <asm/arch/audio.h>
  43 #include <asm/arch/pxafb.h>
  44 #include <asm/arch/mmc.h>
  45 #include <asm/arch/irda.h>
  46
  47 #include "generic.h"
  48
  49
  50 static unsigned long mainstone_irq_enabled;
  51
  52 static void mainstone_mask_irq(unsigned int irq)
  53 {
  54         int mainstone_irq = (irq - MAINSTONE_IRQ(0));
  55         MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
  56 }
  57
  58 static void mainstone_unmask_irq(unsigned int irq)
  59 {
  60         int mainstone_irq = (irq - MAINSTONE_IRQ(0));
  61         /* the irq can be acknowledged only if deasserted, so it's done here */
  62         MST_INTSETCLR &= ~(1 << mainstone_irq);
  63         MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
  64 }
  65
  66 static struct irqchip mainstone_irq_chip = {
  67         .ack            = mainstone_mask_irq,
  68         .mask           = mainstone_mask_irq,
  69         .unmask         = mainstone_unmask_irq,
  70 };
  71
  72 static void mainstone_irq_handler(unsigned int irq, struct irqdesc *desc,
  73                                   struct pt_regs *regs)
  74 {
  75         unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
  76         do {
  77                 GEDR(0) = GPIO_bit(0);  /* clear useless edge notification */
  78                 if (likely(pending)) {
  79                         irq = MAINSTONE_IRQ(0) + __ffs(pending);
  80                         desc = irq_desc + irq;
  81                         desc_handle_irq(irq, desc, regs);
  82                 }
  83                 pending = MST_INTSETCLR & mainstone_irq_enabled;
  84         } while (pending);
  85 }
  86
  87 static void __init mainstone_init_irq(void)
  88 {
  89         int irq;
  90
  91         pxa_init_irq();
  92
  93         /* setup extra Mainstone irqs */
  94         for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
  95                 set_irq_chip(irq, &mainstone_irq_chip);
  96                 set_irq_handler(irq, do_level_IRQ);
  97                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  98         }
  99         set_irq_flags(MAINSTONE_IRQ(8), 0);
 100         set_irq_flags(MAINSTONE_IRQ(12), 0);
 101
 102         MST_INTMSKENA = 0;
 103         MST_INTSETCLR = 0;
 104
 105         set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
 106         set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
 107 }
 108
 109 #ifdef CONFIG_PM
 110
 111 static int mainstone_irq_resume(struct sys_device *dev)
 112 {
 113         MST_INTMSKENA = mainstone_irq_enabled;
 114         return 0;
 115 }
 116
 117 static struct sysdev_class mainstone_irq_sysclass = {
 118         set_kset_name("cpld_irq"),
 119         .resume = mainstone_irq_resume,
 120 };
 121
 122 static struct sys_device mainstone_irq_device = {
 123         .cls = &mainstone_irq_sysclass,
 124 };
 125
 126 static int __init mainstone_irq_device_init(void)
 127 {
 128         int ret = sysdev_class_register(&mainstone_irq_sysclass);
 129         if (ret == 0)
 130                 ret = sysdev_register(&mainstone_irq_device);
 131         return ret;
 132 }
 133
 134 device_initcall(mainstone_irq_device_init);
 135
 136 #endif
 137
 138
 139 static struct resource smc91x_resources[] = {
 140         [0] = {
 141                 .start  = (MST_ETH_PHYS + 0x300),
 142                 .end    = (MST_ETH_PHYS + 0xfffff),
 143                 .flags  = IORESOURCE_MEM,
 144         },
 145         [1] = {
 146                 .start  = MAINSTONE_IRQ(3),
 147                 .end    = MAINSTONE_IRQ(3),
 148                 .flags  = IORESOURCE_IRQ,
 149         }
 150 };
 151
 152 static struct platform_device smc91x_device = {
 153         .name           = "smc91x",
 154         .id             = 0,
 155         .num_resources  = ARRAY_SIZE(smc91x_resources),
 156         .resource       = smc91x_resources,
 157 };
 158
 159 static int mst_audio_startup(snd_pcm_substream_t *substream, void *priv)
 160 {
 161         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 162                 MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
 163         return 0;
 164 }
 165
 166 static void mst_audio_shutdown(snd_pcm_substream_t *substream, void *priv)
 167 {
 168         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 169                 MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
 170 }
 171
 172 static long mst_audio_suspend_mask;
 173
 174 static void mst_audio_suspend(void *priv)
 175 {
 176         mst_audio_suspend_mask = MST_MSCWR2;
 177         MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
 178 }
 179
 180 static void mst_audio_resume(void *priv)
 181 {
 182         MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF;
 183 }
 184
 185 static pxa2xx_audio_ops_t mst_audio_ops = {
 186         .startup        = mst_audio_startup,
 187         .shutdown       = mst_audio_shutdown,
 188         .suspend        = mst_audio_suspend,
 189         .resume         = mst_audio_resume,
 190 };
 191
 192 static struct platform_device mst_audio_device = {
 193         .name           = "pxa2xx-ac97",
 194         .id             = -1,
 195         .dev            = { .platform_data = &mst_audio_ops },
 196 };
 197
 198 static struct resource flash_resources[] = {
 199         [0] = {
 200                 .start  = PXA_CS0_PHYS,
 201                 .end    = PXA_CS0_PHYS + SZ_64M - 1,
 202                 .flags  = IORESOURCE_MEM,
 203         },
 204         [1] = {
 205                 .start  = PXA_CS1_PHYS,
 206                 .end    = PXA_CS1_PHYS + SZ_64M - 1,
 207                 .flags  = IORESOURCE_MEM,
 208         },
 209 };
 210
 211 static struct mtd_partition mainstoneflash0_partitions[] = {
 212         {
 213                 .name =         "Bootloader",
 214                 .size =         0x00040000,
 215                 .offset =       0,
 216                 .mask_flags =   MTD_WRITEABLE  /* force read-only */
 217         },{
 218                 .name =         "Kernel",
 219                 .size =         0x00400000,
 220                 .offset =       0x00040000,
 221         },{
 222                 .name =         "Filesystem",
 223                 .size =         MTDPART_SIZ_FULL,
 224                 .offset =       0x00440000
 225         }
 226 };
 227
 228 static struct flash_platform_data mst_flash_data[2] = {
 229         {
 230                 .map_name       = "cfi_probe",
 231                 .parts          = mainstoneflash0_partitions,
 232                 .nr_parts       = ARRAY_SIZE(mainstoneflash0_partitions),
 233         }, {
 234                 .map_name       = "cfi_probe",
 235                 .parts          = NULL,
 236                 .nr_parts       = 0,
 237         }
 238 };
 239
 240 static struct platform_device mst_flash_device[2] = {
 241         {
 242                 .name           = "pxa2xx-flash",
 243                 .id             = 0,
 244                 .dev = {
 245                         .platform_data = &mst_flash_data[0],
 246                 },
 247                 .resource = &flash_resources[0],
 248                 .num_resources = 1,
 249         },
 250         {
 251                 .name           = "pxa2xx-flash",
 252                 .id             = 1,
 253                 .dev = {
 254                         .platform_data = &mst_flash_data[1],
 255                 },
 256                 .resource = &flash_resources[1],
 257                 .num_resources = 1,
 258         },
 259 };
 260
 261 static void mainstone_backlight_power(int on)
 262 {
 263         if (on) {
 264                 pxa_gpio_mode(GPIO16_PWM0_MD);
 265                 pxa_set_cken(CKEN0_PWM0, 1);
 266                 PWM_CTRL0 = 0;
 267                 PWM_PWDUTY0 = 0x3ff;
 268                 PWM_PERVAL0 = 0x3ff;
 269         } else {
 270                 PWM_CTRL0 = 0;
 271                 PWM_PWDUTY0 = 0x0;
 272                 PWM_PERVAL0 = 0x3FF;
 273                 pxa_set_cken(CKEN0_PWM0, 0);
 274         }
 275 }
 276
 277 static struct pxafb_mach_info toshiba_ltm04c380k __initdata = {
 278         .pixclock               = 50000,
 279         .xres                   = 640,
 280         .yres                   = 480,
 281         .bpp                    = 16,
 282         .hsync_len              = 1,
 283         .left_margin            = 0x9f,
 284         .right_margin           = 1,
 285         .vsync_len              = 44,
 286         .upper_margin           = 0,
 287         .lower_margin           = 0,
 288         .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
 289         .lccr0                  = LCCR0_Act,
 290         .lccr3                  = LCCR3_PCP,
 291         .pxafb_backlight_power  = mainstone_backlight_power,
 292 };
 293
 294 static struct pxafb_mach_info toshiba_ltm035a776c __initdata = {
 295         .pixclock               = 110000,
 296         .xres                   = 240,
 297         .yres                   = 320,
 298         .bpp                    = 16,
 299         .hsync_len              = 4,
 300         .left_margin            = 8,
 301         .right_margin           = 20,
 302         .vsync_len              = 3,
 303         .upper_margin           = 1,
 304         .lower_margin           = 10,
 305         .sync                   = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
 306         .lccr0                  = LCCR0_Act,
 307         .lccr3                  = LCCR3_PCP,
 308         .pxafb_backlight_power  = mainstone_backlight_power,
 309 };
 310
 311 static int mainstone_mci_init(struct device *dev, irqreturn_t (*mstone_detect_int)(int, void *, struct pt_regs *), void *data)
 312 {
 313         int err;
 314
 315         /*
 316          * setup GPIO for PXA27x MMC controller
 317          */
 318         pxa_gpio_mode(GPIO32_MMCCLK_MD);
 319         pxa_gpio_mode(GPIO112_MMCCMD_MD);
 320         pxa_gpio_mode(GPIO92_MMCDAT0_MD);
 321         pxa_gpio_mode(GPIO109_MMCDAT1_MD);
 322         pxa_gpio_mode(GPIO110_MMCDAT2_MD);
 323         pxa_gpio_mode(GPIO111_MMCDAT3_MD);
 324
 325         /* make sure SD/Memory Stick multiplexer's signals
 326          * are routed to MMC controller
 327          */
 328         MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
 329
 330         err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, SA_INTERRUPT,
 331                              "MMC card detect", data);
 332         if (err) {
 333                 printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
 334                 return -1;
 335         }
 336
 337         return 0;
 338 }
 339
 340 static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
 341 {
 342         struct pxamci_platform_data* p_d = dev->platform_data;
 343
 344         if (( 1 << vdd) & p_d->ocr_mask) {
 345                 printk(KERN_DEBUG "%s: on\n", __FUNCTION__);
 346                 MST_MSCWR1 |= MST_MSCWR1_MMC_ON;
 347                 MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
 348         } else {
 349                 printk(KERN_DEBUG "%s: off\n", __FUNCTION__);
 350                 MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
 351         }
 352 }
 353
 354 static void mainstone_mci_exit(struct device *dev, void *data)
 355 {
 356         free_irq(MAINSTONE_MMC_IRQ, data);
 357 }
 358
 359 static struct pxamci_platform_data mainstone_mci_platform_data = {
 360         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 361         .init           = mainstone_mci_init,
 362         .setpower       = mainstone_mci_setpower,
 363         .exit           = mainstone_mci_exit,
 364 };
 365
 366 static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
 367 {
 368         unsigned long flags;
 369
 370         local_irq_save(flags);
 371         if (mode & IR_SIRMODE) {
 372                 MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
 373         } else if (mode & IR_FIRMODE) {
 374                 MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR;
 375         }
 376         if (mode & IR_OFF) {
 377                 MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF;
 378         } else {
 379                 MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL;
 380         }
 381         local_irq_restore(flags);
 382 }
 383
 384 static struct pxaficp_platform_data mainstone_ficp_platform_data = {
 385         .transceiver_cap  = IR_SIRMODE | IR_FIRMODE | IR_OFF,
 386         .transceiver_mode = mainstone_irda_transceiver_mode,
 387 };
 388
 389 static struct platform_device *platform_devices[] __initdata = {
 390         &smc91x_device,
 391         &mst_audio_device,
 392         &mst_flash_device[0],
 393         &mst_flash_device[1],
 394 };
 395
 396 static void __init mainstone_init(void)
 397 {
 398         int SW7 = 0;  /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
 399
 400         mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
 401         mst_flash_data[1].width = 4;
 402
 403         /* Compensate for SW7 which swaps the flash banks */
 404         mst_flash_data[SW7].name = "processor-flash";
 405         mst_flash_data[SW7 ^ 1].name = "mainboard-flash";
 406
 407         printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
 408                mst_flash_data[0].name);
 409
 410         /*
 411          * On Mainstone, we route AC97_SYSCLK via GPIO45 to
 412          * the audio daughter card
 413          */
 414         pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
 415
 416         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 417
 418         /* reading Mainstone's "Virtual Configuration Register"
 419            might be handy to select LCD type here */
 420         if (0)
 421                 set_pxa_fb_info(&toshiba_ltm04c380k);
 422         else
 423                 set_pxa_fb_info(&toshiba_ltm035a776c);
 424
 425         pxa_set_mci_info(&mainstone_mci_platform_data);
 426         pxa_set_ficp_info(&mainstone_ficp_platform_data);
 427 }
 428
 429
 430 static struct map_desc mainstone_io_desc[] __initdata = {
 431         {       /* CPLD */
 432                 .virtual        =  MST_FPGA_VIRT,
 433                 .pfn            = __phys_to_pfn(MST_FPGA_PHYS),
 434                 .length         = 0x00100000,
 435                 .type           = MT_DEVICE
 436         }
 437 };
 438
 439 static void __init mainstone_map_io(void)
 440 {
 441         pxa_map_io();
 442         iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
 443
 444         /* initialize sleep mode regs (wake-up sources, etc) */
 445         PGSR0 = 0x00008800;
 446         PGSR1 = 0x00000002;
 447         PGSR2 = 0x0001FC00;
 448         PGSR3 = 0x00001F81;
 449         PWER  = 0xC0000002;
 450         PRER  = 0x00000002;
 451         PFER  = 0x00000002;
 452         /*      for use I SRAM as framebuffer.  */
 453         PSLR |= 0xF04;
 454         PCFR = 0x66;
 455         /*      For Keypad wakeup.      */
 456         KPC &=~KPC_ASACT;
 457         KPC |=KPC_AS;
 458         PKWR  = 0x000FD000;
 459         /*      Need read PKWR back after set it.       */
 460         PKWR;
 461 }
 462
 463 MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
 464         /* Maintainer: MontaVista Software Inc. */
 465         .phys_ram       = 0xa0000000,
 466         .phys_io        = 0x40000000,
 467         .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
 468         .map_io         = mainstone_map_io,
 469         .init_irq       = mainstone_init_irq,
 470         .timer          = &pxa_timer,
 471         .init_machine   = mainstone_init,
 472 MACHINE_END