2 * linux/arch/arm/mach-omap2/timer.c
4 * OMAP2 GP timer support.
6 * Copyright (C) 2009 Nokia Corporation
8 * Update to use new clocksource/clockevent layers
9 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
10 * Copyright (C) 2007 MontaVista Software, Inc.
13 * Copyright (C) 2005 Nokia Corporation
14 * Author: Paul Mundt <paul.mundt@nokia.com>
15 * Juha Yrjölä <juha.yrjola@nokia.com>
16 * OMAP Dual-mode timer framework support by Timo Teras
18 * Some parts based off of TI's 24xx code:
20 * Copyright (C) 2004-2009 Texas Instruments, Inc.
22 * Roughly modelled after the OMAP1 MPU timer code.
23 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 * This file is subject to the terms and conditions of the GNU General Public
26 * License. See the file "COPYING" in the main directory of this archive
29 #include <linux/init.h>
30 #include <linux/time.h>
31 #include <linux/interrupt.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/delay.h>
35 #include <linux/irq.h>
36 #include <linux/clocksource.h>
37 #include <linux/clockchips.h>
38 #include <linux/slab.h>
40 #include <linux/of_address.h>
41 #include <linux/of_irq.h>
42 #include <linux/platform_device.h>
43 #include <linux/platform_data/dmtimer-omap.h>
44 #include <linux/sched_clock.h>
46 #include <asm/mach/time.h>
47 #include <asm/smp_twd.h>
49 #include "omap_hwmod.h"
50 #include "omap_device.h"
51 #include <plat/counter-32k.h>
52 #include <clocksource/timer-ti-dm.h>
57 #include "powerdomain.h"
58 #include "omap-secure.h"
60 #define REALTIME_COUNTER_BASE 0x48243200
61 #define INCREMENTER_NUMERATOR_OFFSET 0x10
62 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
63 #define NUMERATOR_DENUMERATOR_MASK 0xfffff000
67 static struct omap_dm_timer clkev;
68 static struct clock_event_device clockevent_gpt;
70 /* Clockevent hwmod for am335x and am437x suspend */
71 static struct omap_hwmod *clockevent_gpt_hwmod;
73 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
74 static unsigned long arch_timer_freq;
76 void set_cntfreq(void)
78 omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
82 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
84 struct clock_event_device *evt = &clockevent_gpt;
86 __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
88 evt->event_handler(evt);
92 static struct irqaction omap2_gp_timer_irq = {
94 .flags = IRQF_TIMER | IRQF_IRQPOLL,
95 .handler = omap2_gp_timer_interrupt,
98 static int omap2_gp_timer_set_next_event(unsigned long cycles,
99 struct clock_event_device *evt)
101 __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
102 0xffffffff - cycles, OMAP_TIMER_POSTED);
107 static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
109 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
113 static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
117 __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
119 period = clkev.rate / HZ;
121 /* Looks like we need to first set the load value separately */
122 __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
124 __omap_dm_timer_load_start(&clkev,
125 OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
126 0xffffffff - period, OMAP_TIMER_POSTED);
130 static void omap_clkevt_idle(struct clock_event_device *unused)
132 if (!clockevent_gpt_hwmod)
135 omap_hwmod_idle(clockevent_gpt_hwmod);
138 static void omap_clkevt_unidle(struct clock_event_device *unused)
140 if (!clockevent_gpt_hwmod)
143 omap_hwmod_enable(clockevent_gpt_hwmod);
144 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
147 static struct clock_event_device clockevent_gpt = {
148 .features = CLOCK_EVT_FEAT_PERIODIC |
149 CLOCK_EVT_FEAT_ONESHOT,
151 .set_next_event = omap2_gp_timer_set_next_event,
152 .set_state_shutdown = omap2_gp_timer_shutdown,
153 .set_state_periodic = omap2_gp_timer_set_periodic,
154 .set_state_oneshot = omap2_gp_timer_shutdown,
155 .tick_resume = omap2_gp_timer_shutdown,
158 static const struct of_device_id omap_timer_match[] __initconst = {
159 { .compatible = "ti,omap2420-timer", },
160 { .compatible = "ti,omap3430-timer", },
161 { .compatible = "ti,omap4430-timer", },
162 { .compatible = "ti,omap5430-timer", },
163 { .compatible = "ti,dm814-timer", },
164 { .compatible = "ti,dm816-timer", },
165 { .compatible = "ti,am335x-timer", },
166 { .compatible = "ti,am335x-timer-1ms", },
171 * omap_get_timer_dt - get a timer using device-tree
172 * @match - device-tree match structure for matching a device type
173 * @property - optional timer property to match
175 * Helper function to get a timer during early boot using device-tree for use
176 * as kernel system timer. Optionally, the property argument can be used to
177 * select a timer with a specific property. Once a timer is found then mark
178 * the timer node in device-tree as disabled, to prevent the kernel from
179 * registering this timer as a platform device and so no one else can use it.
181 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
182 const char *property)
184 struct device_node *np;
186 for_each_matching_node(np, match) {
187 if (!of_device_is_available(np))
190 if (property && !of_get_property(np, property, NULL))
193 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
194 of_get_property(np, "ti,timer-dsp", NULL) ||
195 of_get_property(np, "ti,timer-pwm", NULL) ||
196 of_get_property(np, "ti,timer-secure", NULL)))
199 if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
200 struct property *prop;
202 prop = kzalloc(sizeof(*prop), GFP_KERNEL);
205 prop->name = "status";
206 prop->value = "disabled";
207 prop->length = strlen(prop->value);
208 of_add_property(np, prop);
217 * omap_dmtimer_init - initialisation function when device tree is used
219 * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
220 * cannot be used by the kernel as they are reserved. Therefore, to prevent the
221 * kernel registering these devices remove them dynamically from the device
224 static void __init omap_dmtimer_init(void)
226 struct device_node *np;
228 if (!cpu_is_omap34xx() && !soc_is_dra7xx())
231 /* If we are a secure device, remove any secure timer nodes */
232 if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
233 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
239 * omap_dm_timer_get_errata - get errata flags for a timer
241 * Get the timer errata flags that are specific to the OMAP device being used.
243 static u32 __init omap_dm_timer_get_errata(void)
245 if (cpu_is_omap24xx())
248 return OMAP_TIMER_ERRATA_I103_I767;
251 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
252 const char *fck_source,
253 const char *property,
254 const char **timer_name,
257 const char *oh_name = NULL;
258 struct device_node *np;
259 struct omap_hwmod *oh;
263 np = omap_get_timer_dt(omap_timer_match, property);
267 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
271 timer->irq = irq_of_parse_and_map(np, 0);
275 timer->io_base = of_iomap(np, 0);
277 timer->fclk = of_clk_get_by_name(np, "fck");
281 oh = omap_hwmod_lookup(oh_name);
285 *timer_name = oh->name;
290 omap_hwmod_setup_one(oh_name);
292 /* After the dmtimer is using hwmod these clocks won't be needed */
293 if (IS_ERR_OR_NULL(timer->fclk))
294 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
295 if (IS_ERR(timer->fclk))
296 return PTR_ERR(timer->fclk);
298 src = clk_get(NULL, fck_source);
302 WARN(clk_set_parent(timer->fclk, src) < 0,
303 "Cannot set timer parent clock, no PLL clock driver?");
307 omap_hwmod_enable(oh);
308 __omap_dm_timer_init_regs(timer);
311 __omap_dm_timer_enable_posted(timer);
313 /* Check that the intended posted configuration matches the actual */
314 if (posted != timer->posted)
317 timer->rate = clk_get_rate(timer->fclk);
323 #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
324 void tick_broadcast(const struct cpumask *mask)
329 static void __init omap2_gp_clockevent_init(int gptimer_id,
330 const char *fck_source,
331 const char *property)
335 clkev.id = gptimer_id;
336 clkev.errata = omap_dm_timer_get_errata();
339 * For clock-event timers we never read the timer counter and
340 * so we are not impacted by errata i103 and i767. Therefore,
341 * we can safely ignore this errata for clock-event timers.
343 __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
345 res = omap_dm_timer_init_one(&clkev, fck_source, property,
346 &clockevent_gpt.name, OMAP_TIMER_POSTED);
349 omap2_gp_timer_irq.dev_id = &clkev;
350 setup_irq(clkev.irq, &omap2_gp_timer_irq);
352 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
354 clockevent_gpt.cpumask = cpu_possible_mask;
355 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
356 clockevents_config_and_register(&clockevent_gpt, clkev.rate,
357 3, /* Timer internal resynch latency */
360 if (soc_is_am33xx() || soc_is_am43xx()) {
361 clockevent_gpt.suspend = omap_clkevt_idle;
362 clockevent_gpt.resume = omap_clkevt_unidle;
364 clockevent_gpt_hwmod =
365 omap_hwmod_lookup(clockevent_gpt.name);
368 pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
372 /* Clocksource code */
373 static struct omap_dm_timer clksrc;
374 static bool use_gptimer_clksrc __initdata;
379 static u64 clocksource_read_cycles(struct clocksource *cs)
381 return (u64)__omap_dm_timer_read_counter(&clksrc,
382 OMAP_TIMER_NONPOSTED);
385 static struct clocksource clocksource_gpt = {
387 .read = clocksource_read_cycles,
388 .mask = CLOCKSOURCE_MASK(32),
389 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
392 static u64 notrace dmtimer_read_sched_clock(void)
395 return __omap_dm_timer_read_counter(&clksrc,
396 OMAP_TIMER_NONPOSTED);
401 static const struct of_device_id omap_counter_match[] __initconst = {
402 { .compatible = "ti,omap-counter32k", },
406 /* Setup free-running counter for clocksource */
407 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
410 struct device_node *np = NULL;
411 struct omap_hwmod *oh;
412 const char *oh_name = "counter_32k";
415 * See if the 32kHz counter is supported.
417 np = omap_get_timer_dt(omap_counter_match, NULL);
421 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
426 * First check hwmod data is available for sync32k counter
428 oh = omap_hwmod_lookup(oh_name);
429 if (!oh || oh->slaves_cnt == 0)
432 omap_hwmod_setup_one(oh_name);
434 ret = omap_hwmod_enable(oh);
436 pr_warn("%s: failed to enable counter_32k module (%d)\n",
444 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
445 const char *fck_source,
446 const char *property)
450 clksrc.id = gptimer_id;
451 clksrc.errata = omap_dm_timer_get_errata();
453 res = omap_dm_timer_init_one(&clksrc, fck_source, property,
454 &clocksource_gpt.name,
455 OMAP_TIMER_NONPOSTED);
458 __omap_dm_timer_load_start(&clksrc,
459 OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
460 OMAP_TIMER_NONPOSTED);
461 sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
463 if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
464 pr_err("Could not register clocksource %s\n",
465 clocksource_gpt.name);
467 pr_info("OMAP clocksource: %s at %lu Hz\n",
468 clocksource_gpt.name, clksrc.rate);
471 static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
472 const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
473 const char *clksrc_prop, bool gptimer)
477 omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
479 /* Enable the use of clocksource="gp_timer" kernel parameter */
480 if (use_gptimer_clksrc || gptimer)
481 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
484 omap2_sync32k_clocksource_init();
487 void __init omap_init_time(void)
489 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
490 2, "timer_sys_ck", NULL, false);
495 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
496 void __init omap3_secure_sync32k_timer_init(void)
498 __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
499 2, "timer_sys_ck", NULL, false);
503 #endif /* CONFIG_ARCH_OMAP3 */
505 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
506 defined(CONFIG_SOC_AM43XX)
507 void __init omap3_gptimer_timer_init(void)
509 __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
510 1, "timer_sys_ck", "ti,timer-alwon", true);
511 if (of_have_populated_dt())
516 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
517 defined(CONFIG_SOC_DRA7XX)
518 static void __init omap4_sync32k_timer_init(void)
520 __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
521 2, "sys_clkin_ck", NULL, false);
524 void __init omap4_local_timer_init(void)
526 omap4_sync32k_timer_init();
531 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
534 * The realtime counter also called master counter, is a free-running
535 * counter, which is related to real time. It produces the count used
536 * by the CPU local timer peripherals in the MPU cluster. The timer counts
537 * at a rate of 6.144 MHz. Because the device operates on different clocks
538 * in different power modes, the master counter shifts operation between
539 * clocks, adjusting the increment per clock in hardware accordingly to
540 * maintain a constant count rate.
542 static void __init realtime_counter_init(void)
544 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
546 static struct clk *sys_clk;
549 unsigned long long num, den;
551 base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
553 pr_err("%s: ioremap failed\n", __func__);
556 sys_clk = clk_get(NULL, "sys_clkin");
557 if (IS_ERR(sys_clk)) {
558 pr_err("%s: failed to get system clock handle\n", __func__);
563 rate = clk_get_rate(sys_clk);
565 if (soc_is_dra7xx()) {
567 * Errata i856 says the 32.768KHz crystal does not start at
568 * power on, so the CPU falls back to an emulated 32KHz clock
569 * based on sysclk / 610 instead. This causes the master counter
570 * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
571 * (OR sysclk * 75 / 244)
573 * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
574 * Of course any board built without a populated 32.768KHz
575 * crystal would also need this fix even if the CPU is fixed
578 * Either case can be detected by using the two speedselect bits
579 * If they are not 0, then the 32.768KHz clock driving the
580 * coarse counter that corrects the fine counter every time it
581 * ticks is actually rate/610 rather than 32.768KHz and we
582 * should compensate to avoid the 570ppm (at 20MHz, much worse
583 * at other rates) too fast system time.
585 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
586 if (reg & DRA7_SPEEDSELECT_MASK) {
593 /* Numerator/denumerator values refer TRM Realtime Counter section */
621 /* Program it for 38.4 MHz */
628 /* Program numerator and denumerator registers */
629 reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
630 NUMERATOR_DENUMERATOR_MASK;
632 writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
634 reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
635 NUMERATOR_DENUMERATOR_MASK;
637 writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
639 arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
646 void __init omap5_realtime_timer_init(void)
648 omap4_sync32k_timer_init();
649 realtime_counter_init();
653 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
656 * omap2_override_clocksource - clocksource override with user configuration
658 * Allows user to override default clocksource, using kernel parameter
659 * clocksource="gp_timer" (For all OMAP2PLUS architectures)
661 * Note that, here we are using same standard kernel parameter "clocksource=",
662 * and not introducing any OMAP specific interface.
664 static int __init omap2_override_clocksource(char *str)
669 * For OMAP architecture, we only have two options
670 * - sync_32k (default)
671 * - gp_timer (sys_clk based)
673 if (!strcmp(str, "gp_timer"))
674 use_gptimer_clksrc = true;
678 early_param("clocksource", omap2_override_clocksource);