arch/arm/mach-omap2/timer.c

   1 /*
   2  * linux/arch/arm/mach-omap2/timer.c
   3  *
   4  * OMAP2 GP timer support.
   5  *
   6  * Copyright (C) 2009 Nokia Corporation
   7  *
   8  * Update to use new clocksource/clockevent layers
   9  * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
  10  * Copyright (C) 2007 MontaVista Software, Inc.
  11  *
  12  * Original driver:
  13  * Copyright (C) 2005 Nokia Corporation
  14  * Author: Paul Mundt <paul.mundt@nokia.com>
  15  *         Juha Yrjölä <juha.yrjola@nokia.com>
  16  * OMAP Dual-mode timer framework support by Timo Teras
  17  *
  18  * Some parts based off of TI's 24xx code:
  19  *
  20  * Copyright (C) 2004-2009 Texas Instruments, Inc.
  21  *
  22  * Roughly modelled after the OMAP1 MPU timer code.
  23  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  24  *
  25  * This file is subject to the terms and conditions of the GNU General Public
  26  * License. See the file "COPYING" in the main directory of this archive
  27  * for more details.
  28  */
  29 #include <linux/init.h>
  30 #include <linux/time.h>
  31 #include <linux/interrupt.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/delay.h>
  35 #include <linux/irq.h>
  36 #include <linux/clocksource.h>
  37 #include <linux/clockchips.h>
  38 #include <linux/slab.h>
  39 #include <linux/of.h>
  40 #include <linux/of_address.h>
  41 #include <linux/of_irq.h>
  42 #include <linux/platform_device.h>
  43 #include <linux/platform_data/dmtimer-omap.h>
  44 #include <linux/sched_clock.h>
  45
  46 #include <asm/mach/time.h>
  47 #include <asm/smp_twd.h>
  48
  49 #include "omap_hwmod.h"
  50 #include "omap_device.h"
  51 #include <plat/counter-32k.h>
  52 #include <clocksource/timer-ti-dm.h>
  53
  54 #include "soc.h"
  55 #include "common.h"
  56 #include "control.h"
  57 #include "powerdomain.h"
  58 #include "omap-secure.h"
  59
  60 #define REALTIME_COUNTER_BASE                           0x48243200
  61 #define INCREMENTER_NUMERATOR_OFFSET                    0x10
  62 #define INCREMENTER_DENUMERATOR_RELOAD_OFFSET           0x14
  63 #define NUMERATOR_DENUMERATOR_MASK                      0xfffff000
  64
  65 /* Clockevent code */
  66
  67 static struct omap_dm_timer clkev;
  68 static struct clock_event_device clockevent_gpt;
  69
  70 /* Clockevent hwmod for am335x and am437x suspend */
  71 static struct omap_hwmod *clockevent_gpt_hwmod;
  72
  73 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
  74 static unsigned long arch_timer_freq;
  75
  76 void set_cntfreq(void)
  77 {
  78         omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
  79 }
  80 #endif
  81
  82 static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
  83 {
  84         struct clock_event_device *evt = &clockevent_gpt;
  85
  86         __omap_dm_timer_write_status(&clkev, OMAP_TIMER_INT_OVERFLOW);
  87
  88         evt->event_handler(evt);
  89         return IRQ_HANDLED;
  90 }
  91
  92 static struct irqaction omap2_gp_timer_irq = {
  93         .name           = "gp_timer",
  94         .flags          = IRQF_TIMER | IRQF_IRQPOLL,
  95         .handler        = omap2_gp_timer_interrupt,
  96 };
  97
  98 static int omap2_gp_timer_set_next_event(unsigned long cycles,
  99                                          struct clock_event_device *evt)
 100 {
 101         __omap_dm_timer_load_start(&clkev, OMAP_TIMER_CTRL_ST,
 102                                    0xffffffff - cycles, OMAP_TIMER_POSTED);
 103
 104         return 0;
 105 }
 106
 107 static int omap2_gp_timer_shutdown(struct clock_event_device *evt)
 108 {
 109         __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
 110         return 0;
 111 }
 112
 113 static int omap2_gp_timer_set_periodic(struct clock_event_device *evt)
 114 {
 115         u32 period;
 116
 117         __omap_dm_timer_stop(&clkev, OMAP_TIMER_POSTED, clkev.rate);
 118
 119         period = clkev.rate / HZ;
 120         period -= 1;
 121         /* Looks like we need to first set the load value separately */
 122         __omap_dm_timer_write(&clkev, OMAP_TIMER_LOAD_REG, 0xffffffff - period,
 123                               OMAP_TIMER_POSTED);
 124         __omap_dm_timer_load_start(&clkev,
 125                                    OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
 126                                    0xffffffff - period, OMAP_TIMER_POSTED);
 127         return 0;
 128 }
 129
 130 static void omap_clkevt_idle(struct clock_event_device *unused)
 131 {
 132         if (!clockevent_gpt_hwmod)
 133                 return;
 134
 135         omap_hwmod_idle(clockevent_gpt_hwmod);
 136 }
 137
 138 static void omap_clkevt_unidle(struct clock_event_device *unused)
 139 {
 140         if (!clockevent_gpt_hwmod)
 141                 return;
 142
 143         omap_hwmod_enable(clockevent_gpt_hwmod);
 144         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 145 }
 146
 147 static struct clock_event_device clockevent_gpt = {
 148         .features               = CLOCK_EVT_FEAT_PERIODIC |
 149                                   CLOCK_EVT_FEAT_ONESHOT,
 150         .rating                 = 300,
 151         .set_next_event         = omap2_gp_timer_set_next_event,
 152         .set_state_shutdown     = omap2_gp_timer_shutdown,
 153         .set_state_periodic     = omap2_gp_timer_set_periodic,
 154         .set_state_oneshot      = omap2_gp_timer_shutdown,
 155         .tick_resume            = omap2_gp_timer_shutdown,
 156 };
 157
 158 static const struct of_device_id omap_timer_match[] __initconst = {
 159         { .compatible = "ti,omap2420-timer", },
 160         { .compatible = "ti,omap3430-timer", },
 161         { .compatible = "ti,omap4430-timer", },
 162         { .compatible = "ti,omap5430-timer", },
 163         { .compatible = "ti,dm814-timer", },
 164         { .compatible = "ti,dm816-timer", },
 165         { .compatible = "ti,am335x-timer", },
 166         { .compatible = "ti,am335x-timer-1ms", },
 167         { }
 168 };
 169
 170 static int omap_timer_add_disabled_property(struct device_node *np)
 171 {
 172         struct property *prop;
 173
 174         prop = kzalloc(sizeof(*prop), GFP_KERNEL);
 175         if (!prop)
 176                 return -ENOMEM;
 177
 178         prop->name = "status";
 179         prop->value = "disabled";
 180         prop->length = strlen(prop->value);
 181
 182         return of_add_property(np, prop);
 183 }
 184
 185 static int omap_timer_update_dt(struct device_node *np)
 186 {
 187         int error = 0;
 188
 189         if (!of_device_is_compatible(np, "ti,omap-counter32k")) {
 190                 error = omap_timer_add_disabled_property(np);
 191                 if (error)
 192                         return error;
 193         }
 194
 195         /* No parent interconnect target module configured? */
 196         if (of_get_property(np, "ti,hwmods", NULL))
 197                 return error;
 198
 199         /* Tag parent interconnect target module disabled */
 200         error = omap_timer_add_disabled_property(np->parent);
 201         if (error)
 202                 return error;
 203
 204         return 0;
 205 }
 206
 207 /**
 208  * omap_get_timer_dt - get a timer using device-tree
 209  * @match       - device-tree match structure for matching a device type
 210  * @property    - optional timer property to match
 211  *
 212  * Helper function to get a timer during early boot using device-tree for use
 213  * as kernel system timer. Optionally, the property argument can be used to
 214  * select a timer with a specific property. Once a timer is found then mark
 215  * the timer node in device-tree as disabled, to prevent the kernel from
 216  * registering this timer as a platform device and so no one else can use it.
 217  */
 218 static struct device_node * __init omap_get_timer_dt(const struct of_device_id *match,
 219                                                      const char *property)
 220 {
 221         struct device_node *np;
 222         int error;
 223
 224         for_each_matching_node(np, match) {
 225                 if (!of_device_is_available(np))
 226                         continue;
 227
 228                 if (property && !of_get_property(np, property, NULL))
 229                         continue;
 230
 231                 if (!property && (of_get_property(np, "ti,timer-alwon", NULL) ||
 232                                   of_get_property(np, "ti,timer-dsp", NULL) ||
 233                                   of_get_property(np, "ti,timer-pwm", NULL) ||
 234                                   of_get_property(np, "ti,timer-secure", NULL)))
 235                         continue;
 236
 237                 error = omap_timer_update_dt(np);
 238                 WARN(error, "%s: Could not update dt: %i\n", __func__, error);
 239
 240                 return np;
 241         }
 242
 243         return NULL;
 244 }
 245
 246 /**
 247  * omap_dmtimer_init - initialisation function when device tree is used
 248  *
 249  * For secure OMAP3/DRA7xx devices, timers with device type "timer-secure"
 250  * cannot be used by the kernel as they are reserved. Therefore, to prevent the
 251  * kernel registering these devices remove them dynamically from the device
 252  * tree on boot.
 253  */
 254 static void __init omap_dmtimer_init(void)
 255 {
 256         struct device_node *np;
 257
 258         if (!cpu_is_omap34xx() && !soc_is_dra7xx())
 259                 return;
 260
 261         /* If we are a secure device, remove any secure timer nodes */
 262         if ((omap_type() != OMAP2_DEVICE_TYPE_GP)) {
 263                 np = omap_get_timer_dt(omap_timer_match, "ti,timer-secure");
 264                 of_node_put(np);
 265         }
 266 }
 267
 268 /**
 269  * omap_dm_timer_get_errata - get errata flags for a timer
 270  *
 271  * Get the timer errata flags that are specific to the OMAP device being used.
 272  */
 273 static u32 __init omap_dm_timer_get_errata(void)
 274 {
 275         if (cpu_is_omap24xx())
 276                 return 0;
 277
 278         return OMAP_TIMER_ERRATA_I103_I767;
 279 }
 280
 281 static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
 282                                          const char *fck_source,
 283                                          const char *property,
 284                                          const char **timer_name,
 285                                          int posted)
 286 {
 287         const char *oh_name = NULL;
 288         struct device_node *np;
 289         struct omap_hwmod *oh;
 290         struct clk *src;
 291         int r = 0;
 292
 293         np = omap_get_timer_dt(omap_timer_match, property);
 294         if (!np)
 295                 return -ENODEV;
 296
 297         of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 298         if (!oh_name) {
 299                 of_property_read_string_index(np->parent, "ti,hwmods", 0,
 300                                               &oh_name);
 301                 if (!oh_name)
 302                         return -ENODEV;
 303         }
 304
 305         timer->irq = irq_of_parse_and_map(np, 0);
 306         if (!timer->irq)
 307                 return -ENXIO;
 308
 309         timer->io_base = of_iomap(np, 0);
 310
 311         timer->fclk = of_clk_get_by_name(np, "fck");
 312
 313         of_node_put(np);
 314
 315         oh = omap_hwmod_lookup(oh_name);
 316         if (!oh)
 317                 return -ENODEV;
 318
 319         *timer_name = oh->name;
 320
 321         if (!timer->io_base)
 322                 return -ENXIO;
 323
 324         omap_hwmod_setup_one(oh_name);
 325
 326         /* After the dmtimer is using hwmod these clocks won't be needed */
 327         if (IS_ERR_OR_NULL(timer->fclk))
 328                 timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
 329         if (IS_ERR(timer->fclk))
 330                 return PTR_ERR(timer->fclk);
 331
 332         src = clk_get(NULL, fck_source);
 333         if (IS_ERR(src))
 334                 return PTR_ERR(src);
 335
 336         WARN(clk_set_parent(timer->fclk, src) < 0,
 337              "Cannot set timer parent clock, no PLL clock driver?");
 338
 339         clk_put(src);
 340
 341         omap_hwmod_enable(oh);
 342         __omap_dm_timer_init_regs(timer);
 343
 344         if (posted)
 345                 __omap_dm_timer_enable_posted(timer);
 346
 347         /* Check that the intended posted configuration matches the actual */
 348         if (posted != timer->posted)
 349                 return -EINVAL;
 350
 351         timer->rate = clk_get_rate(timer->fclk);
 352         timer->reserved = 1;
 353
 354         return r;
 355 }
 356
 357 #if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
 358 void tick_broadcast(const struct cpumask *mask)
 359 {
 360 }
 361 #endif
 362
 363 static void __init omap2_gp_clockevent_init(int gptimer_id,
 364                                                 const char *fck_source,
 365                                                 const char *property)
 366 {
 367         int res;
 368
 369         clkev.id = gptimer_id;
 370         clkev.errata = omap_dm_timer_get_errata();
 371
 372         /*
 373          * For clock-event timers we never read the timer counter and
 374          * so we are not impacted by errata i103 and i767. Therefore,
 375          * we can safely ignore this errata for clock-event timers.
 376          */
 377         __omap_dm_timer_override_errata(&clkev, OMAP_TIMER_ERRATA_I103_I767);
 378
 379         res = omap_dm_timer_init_one(&clkev, fck_source, property,
 380                                      &clockevent_gpt.name, OMAP_TIMER_POSTED);
 381         BUG_ON(res);
 382
 383         omap2_gp_timer_irq.dev_id = &clkev;
 384         setup_irq(clkev.irq, &omap2_gp_timer_irq);
 385
 386         __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
 387
 388         clockevent_gpt.cpumask = cpu_possible_mask;
 389         clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
 390         clockevents_config_and_register(&clockevent_gpt, clkev.rate,
 391                                         3, /* Timer internal resynch latency */
 392                                         0xffffffff);
 393
 394         if (soc_is_am33xx() || soc_is_am43xx()) {
 395                 clockevent_gpt.suspend = omap_clkevt_idle;
 396                 clockevent_gpt.resume = omap_clkevt_unidle;
 397
 398                 clockevent_gpt_hwmod =
 399                         omap_hwmod_lookup(clockevent_gpt.name);
 400         }
 401
 402         pr_info("OMAP clockevent source: %s at %lu Hz\n", clockevent_gpt.name,
 403                 clkev.rate);
 404 }
 405
 406 /* Clocksource code */
 407 static struct omap_dm_timer clksrc;
 408 static bool use_gptimer_clksrc __initdata;
 409
 410 /*
 411  * clocksource
 412  */
 413 static u64 clocksource_read_cycles(struct clocksource *cs)
 414 {
 415         return (u64)__omap_dm_timer_read_counter(&clksrc,
 416                                                      OMAP_TIMER_NONPOSTED);
 417 }
 418
 419 static struct clocksource clocksource_gpt = {
 420         .rating         = 300,
 421         .read           = clocksource_read_cycles,
 422         .mask           = CLOCKSOURCE_MASK(32),
 423         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 424 };
 425
 426 static u64 notrace dmtimer_read_sched_clock(void)
 427 {
 428         if (clksrc.reserved)
 429                 return __omap_dm_timer_read_counter(&clksrc,
 430                                                     OMAP_TIMER_NONPOSTED);
 431
 432         return 0;
 433 }
 434
 435 static const struct of_device_id omap_counter_match[] __initconst = {
 436         { .compatible = "ti,omap-counter32k", },
 437         { }
 438 };
 439
 440 /* Setup free-running counter for clocksource */
 441 static int __init __maybe_unused omap2_sync32k_clocksource_init(void)
 442 {
 443         int ret;
 444         struct device_node *np = NULL;
 445         struct omap_hwmod *oh;
 446         const char *oh_name = "counter_32k";
 447
 448         /*
 449          * See if the 32kHz counter is supported.
 450          */
 451         np = omap_get_timer_dt(omap_counter_match, NULL);
 452         if (!np)
 453                 return -ENODEV;
 454
 455         of_property_read_string_index(np->parent, "ti,hwmods", 0, &oh_name);
 456         if (!oh_name) {
 457                 of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
 458                 if (!oh_name)
 459                         return -ENODEV;
 460         }
 461
 462         /*
 463          * First check hwmod data is available for sync32k counter
 464          */
 465         oh = omap_hwmod_lookup(oh_name);
 466         if (!oh || oh->slaves_cnt == 0)
 467                 return -ENODEV;
 468
 469         omap_hwmod_setup_one(oh_name);
 470
 471         ret = omap_hwmod_enable(oh);
 472         if (ret) {
 473                 pr_warn("%s: failed to enable counter_32k module (%d)\n",
 474                                                         __func__, ret);
 475                 return ret;
 476         }
 477
 478         return ret;
 479 }
 480
 481 static void __init omap2_gptimer_clocksource_init(int gptimer_id,
 482                                                   const char *fck_source,
 483                                                   const char *property)
 484 {
 485         int res;
 486
 487         clksrc.id = gptimer_id;
 488         clksrc.errata = omap_dm_timer_get_errata();
 489
 490         res = omap_dm_timer_init_one(&clksrc, fck_source, property,
 491                                      &clocksource_gpt.name,
 492                                      OMAP_TIMER_NONPOSTED);
 493         BUG_ON(res);
 494
 495         __omap_dm_timer_load_start(&clksrc,
 496                                    OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0,
 497                                    OMAP_TIMER_NONPOSTED);
 498         sched_clock_register(dmtimer_read_sched_clock, 32, clksrc.rate);
 499
 500         if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
 501                 pr_err("Could not register clocksource %s\n",
 502                         clocksource_gpt.name);
 503         else
 504                 pr_info("OMAP clocksource: %s at %lu Hz\n",
 505                         clocksource_gpt.name, clksrc.rate);
 506 }
 507
 508 static void __init __omap_sync32k_timer_init(int clkev_nr, const char *clkev_src,
 509                 const char *clkev_prop, int clksrc_nr, const char *clksrc_src,
 510                 const char *clksrc_prop, bool gptimer)
 511 {
 512         omap_clk_init();
 513         omap_dmtimer_init();
 514         omap2_gp_clockevent_init(clkev_nr, clkev_src, clkev_prop);
 515
 516         /* Enable the use of clocksource="gp_timer" kernel parameter */
 517         if (use_gptimer_clksrc || gptimer)
 518                 omap2_gptimer_clocksource_init(clksrc_nr, clksrc_src,
 519                                                 clksrc_prop);
 520         else
 521                 omap2_sync32k_clocksource_init();
 522 }
 523
 524 void __init omap_init_time(void)
 525 {
 526         __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
 527                         2, "timer_sys_ck", NULL, false);
 528
 529         timer_probe();
 530 }
 531
 532 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
 533 void __init omap3_secure_sync32k_timer_init(void)
 534 {
 535         __omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
 536                         2, "timer_sys_ck", NULL, false);
 537
 538         timer_probe();
 539 }
 540 #endif /* CONFIG_ARCH_OMAP3 */
 541
 542 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX) || \
 543         defined(CONFIG_SOC_AM43XX)
 544 void __init omap3_gptimer_timer_init(void)
 545 {
 546         __omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
 547                         1, "timer_sys_ck", "ti,timer-alwon", true);
 548         if (of_have_populated_dt())
 549                 timer_probe();
 550 }
 551 #endif
 552
 553 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) ||          \
 554         defined(CONFIG_SOC_DRA7XX)
 555 static void __init omap4_sync32k_timer_init(void)
 556 {
 557         __omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
 558                         2, "sys_clkin_ck", NULL, false);
 559 }
 560
 561 void __init omap4_local_timer_init(void)
 562 {
 563         omap4_sync32k_timer_init();
 564         timer_probe();
 565 }
 566 #endif
 567
 568 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
 569
 570 /*
 571  * The realtime counter also called master counter, is a free-running
 572  * counter, which is related to real time. It produces the count used
 573  * by the CPU local timer peripherals in the MPU cluster. The timer counts
 574  * at a rate of 6.144 MHz. Because the device operates on different clocks
 575  * in different power modes, the master counter shifts operation between
 576  * clocks, adjusting the increment per clock in hardware accordingly to
 577  * maintain a constant count rate.
 578  */
 579 static void __init realtime_counter_init(void)
 580 {
 581 #ifdef CONFIG_SOC_HAS_REALTIME_COUNTER
 582         void __iomem *base;
 583         static struct clk *sys_clk;
 584         unsigned long rate;
 585         unsigned int reg;
 586         unsigned long long num, den;
 587
 588         base = ioremap(REALTIME_COUNTER_BASE, SZ_32);
 589         if (!base) {
 590                 pr_err("%s: ioremap failed\n", __func__);
 591                 return;
 592         }
 593         sys_clk = clk_get(NULL, "sys_clkin");
 594         if (IS_ERR(sys_clk)) {
 595                 pr_err("%s: failed to get system clock handle\n", __func__);
 596                 iounmap(base);
 597                 return;
 598         }
 599
 600         rate = clk_get_rate(sys_clk);
 601
 602         if (soc_is_dra7xx()) {
 603                 /*
 604                  * Errata i856 says the 32.768KHz crystal does not start at
 605                  * power on, so the CPU falls back to an emulated 32KHz clock
 606                  * based on sysclk / 610 instead. This causes the master counter
 607                  * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2
 608                  * (OR sysclk * 75 / 244)
 609                  *
 610                  * This affects at least the DRA7/AM572x 1.0, 1.1 revisions.
 611                  * Of course any board built without a populated 32.768KHz
 612                  * crystal would also need this fix even if the CPU is fixed
 613                  * later.
 614                  *
 615                  * Either case can be detected by using the two speedselect bits
 616                  * If they are not 0, then the 32.768KHz clock driving the
 617                  * coarse counter that corrects the fine counter every time it
 618                  * ticks is actually rate/610 rather than 32.768KHz and we
 619                  * should compensate to avoid the 570ppm (at 20MHz, much worse
 620                  * at other rates) too fast system time.
 621                  */
 622                 reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP);
 623                 if (reg & DRA7_SPEEDSELECT_MASK) {
 624                         num = 75;
 625                         den = 244;
 626                         goto sysclk1_based;
 627                 }
 628         }
 629
 630         /* Numerator/denumerator values refer TRM Realtime Counter section */
 631         switch (rate) {
 632         case 12000000:
 633                 num = 64;
 634                 den = 125;
 635                 break;
 636         case 13000000:
 637                 num = 768;
 638                 den = 1625;
 639                 break;
 640         case 19200000:
 641                 num = 8;
 642                 den = 25;
 643                 break;
 644         case 20000000:
 645                 num = 192;
 646                 den = 625;
 647                 break;
 648         case 26000000:
 649                 num = 384;
 650                 den = 1625;
 651                 break;
 652         case 27000000:
 653                 num = 256;
 654                 den = 1125;
 655                 break;
 656         case 38400000:
 657         default:
 658                 /* Program it for 38.4 MHz */
 659                 num = 4;
 660                 den = 25;
 661                 break;
 662         }
 663
 664 sysclk1_based:
 665         /* Program numerator and denumerator registers */
 666         reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
 667                         NUMERATOR_DENUMERATOR_MASK;
 668         reg |= num;
 669         writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
 670
 671         reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
 672                         NUMERATOR_DENUMERATOR_MASK;
 673         reg |= den;
 674         writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
 675
 676         arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den);
 677         set_cntfreq();
 678
 679         iounmap(base);
 680 #endif
 681 }
 682
 683 void __init omap5_realtime_timer_init(void)
 684 {
 685         omap4_sync32k_timer_init();
 686         realtime_counter_init();
 687
 688         timer_probe();
 689 }
 690 #endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */
 691
 692 /**
 693  * omap2_override_clocksource - clocksource override with user configuration
 694  *
 695  * Allows user to override default clocksource, using kernel parameter
 696  *   clocksource="gp_timer"     (For all OMAP2PLUS architectures)
 697  *
 698  * Note that, here we are using same standard kernel parameter "clocksource=",
 699  * and not introducing any OMAP specific interface.
 700  */
 701 static int __init omap2_override_clocksource(char *str)
 702 {
 703         if (!str)
 704                 return 0;
 705         /*
 706          * For OMAP architecture, we only have two options
 707          *    - sync_32k (default)
 708          *    - gp_timer (sys_clk based)
 709          */
 710         if (!strcmp(str, "gp_timer"))
 711                 use_gptimer_clksrc = true;
 712
 713         return 0;
 714 }
 715 early_param("clocksource", omap2_override_clocksource);