2 * Hardware modules present on the DRA7xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/platform_data/hsmmc-omap.h>
23 #include <linux/power/smartreflex.h>
24 #include <linux/i2c-omap.h>
26 #include <linux/omap-dma.h>
27 #include <linux/platform_data/spi-omap2-mcspi.h>
28 #include <linux/platform_data/asoc-ti-mcbsp.h>
29 #include <plat/dmtimer.h>
31 #include "omap_hwmod.h"
32 #include "omap_hwmod_common_data.h"
40 /* Base offset for all DRA7XX interrupts external to MPUSS */
41 #define DRA7XX_IRQ_GIC_START 32
43 /* Base offset for all DRA7XX dma requests */
44 #define DRA7XX_DMA_REQ_START 1
55 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
60 static struct omap_hwmod dra7xx_dmm_hwmod = {
62 .class = &dra7xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
66 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
74 * instance(s): l3_instr, l3_main_1, l3_main_2
76 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
81 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
83 .class = &dra7xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
87 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
95 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
97 .class = &dra7xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
101 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
108 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
110 .class = &dra7xx_l3_hwmod_class,
111 .clkdm_name = "l3instr_clkdm",
114 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
116 .modulemode = MODULEMODE_HWCTRL,
123 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
125 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
130 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
132 .class = &dra7xx_l4_hwmod_class,
133 .clkdm_name = "l4cfg_clkdm",
136 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
137 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
143 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
145 .class = &dra7xx_l4_hwmod_class,
146 .clkdm_name = "l4per_clkdm",
149 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
156 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
158 .class = &dra7xx_l4_hwmod_class,
159 .clkdm_name = "l4per2_clkdm",
162 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
163 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
169 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
171 .class = &dra7xx_l4_hwmod_class,
172 .clkdm_name = "l4per3_clkdm",
175 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
176 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
182 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
184 .class = &dra7xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
188 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
199 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
204 static struct omap_hwmod dra7xx_atl_hwmod = {
206 .class = &dra7xx_atl_hwmod_class,
207 .clkdm_name = "atl_clkdm",
208 .main_clk = "atl_gfclk_mux",
211 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
212 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
213 .modulemode = MODULEMODE_SWCTRL,
223 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
228 static struct omap_hwmod dra7xx_bb2d_hwmod = {
230 .class = &dra7xx_bb2d_hwmod_class,
231 .clkdm_name = "dss_clkdm",
232 .main_clk = "dpll_core_h24x2_ck",
235 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
236 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
237 .modulemode = MODULEMODE_SWCTRL,
247 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
250 .sysc_flags = SYSC_HAS_SIDLEMODE,
251 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
253 .sysc_fields = &omap_hwmod_sysc_type1,
256 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
258 .sysc = &dra7xx_counter_sysc,
262 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
263 .name = "counter_32k",
264 .class = &dra7xx_counter_hwmod_class,
265 .clkdm_name = "wkupaon_clkdm",
266 .flags = HWMOD_SWSUP_SIDLE,
267 .main_clk = "wkupaon_iclk_mux",
270 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
271 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
277 * 'ctrl_module' class
281 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
282 .name = "ctrl_module",
285 /* ctrl_module_wkup */
286 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
287 .name = "ctrl_module_wkup",
288 .class = &dra7xx_ctrl_module_hwmod_class,
289 .clkdm_name = "wkupaon_clkdm",
292 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
299 * cpsw/gmac sub system
301 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
305 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
306 SYSS_HAS_RESET_STATUS),
307 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
309 .sysc_fields = &omap_hwmod_sysc_type3,
312 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
314 .sysc = &dra7xx_gmac_sysc,
317 static struct omap_hwmod dra7xx_gmac_hwmod = {
319 .class = &dra7xx_gmac_hwmod_class,
320 .clkdm_name = "gmac_clkdm",
321 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
322 .main_clk = "dpll_gmac_ck",
326 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
327 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
328 .modulemode = MODULEMODE_SWCTRL,
336 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
337 .name = "davinci_mdio",
340 static struct omap_hwmod dra7xx_mdio_hwmod = {
341 .name = "davinci_mdio",
342 .class = &dra7xx_mdio_hwmod_class,
343 .clkdm_name = "gmac_clkdm",
344 .main_clk = "dpll_gmac_ck",
352 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
357 static struct omap_hwmod dra7xx_dcan1_hwmod = {
359 .class = &dra7xx_dcan_hwmod_class,
360 .clkdm_name = "wkupaon_clkdm",
361 .main_clk = "dcan1_sys_clk_mux",
362 .flags = HWMOD_CLKDM_NOAUTO,
365 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
366 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
367 .modulemode = MODULEMODE_SWCTRL,
373 static struct omap_hwmod dra7xx_dcan2_hwmod = {
375 .class = &dra7xx_dcan_hwmod_class,
376 .clkdm_name = "l4per2_clkdm",
377 .main_clk = "sys_clkin1",
378 .flags = HWMOD_CLKDM_NOAUTO,
381 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
382 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
383 .modulemode = MODULEMODE_SWCTRL,
389 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
392 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
393 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
394 .sysc_fields = &omap_hwmod_sysc_type2,
400 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
402 .sysc = &dra7xx_epwmss_sysc,
406 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
408 .class = &dra7xx_epwmss_hwmod_class,
409 .clkdm_name = "l4per2_clkdm",
410 .main_clk = "l4_root_clk_div",
413 .modulemode = MODULEMODE_SWCTRL,
414 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
415 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
421 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
423 .class = &dra7xx_epwmss_hwmod_class,
424 .clkdm_name = "l4per2_clkdm",
425 .main_clk = "l4_root_clk_div",
428 .modulemode = MODULEMODE_SWCTRL,
429 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
430 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
436 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
438 .class = &dra7xx_epwmss_hwmod_class,
439 .clkdm_name = "l4per2_clkdm",
440 .main_clk = "l4_root_clk_div",
443 .modulemode = MODULEMODE_SWCTRL,
444 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
445 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
455 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
459 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
460 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
461 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
462 SYSS_HAS_RESET_STATUS),
463 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
464 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
465 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
466 .sysc_fields = &omap_hwmod_sysc_type1,
469 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
471 .sysc = &dra7xx_dma_sysc,
475 static struct omap_dma_dev_attr dma_dev_attr = {
476 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
477 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
482 static struct omap_hwmod dra7xx_dma_system_hwmod = {
483 .name = "dma_system",
484 .class = &dra7xx_dma_hwmod_class,
485 .clkdm_name = "dma_clkdm",
486 .main_clk = "l3_iclk_div",
489 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
490 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
493 .dev_attr = &dma_dev_attr,
500 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
504 static struct omap_hwmod dra7xx_tpcc_hwmod = {
506 .class = &dra7xx_tpcc_hwmod_class,
507 .clkdm_name = "l3main1_clkdm",
508 .main_clk = "l3_iclk_div",
511 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
512 .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
521 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
526 static struct omap_hwmod dra7xx_tptc0_hwmod = {
528 .class = &dra7xx_tptc_hwmod_class,
529 .clkdm_name = "l3main1_clkdm",
530 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
531 .main_clk = "l3_iclk_div",
534 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
535 .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
536 .modulemode = MODULEMODE_HWCTRL,
542 static struct omap_hwmod dra7xx_tptc1_hwmod = {
544 .class = &dra7xx_tptc_hwmod_class,
545 .clkdm_name = "l3main1_clkdm",
546 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
547 .main_clk = "l3_iclk_div",
550 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
551 .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
552 .modulemode = MODULEMODE_HWCTRL,
562 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
565 .sysc_flags = SYSS_HAS_RESET_STATUS,
568 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
570 .sysc = &dra7xx_dss_sysc,
571 .reset = omap_dss_reset,
575 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
576 { .role = "dss_clk", .clk = "dss_dss_clk" },
577 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
578 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
579 { .role = "video2_clk", .clk = "dss_video2_clk" },
580 { .role = "video1_clk", .clk = "dss_video1_clk" },
581 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
582 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
585 static struct omap_hwmod dra7xx_dss_hwmod = {
587 .class = &dra7xx_dss_hwmod_class,
588 .clkdm_name = "dss_clkdm",
589 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
590 .main_clk = "dss_dss_clk",
593 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
594 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
595 .modulemode = MODULEMODE_SWCTRL,
598 .opt_clks = dss_opt_clks,
599 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
607 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
611 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
612 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
613 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
614 SYSS_HAS_RESET_STATUS),
615 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
616 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
617 .sysc_fields = &omap_hwmod_sysc_type1,
620 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
622 .sysc = &dra7xx_dispc_sysc,
626 /* dss_dispc dev_attr */
627 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
628 .has_framedonetv_irq = 1,
632 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
634 .class = &dra7xx_dispc_hwmod_class,
635 .clkdm_name = "dss_clkdm",
636 .main_clk = "dss_dss_clk",
639 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
640 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
643 .dev_attr = &dss_dispc_dev_attr,
644 .parent_hwmod = &dra7xx_dss_hwmod,
652 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
655 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
657 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
659 .sysc_fields = &omap_hwmod_sysc_type2,
662 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
664 .sysc = &dra7xx_hdmi_sysc,
669 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
670 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
673 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
675 .class = &dra7xx_hdmi_hwmod_class,
676 .clkdm_name = "dss_clkdm",
677 .main_clk = "dss_48mhz_clk",
680 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
681 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
684 .opt_clks = dss_hdmi_opt_clks,
685 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
686 .parent_hwmod = &dra7xx_dss_hwmod,
689 /* AES (the 'P' (public) device) */
690 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
694 .sysc_flags = SYSS_HAS_RESET_STATUS,
697 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
699 .sysc = &dra7xx_aes_sysc,
704 static struct omap_hwmod dra7xx_aes1_hwmod = {
706 .class = &dra7xx_aes_hwmod_class,
707 .clkdm_name = "l4sec_clkdm",
708 .main_clk = "l3_iclk_div",
711 .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
712 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
713 .modulemode = MODULEMODE_HWCTRL,
719 static struct omap_hwmod dra7xx_aes2_hwmod = {
721 .class = &dra7xx_aes_hwmod_class,
722 .clkdm_name = "l4sec_clkdm",
723 .main_clk = "l3_iclk_div",
726 .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
727 .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
728 .modulemode = MODULEMODE_HWCTRL,
733 /* sha0 HIB2 (the 'P' (public) device) */
734 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
738 .sysc_flags = SYSS_HAS_RESET_STATUS,
741 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
743 .sysc = &dra7xx_sha0_sysc,
747 struct omap_hwmod dra7xx_sha0_hwmod = {
749 .class = &dra7xx_sha0_hwmod_class,
750 .clkdm_name = "l4sec_clkdm",
751 .main_clk = "l3_iclk_div",
754 .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
755 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
756 .modulemode = MODULEMODE_HWCTRL,
766 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
770 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
771 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
772 SYSS_HAS_RESET_STATUS),
773 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
775 .sysc_fields = &omap_hwmod_sysc_type1,
778 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
780 .sysc = &dra7xx_elm_sysc,
785 static struct omap_hwmod dra7xx_elm_hwmod = {
787 .class = &dra7xx_elm_hwmod_class,
788 .clkdm_name = "l4per_clkdm",
789 .main_clk = "l3_iclk_div",
792 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
793 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
803 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
807 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
808 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
809 SYSS_HAS_RESET_STATUS),
810 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
812 .sysc_fields = &omap_hwmod_sysc_type1,
815 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
817 .sysc = &dra7xx_gpio_sysc,
822 static struct omap_gpio_dev_attr gpio_dev_attr = {
828 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
829 { .role = "dbclk", .clk = "gpio1_dbclk" },
832 static struct omap_hwmod dra7xx_gpio1_hwmod = {
834 .class = &dra7xx_gpio_hwmod_class,
835 .clkdm_name = "wkupaon_clkdm",
836 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
837 .main_clk = "wkupaon_iclk_mux",
840 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
841 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
842 .modulemode = MODULEMODE_HWCTRL,
845 .opt_clks = gpio1_opt_clks,
846 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
847 .dev_attr = &gpio_dev_attr,
851 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
852 { .role = "dbclk", .clk = "gpio2_dbclk" },
855 static struct omap_hwmod dra7xx_gpio2_hwmod = {
857 .class = &dra7xx_gpio_hwmod_class,
858 .clkdm_name = "l4per_clkdm",
859 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
860 .main_clk = "l3_iclk_div",
863 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
864 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
865 .modulemode = MODULEMODE_HWCTRL,
868 .opt_clks = gpio2_opt_clks,
869 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
870 .dev_attr = &gpio_dev_attr,
874 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
875 { .role = "dbclk", .clk = "gpio3_dbclk" },
878 static struct omap_hwmod dra7xx_gpio3_hwmod = {
880 .class = &dra7xx_gpio_hwmod_class,
881 .clkdm_name = "l4per_clkdm",
882 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
883 .main_clk = "l3_iclk_div",
886 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
887 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
888 .modulemode = MODULEMODE_HWCTRL,
891 .opt_clks = gpio3_opt_clks,
892 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
893 .dev_attr = &gpio_dev_attr,
897 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
898 { .role = "dbclk", .clk = "gpio4_dbclk" },
901 static struct omap_hwmod dra7xx_gpio4_hwmod = {
903 .class = &dra7xx_gpio_hwmod_class,
904 .clkdm_name = "l4per_clkdm",
905 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
906 .main_clk = "l3_iclk_div",
909 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
910 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
911 .modulemode = MODULEMODE_HWCTRL,
914 .opt_clks = gpio4_opt_clks,
915 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
916 .dev_attr = &gpio_dev_attr,
920 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
921 { .role = "dbclk", .clk = "gpio5_dbclk" },
924 static struct omap_hwmod dra7xx_gpio5_hwmod = {
926 .class = &dra7xx_gpio_hwmod_class,
927 .clkdm_name = "l4per_clkdm",
928 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
929 .main_clk = "l3_iclk_div",
932 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
933 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
934 .modulemode = MODULEMODE_HWCTRL,
937 .opt_clks = gpio5_opt_clks,
938 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
939 .dev_attr = &gpio_dev_attr,
943 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
944 { .role = "dbclk", .clk = "gpio6_dbclk" },
947 static struct omap_hwmod dra7xx_gpio6_hwmod = {
949 .class = &dra7xx_gpio_hwmod_class,
950 .clkdm_name = "l4per_clkdm",
951 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
952 .main_clk = "l3_iclk_div",
955 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
956 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
957 .modulemode = MODULEMODE_HWCTRL,
960 .opt_clks = gpio6_opt_clks,
961 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
962 .dev_attr = &gpio_dev_attr,
966 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
967 { .role = "dbclk", .clk = "gpio7_dbclk" },
970 static struct omap_hwmod dra7xx_gpio7_hwmod = {
972 .class = &dra7xx_gpio_hwmod_class,
973 .clkdm_name = "l4per_clkdm",
974 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
975 .main_clk = "l3_iclk_div",
978 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
979 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
980 .modulemode = MODULEMODE_HWCTRL,
983 .opt_clks = gpio7_opt_clks,
984 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
985 .dev_attr = &gpio_dev_attr,
989 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
990 { .role = "dbclk", .clk = "gpio8_dbclk" },
993 static struct omap_hwmod dra7xx_gpio8_hwmod = {
995 .class = &dra7xx_gpio_hwmod_class,
996 .clkdm_name = "l4per_clkdm",
997 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
998 .main_clk = "l3_iclk_div",
1001 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
1002 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
1003 .modulemode = MODULEMODE_HWCTRL,
1006 .opt_clks = gpio8_opt_clks,
1007 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
1008 .dev_attr = &gpio_dev_attr,
1016 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
1018 .sysc_offs = 0x0010,
1019 .syss_offs = 0x0014,
1020 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1021 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1022 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1023 .sysc_fields = &omap_hwmod_sysc_type1,
1026 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
1028 .sysc = &dra7xx_gpmc_sysc,
1033 static struct omap_hwmod dra7xx_gpmc_hwmod = {
1035 .class = &dra7xx_gpmc_hwmod_class,
1036 .clkdm_name = "l3main1_clkdm",
1037 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1038 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1039 .main_clk = "l3_iclk_div",
1042 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
1043 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
1044 .modulemode = MODULEMODE_HWCTRL,
1054 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
1056 .sysc_offs = 0x0014,
1057 .syss_offs = 0x0018,
1058 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1059 SYSS_HAS_RESET_STATUS),
1060 .sysc_fields = &omap_hwmod_sysc_type1,
1063 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
1065 .sysc = &dra7xx_hdq1w_sysc,
1070 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
1072 .class = &dra7xx_hdq1w_hwmod_class,
1073 .clkdm_name = "l4per_clkdm",
1074 .flags = HWMOD_INIT_NO_RESET,
1075 .main_clk = "func_12m_fclk",
1078 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1079 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1080 .modulemode = MODULEMODE_SWCTRL,
1090 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
1091 .sysc_offs = 0x0010,
1092 .syss_offs = 0x0090,
1093 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1094 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1095 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1096 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1098 .sysc_fields = &omap_hwmod_sysc_type1,
1101 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
1103 .sysc = &dra7xx_i2c_sysc,
1104 .reset = &omap_i2c_reset,
1105 .rev = OMAP_I2C_IP_VERSION_2,
1109 static struct omap_i2c_dev_attr i2c_dev_attr = {
1110 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1114 static struct omap_hwmod dra7xx_i2c1_hwmod = {
1116 .class = &dra7xx_i2c_hwmod_class,
1117 .clkdm_name = "l4per_clkdm",
1118 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1119 .main_clk = "func_96m_fclk",
1122 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1123 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
1124 .modulemode = MODULEMODE_SWCTRL,
1127 .dev_attr = &i2c_dev_attr,
1131 static struct omap_hwmod dra7xx_i2c2_hwmod = {
1133 .class = &dra7xx_i2c_hwmod_class,
1134 .clkdm_name = "l4per_clkdm",
1135 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1136 .main_clk = "func_96m_fclk",
1139 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1140 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
1141 .modulemode = MODULEMODE_SWCTRL,
1144 .dev_attr = &i2c_dev_attr,
1148 static struct omap_hwmod dra7xx_i2c3_hwmod = {
1150 .class = &dra7xx_i2c_hwmod_class,
1151 .clkdm_name = "l4per_clkdm",
1152 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1153 .main_clk = "func_96m_fclk",
1156 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1157 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
1158 .modulemode = MODULEMODE_SWCTRL,
1161 .dev_attr = &i2c_dev_attr,
1165 static struct omap_hwmod dra7xx_i2c4_hwmod = {
1167 .class = &dra7xx_i2c_hwmod_class,
1168 .clkdm_name = "l4per_clkdm",
1169 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1170 .main_clk = "func_96m_fclk",
1173 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1174 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
1175 .modulemode = MODULEMODE_SWCTRL,
1178 .dev_attr = &i2c_dev_attr,
1182 static struct omap_hwmod dra7xx_i2c5_hwmod = {
1184 .class = &dra7xx_i2c_hwmod_class,
1185 .clkdm_name = "ipu_clkdm",
1186 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1187 .main_clk = "func_96m_fclk",
1190 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
1191 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
1192 .modulemode = MODULEMODE_SWCTRL,
1195 .dev_attr = &i2c_dev_attr,
1203 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
1205 .sysc_offs = 0x0010,
1206 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1207 SYSC_HAS_SOFTRESET),
1208 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1209 .sysc_fields = &omap_hwmod_sysc_type2,
1212 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
1214 .sysc = &dra7xx_mailbox_sysc,
1218 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
1220 .class = &dra7xx_mailbox_hwmod_class,
1221 .clkdm_name = "l4cfg_clkdm",
1224 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
1225 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
1231 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
1233 .class = &dra7xx_mailbox_hwmod_class,
1234 .clkdm_name = "l4cfg_clkdm",
1237 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
1238 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
1244 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
1246 .class = &dra7xx_mailbox_hwmod_class,
1247 .clkdm_name = "l4cfg_clkdm",
1250 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
1251 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
1257 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1259 .class = &dra7xx_mailbox_hwmod_class,
1260 .clkdm_name = "l4cfg_clkdm",
1263 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1264 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1270 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1272 .class = &dra7xx_mailbox_hwmod_class,
1273 .clkdm_name = "l4cfg_clkdm",
1276 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1277 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1283 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1285 .class = &dra7xx_mailbox_hwmod_class,
1286 .clkdm_name = "l4cfg_clkdm",
1289 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1290 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1296 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1298 .class = &dra7xx_mailbox_hwmod_class,
1299 .clkdm_name = "l4cfg_clkdm",
1302 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1303 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1309 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1311 .class = &dra7xx_mailbox_hwmod_class,
1312 .clkdm_name = "l4cfg_clkdm",
1315 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1316 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1322 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1324 .class = &dra7xx_mailbox_hwmod_class,
1325 .clkdm_name = "l4cfg_clkdm",
1328 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1329 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1335 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1336 .name = "mailbox10",
1337 .class = &dra7xx_mailbox_hwmod_class,
1338 .clkdm_name = "l4cfg_clkdm",
1341 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1342 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1348 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1349 .name = "mailbox11",
1350 .class = &dra7xx_mailbox_hwmod_class,
1351 .clkdm_name = "l4cfg_clkdm",
1354 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1355 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1361 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1362 .name = "mailbox12",
1363 .class = &dra7xx_mailbox_hwmod_class,
1364 .clkdm_name = "l4cfg_clkdm",
1367 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1368 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1374 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1375 .name = "mailbox13",
1376 .class = &dra7xx_mailbox_hwmod_class,
1377 .clkdm_name = "l4cfg_clkdm",
1380 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1381 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1391 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1393 .sysc_offs = 0x0010,
1394 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1395 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1396 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1398 .sysc_fields = &omap_hwmod_sysc_type2,
1401 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1403 .sysc = &dra7xx_mcspi_sysc,
1404 .rev = OMAP4_MCSPI_REV,
1408 /* mcspi1 dev_attr */
1409 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
1410 .num_chipselect = 4,
1413 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1415 .class = &dra7xx_mcspi_hwmod_class,
1416 .clkdm_name = "l4per_clkdm",
1417 .main_clk = "func_48m_fclk",
1420 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1421 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1422 .modulemode = MODULEMODE_SWCTRL,
1425 .dev_attr = &mcspi1_dev_attr,
1429 /* mcspi2 dev_attr */
1430 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
1431 .num_chipselect = 2,
1434 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1436 .class = &dra7xx_mcspi_hwmod_class,
1437 .clkdm_name = "l4per_clkdm",
1438 .main_clk = "func_48m_fclk",
1441 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1442 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1443 .modulemode = MODULEMODE_SWCTRL,
1446 .dev_attr = &mcspi2_dev_attr,
1450 /* mcspi3 dev_attr */
1451 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1452 .num_chipselect = 2,
1455 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1457 .class = &dra7xx_mcspi_hwmod_class,
1458 .clkdm_name = "l4per_clkdm",
1459 .main_clk = "func_48m_fclk",
1462 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1463 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1464 .modulemode = MODULEMODE_SWCTRL,
1467 .dev_attr = &mcspi3_dev_attr,
1471 /* mcspi4 dev_attr */
1472 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1473 .num_chipselect = 1,
1476 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1478 .class = &dra7xx_mcspi_hwmod_class,
1479 .clkdm_name = "l4per_clkdm",
1480 .main_clk = "func_48m_fclk",
1483 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1484 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1485 .modulemode = MODULEMODE_SWCTRL,
1488 .dev_attr = &mcspi4_dev_attr,
1495 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1496 .sysc_offs = 0x0004,
1497 .sysc_flags = SYSC_HAS_SIDLEMODE,
1498 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1499 .sysc_fields = &omap_hwmod_sysc_type3,
1502 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1504 .sysc = &dra7xx_mcasp_sysc,
1508 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1509 { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1510 { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1513 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1515 .class = &dra7xx_mcasp_hwmod_class,
1516 .clkdm_name = "ipu_clkdm",
1517 .main_clk = "mcasp1_aux_gfclk_mux",
1518 .flags = HWMOD_OPT_CLKS_NEEDED,
1521 .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1522 .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1523 .modulemode = MODULEMODE_SWCTRL,
1526 .opt_clks = mcasp1_opt_clks,
1527 .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks),
1531 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1532 { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1533 { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1536 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1538 .class = &dra7xx_mcasp_hwmod_class,
1539 .clkdm_name = "l4per2_clkdm",
1540 .main_clk = "mcasp2_aux_gfclk_mux",
1541 .flags = HWMOD_OPT_CLKS_NEEDED,
1544 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1545 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1546 .modulemode = MODULEMODE_SWCTRL,
1549 .opt_clks = mcasp2_opt_clks,
1550 .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks),
1554 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1555 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1558 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1560 .class = &dra7xx_mcasp_hwmod_class,
1561 .clkdm_name = "l4per2_clkdm",
1562 .main_clk = "mcasp3_aux_gfclk_mux",
1563 .flags = HWMOD_OPT_CLKS_NEEDED,
1566 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1567 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1568 .modulemode = MODULEMODE_SWCTRL,
1571 .opt_clks = mcasp3_opt_clks,
1572 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
1576 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1577 { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1580 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1582 .class = &dra7xx_mcasp_hwmod_class,
1583 .clkdm_name = "l4per2_clkdm",
1584 .main_clk = "mcasp4_aux_gfclk_mux",
1585 .flags = HWMOD_OPT_CLKS_NEEDED,
1588 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1589 .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1590 .modulemode = MODULEMODE_SWCTRL,
1593 .opt_clks = mcasp4_opt_clks,
1594 .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks),
1598 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1599 { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1602 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1604 .class = &dra7xx_mcasp_hwmod_class,
1605 .clkdm_name = "l4per2_clkdm",
1606 .main_clk = "mcasp5_aux_gfclk_mux",
1607 .flags = HWMOD_OPT_CLKS_NEEDED,
1610 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1611 .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1612 .modulemode = MODULEMODE_SWCTRL,
1615 .opt_clks = mcasp5_opt_clks,
1616 .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks),
1620 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1621 { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1624 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1626 .class = &dra7xx_mcasp_hwmod_class,
1627 .clkdm_name = "l4per2_clkdm",
1628 .main_clk = "mcasp6_aux_gfclk_mux",
1629 .flags = HWMOD_OPT_CLKS_NEEDED,
1632 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1633 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1634 .modulemode = MODULEMODE_SWCTRL,
1637 .opt_clks = mcasp6_opt_clks,
1638 .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks),
1642 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1643 { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1646 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1648 .class = &dra7xx_mcasp_hwmod_class,
1649 .clkdm_name = "l4per2_clkdm",
1650 .main_clk = "mcasp7_aux_gfclk_mux",
1651 .flags = HWMOD_OPT_CLKS_NEEDED,
1654 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1655 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1656 .modulemode = MODULEMODE_SWCTRL,
1659 .opt_clks = mcasp7_opt_clks,
1660 .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks),
1664 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1665 { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1668 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1670 .class = &dra7xx_mcasp_hwmod_class,
1671 .clkdm_name = "l4per2_clkdm",
1672 .main_clk = "mcasp8_aux_gfclk_mux",
1673 .flags = HWMOD_OPT_CLKS_NEEDED,
1676 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1677 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1678 .modulemode = MODULEMODE_SWCTRL,
1681 .opt_clks = mcasp8_opt_clks,
1682 .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks),
1690 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1692 .sysc_offs = 0x0010,
1693 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1694 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1695 SYSC_HAS_SOFTRESET),
1696 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1697 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1698 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1699 .sysc_fields = &omap_hwmod_sysc_type2,
1702 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1704 .sysc = &dra7xx_mmc_sysc,
1708 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1709 { .role = "clk32k", .clk = "mmc1_clk32k" },
1713 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1714 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1717 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1719 .class = &dra7xx_mmc_hwmod_class,
1720 .clkdm_name = "l3init_clkdm",
1721 .main_clk = "mmc1_fclk_div",
1724 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1725 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1726 .modulemode = MODULEMODE_SWCTRL,
1729 .opt_clks = mmc1_opt_clks,
1730 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1731 .dev_attr = &mmc1_dev_attr,
1735 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1736 { .role = "clk32k", .clk = "mmc2_clk32k" },
1739 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1741 .class = &dra7xx_mmc_hwmod_class,
1742 .clkdm_name = "l3init_clkdm",
1743 .main_clk = "mmc2_fclk_div",
1746 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1747 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1748 .modulemode = MODULEMODE_SWCTRL,
1751 .opt_clks = mmc2_opt_clks,
1752 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1756 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1757 { .role = "clk32k", .clk = "mmc3_clk32k" },
1760 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1762 .class = &dra7xx_mmc_hwmod_class,
1763 .clkdm_name = "l4per_clkdm",
1764 .main_clk = "mmc3_gfclk_div",
1767 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1768 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1769 .modulemode = MODULEMODE_SWCTRL,
1772 .opt_clks = mmc3_opt_clks,
1773 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1777 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1778 { .role = "clk32k", .clk = "mmc4_clk32k" },
1781 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1783 .class = &dra7xx_mmc_hwmod_class,
1784 .clkdm_name = "l4per_clkdm",
1785 .main_clk = "mmc4_gfclk_div",
1788 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1789 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1790 .modulemode = MODULEMODE_SWCTRL,
1793 .opt_clks = mmc4_opt_clks,
1794 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1802 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1807 static struct omap_hwmod dra7xx_mpu_hwmod = {
1809 .class = &dra7xx_mpu_hwmod_class,
1810 .clkdm_name = "mpu_clkdm",
1811 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1812 .main_clk = "dpll_mpu_m2_ck",
1815 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1816 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1826 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1828 .sysc_offs = 0x0010,
1829 .syss_offs = 0x0014,
1830 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1831 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1832 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1833 .sysc_fields = &omap_hwmod_sysc_type1,
1836 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1838 .sysc = &dra7xx_ocp2scp_sysc,
1842 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1844 .class = &dra7xx_ocp2scp_hwmod_class,
1845 .clkdm_name = "l3init_clkdm",
1846 .main_clk = "l4_root_clk_div",
1849 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1850 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1851 .modulemode = MODULEMODE_HWCTRL,
1857 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1859 .class = &dra7xx_ocp2scp_hwmod_class,
1860 .clkdm_name = "l3init_clkdm",
1861 .main_clk = "l4_root_clk_div",
1864 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1865 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1866 .modulemode = MODULEMODE_HWCTRL,
1877 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1878 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1879 * associated with an IP automatically leaving the driver to handle that
1880 * by itself. This does not work for PCIeSS which needs the reset lines
1881 * deasserted for the driver to start accessing registers.
1883 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1884 * lines after asserting them.
1886 static int dra7xx_pciess_reset(struct omap_hwmod *oh)
1890 for (i = 0; i < oh->rst_lines_cnt; i++) {
1891 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1892 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1898 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1900 .reset = dra7xx_pciess_reset,
1904 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1905 { .name = "pcie", .rst_shift = 0 },
1908 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1910 .class = &dra7xx_pciess_hwmod_class,
1911 .clkdm_name = "pcie_clkdm",
1912 .rst_lines = dra7xx_pciess1_resets,
1913 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
1914 .main_clk = "l4_root_clk_div",
1917 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1918 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1919 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1920 .modulemode = MODULEMODE_SWCTRL,
1926 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1927 { .name = "pcie", .rst_shift = 1 },
1931 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1933 .class = &dra7xx_pciess_hwmod_class,
1934 .clkdm_name = "pcie_clkdm",
1935 .rst_lines = dra7xx_pciess2_resets,
1936 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
1937 .main_clk = "l4_root_clk_div",
1940 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1941 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1942 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1943 .modulemode = MODULEMODE_SWCTRL,
1953 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1954 .sysc_offs = 0x0010,
1955 .sysc_flags = SYSC_HAS_SIDLEMODE,
1956 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1958 .sysc_fields = &omap_hwmod_sysc_type2,
1961 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1963 .sysc = &dra7xx_qspi_sysc,
1967 static struct omap_hwmod dra7xx_qspi_hwmod = {
1969 .class = &dra7xx_qspi_hwmod_class,
1970 .clkdm_name = "l4per2_clkdm",
1971 .main_clk = "qspi_gfclk_div",
1974 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1975 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1976 .modulemode = MODULEMODE_SWCTRL,
1985 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1986 .sysc_offs = 0x0078,
1987 .sysc_flags = SYSC_HAS_SIDLEMODE,
1988 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1990 .sysc_fields = &omap_hwmod_sysc_type3,
1993 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1995 .sysc = &dra7xx_rtcss_sysc,
1996 .unlock = &omap_hwmod_rtc_unlock,
1997 .lock = &omap_hwmod_rtc_lock,
2001 static struct omap_hwmod dra7xx_rtcss_hwmod = {
2003 .class = &dra7xx_rtcss_hwmod_class,
2004 .clkdm_name = "rtc_clkdm",
2005 .main_clk = "sys_32k_ck",
2008 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
2009 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
2010 .modulemode = MODULEMODE_SWCTRL,
2020 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
2021 .sysc_offs = 0x0000,
2022 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
2023 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2024 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2025 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2026 .sysc_fields = &omap_hwmod_sysc_type2,
2029 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
2031 .sysc = &dra7xx_sata_sysc,
2036 static struct omap_hwmod dra7xx_sata_hwmod = {
2038 .class = &dra7xx_sata_hwmod_class,
2039 .clkdm_name = "l3init_clkdm",
2040 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2041 .main_clk = "func_48m_fclk",
2045 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
2046 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
2047 .modulemode = MODULEMODE_SWCTRL,
2053 * 'smartreflex' class
2057 /* The IP is not compliant to type1 / type2 scheme */
2058 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
2063 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
2064 .sysc_offs = 0x0038,
2065 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2066 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2068 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
2071 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
2072 .name = "smartreflex",
2073 .sysc = &dra7xx_smartreflex_sysc,
2077 /* smartreflex_core */
2078 /* smartreflex_core dev_attr */
2079 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2080 .sensor_voltdm_name = "core",
2083 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
2084 .name = "smartreflex_core",
2085 .class = &dra7xx_smartreflex_hwmod_class,
2086 .clkdm_name = "coreaon_clkdm",
2087 .main_clk = "wkupaon_iclk_mux",
2090 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
2091 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
2092 .modulemode = MODULEMODE_SWCTRL,
2095 .dev_attr = &smartreflex_core_dev_attr,
2098 /* smartreflex_mpu */
2099 /* smartreflex_mpu dev_attr */
2100 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2101 .sensor_voltdm_name = "mpu",
2104 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
2105 .name = "smartreflex_mpu",
2106 .class = &dra7xx_smartreflex_hwmod_class,
2107 .clkdm_name = "coreaon_clkdm",
2108 .main_clk = "wkupaon_iclk_mux",
2111 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
2112 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
2113 .modulemode = MODULEMODE_SWCTRL,
2116 .dev_attr = &smartreflex_mpu_dev_attr,
2124 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
2126 .sysc_offs = 0x0010,
2127 .syss_offs = 0x0014,
2128 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2129 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2130 SYSS_HAS_RESET_STATUS),
2131 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2132 .sysc_fields = &omap_hwmod_sysc_type1,
2135 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
2137 .sysc = &dra7xx_spinlock_sysc,
2141 static struct omap_hwmod dra7xx_spinlock_hwmod = {
2143 .class = &dra7xx_spinlock_hwmod_class,
2144 .clkdm_name = "l4cfg_clkdm",
2145 .main_clk = "l3_iclk_div",
2148 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
2149 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
2157 * This class contains several variants: ['timer_1ms', 'timer_secure',
2161 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
2163 .sysc_offs = 0x0010,
2164 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2165 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2166 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2168 .sysc_fields = &omap_hwmod_sysc_type2,
2171 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
2173 .sysc = &dra7xx_timer_1ms_sysc,
2176 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
2178 .sysc_offs = 0x0010,
2179 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2180 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2181 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2183 .sysc_fields = &omap_hwmod_sysc_type2,
2186 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
2188 .sysc = &dra7xx_timer_sysc,
2192 static struct omap_hwmod dra7xx_timer1_hwmod = {
2194 .class = &dra7xx_timer_1ms_hwmod_class,
2195 .clkdm_name = "wkupaon_clkdm",
2196 .main_clk = "timer1_gfclk_mux",
2199 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
2200 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
2201 .modulemode = MODULEMODE_SWCTRL,
2207 static struct omap_hwmod dra7xx_timer2_hwmod = {
2209 .class = &dra7xx_timer_1ms_hwmod_class,
2210 .clkdm_name = "l4per_clkdm",
2211 .main_clk = "timer2_gfclk_mux",
2214 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
2215 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
2216 .modulemode = MODULEMODE_SWCTRL,
2222 static struct omap_hwmod dra7xx_timer3_hwmod = {
2224 .class = &dra7xx_timer_hwmod_class,
2225 .clkdm_name = "l4per_clkdm",
2226 .main_clk = "timer3_gfclk_mux",
2229 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
2230 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
2231 .modulemode = MODULEMODE_SWCTRL,
2237 static struct omap_hwmod dra7xx_timer4_hwmod = {
2239 .class = &dra7xx_timer_hwmod_class,
2240 .clkdm_name = "l4per_clkdm",
2241 .main_clk = "timer4_gfclk_mux",
2244 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
2245 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
2246 .modulemode = MODULEMODE_SWCTRL,
2252 static struct omap_hwmod dra7xx_timer5_hwmod = {
2254 .class = &dra7xx_timer_hwmod_class,
2255 .clkdm_name = "ipu_clkdm",
2256 .main_clk = "timer5_gfclk_mux",
2259 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
2260 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
2261 .modulemode = MODULEMODE_SWCTRL,
2267 static struct omap_hwmod dra7xx_timer6_hwmod = {
2269 .class = &dra7xx_timer_hwmod_class,
2270 .clkdm_name = "ipu_clkdm",
2271 .main_clk = "timer6_gfclk_mux",
2274 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
2275 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
2276 .modulemode = MODULEMODE_SWCTRL,
2282 static struct omap_hwmod dra7xx_timer7_hwmod = {
2284 .class = &dra7xx_timer_hwmod_class,
2285 .clkdm_name = "ipu_clkdm",
2286 .main_clk = "timer7_gfclk_mux",
2289 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
2290 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
2291 .modulemode = MODULEMODE_SWCTRL,
2297 static struct omap_hwmod dra7xx_timer8_hwmod = {
2299 .class = &dra7xx_timer_hwmod_class,
2300 .clkdm_name = "ipu_clkdm",
2301 .main_clk = "timer8_gfclk_mux",
2304 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
2305 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
2306 .modulemode = MODULEMODE_SWCTRL,
2312 static struct omap_hwmod dra7xx_timer9_hwmod = {
2314 .class = &dra7xx_timer_hwmod_class,
2315 .clkdm_name = "l4per_clkdm",
2316 .main_clk = "timer9_gfclk_mux",
2319 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
2320 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
2321 .modulemode = MODULEMODE_SWCTRL,
2327 static struct omap_hwmod dra7xx_timer10_hwmod = {
2329 .class = &dra7xx_timer_1ms_hwmod_class,
2330 .clkdm_name = "l4per_clkdm",
2331 .main_clk = "timer10_gfclk_mux",
2334 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
2335 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
2336 .modulemode = MODULEMODE_SWCTRL,
2342 static struct omap_hwmod dra7xx_timer11_hwmod = {
2344 .class = &dra7xx_timer_hwmod_class,
2345 .clkdm_name = "l4per_clkdm",
2346 .main_clk = "timer11_gfclk_mux",
2349 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
2350 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
2351 .modulemode = MODULEMODE_SWCTRL,
2357 static struct omap_hwmod dra7xx_timer12_hwmod = {
2359 .class = &dra7xx_timer_hwmod_class,
2360 .clkdm_name = "wkupaon_clkdm",
2361 .main_clk = "secure_32k_clk_src_ck",
2364 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
2365 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
2371 static struct omap_hwmod dra7xx_timer13_hwmod = {
2373 .class = &dra7xx_timer_hwmod_class,
2374 .clkdm_name = "l4per3_clkdm",
2375 .main_clk = "timer13_gfclk_mux",
2378 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
2379 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
2380 .modulemode = MODULEMODE_SWCTRL,
2386 static struct omap_hwmod dra7xx_timer14_hwmod = {
2388 .class = &dra7xx_timer_hwmod_class,
2389 .clkdm_name = "l4per3_clkdm",
2390 .main_clk = "timer14_gfclk_mux",
2393 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
2394 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
2395 .modulemode = MODULEMODE_SWCTRL,
2401 static struct omap_hwmod dra7xx_timer15_hwmod = {
2403 .class = &dra7xx_timer_hwmod_class,
2404 .clkdm_name = "l4per3_clkdm",
2405 .main_clk = "timer15_gfclk_mux",
2408 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
2409 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
2410 .modulemode = MODULEMODE_SWCTRL,
2416 static struct omap_hwmod dra7xx_timer16_hwmod = {
2418 .class = &dra7xx_timer_hwmod_class,
2419 .clkdm_name = "l4per3_clkdm",
2420 .main_clk = "timer16_gfclk_mux",
2423 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
2424 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
2425 .modulemode = MODULEMODE_SWCTRL,
2435 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
2437 .sysc_offs = 0x0054,
2438 .syss_offs = 0x0058,
2439 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2440 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2441 SYSS_HAS_RESET_STATUS),
2442 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2444 .sysc_fields = &omap_hwmod_sysc_type1,
2447 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
2449 .sysc = &dra7xx_uart_sysc,
2453 static struct omap_hwmod dra7xx_uart1_hwmod = {
2455 .class = &dra7xx_uart_hwmod_class,
2456 .clkdm_name = "l4per_clkdm",
2457 .main_clk = "uart1_gfclk_mux",
2458 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
2461 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
2462 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
2463 .modulemode = MODULEMODE_SWCTRL,
2469 static struct omap_hwmod dra7xx_uart2_hwmod = {
2471 .class = &dra7xx_uart_hwmod_class,
2472 .clkdm_name = "l4per_clkdm",
2473 .main_clk = "uart2_gfclk_mux",
2474 .flags = HWMOD_SWSUP_SIDLE_ACT,
2477 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
2478 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
2479 .modulemode = MODULEMODE_SWCTRL,
2485 static struct omap_hwmod dra7xx_uart3_hwmod = {
2487 .class = &dra7xx_uart_hwmod_class,
2488 .clkdm_name = "l4per_clkdm",
2489 .main_clk = "uart3_gfclk_mux",
2490 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART3_FLAGS,
2493 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
2494 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
2495 .modulemode = MODULEMODE_SWCTRL,
2501 static struct omap_hwmod dra7xx_uart4_hwmod = {
2503 .class = &dra7xx_uart_hwmod_class,
2504 .clkdm_name = "l4per_clkdm",
2505 .main_clk = "uart4_gfclk_mux",
2506 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP4UART4_FLAGS,
2509 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
2510 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
2511 .modulemode = MODULEMODE_SWCTRL,
2517 static struct omap_hwmod dra7xx_uart5_hwmod = {
2519 .class = &dra7xx_uart_hwmod_class,
2520 .clkdm_name = "l4per_clkdm",
2521 .main_clk = "uart5_gfclk_mux",
2522 .flags = HWMOD_SWSUP_SIDLE_ACT,
2525 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
2526 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
2527 .modulemode = MODULEMODE_SWCTRL,
2533 static struct omap_hwmod dra7xx_uart6_hwmod = {
2535 .class = &dra7xx_uart_hwmod_class,
2536 .clkdm_name = "ipu_clkdm",
2537 .main_clk = "uart6_gfclk_mux",
2538 .flags = HWMOD_SWSUP_SIDLE_ACT,
2541 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
2542 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
2543 .modulemode = MODULEMODE_SWCTRL,
2549 static struct omap_hwmod dra7xx_uart7_hwmod = {
2551 .class = &dra7xx_uart_hwmod_class,
2552 .clkdm_name = "l4per2_clkdm",
2553 .main_clk = "uart7_gfclk_mux",
2554 .flags = HWMOD_SWSUP_SIDLE_ACT,
2557 .clkctrl_offs = DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET,
2558 .context_offs = DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET,
2559 .modulemode = MODULEMODE_SWCTRL,
2565 static struct omap_hwmod dra7xx_uart8_hwmod = {
2567 .class = &dra7xx_uart_hwmod_class,
2568 .clkdm_name = "l4per2_clkdm",
2569 .main_clk = "uart8_gfclk_mux",
2570 .flags = HWMOD_SWSUP_SIDLE_ACT,
2573 .clkctrl_offs = DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET,
2574 .context_offs = DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET,
2575 .modulemode = MODULEMODE_SWCTRL,
2581 static struct omap_hwmod dra7xx_uart9_hwmod = {
2583 .class = &dra7xx_uart_hwmod_class,
2584 .clkdm_name = "l4per2_clkdm",
2585 .main_clk = "uart9_gfclk_mux",
2586 .flags = HWMOD_SWSUP_SIDLE_ACT,
2589 .clkctrl_offs = DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET,
2590 .context_offs = DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET,
2591 .modulemode = MODULEMODE_SWCTRL,
2597 static struct omap_hwmod dra7xx_uart10_hwmod = {
2599 .class = &dra7xx_uart_hwmod_class,
2600 .clkdm_name = "wkupaon_clkdm",
2601 .main_clk = "uart10_gfclk_mux",
2602 .flags = HWMOD_SWSUP_SIDLE_ACT,
2605 .clkctrl_offs = DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET,
2606 .context_offs = DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET,
2607 .modulemode = MODULEMODE_SWCTRL,
2612 /* DES (the 'P' (public) device) */
2613 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
2615 .sysc_offs = 0x0034,
2616 .syss_offs = 0x0038,
2617 .sysc_flags = SYSS_HAS_RESET_STATUS,
2620 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
2622 .sysc = &dra7xx_des_sysc,
2626 static struct omap_hwmod dra7xx_des_hwmod = {
2628 .class = &dra7xx_des_hwmod_class,
2629 .clkdm_name = "l4sec_clkdm",
2630 .main_clk = "l3_iclk_div",
2633 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
2634 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
2635 .modulemode = MODULEMODE_HWCTRL,
2641 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
2643 .sysc_offs = 0x1fe4,
2644 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
2645 .idlemodes = SIDLE_FORCE | SIDLE_NO,
2646 .sysc_fields = &omap_hwmod_sysc_type1,
2649 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
2651 .sysc = &dra7xx_rng_sysc,
2654 static struct omap_hwmod dra7xx_rng_hwmod = {
2656 .class = &dra7xx_rng_hwmod_class,
2657 .flags = HWMOD_SWSUP_SIDLE,
2658 .clkdm_name = "l4sec_clkdm",
2661 .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2662 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2663 .modulemode = MODULEMODE_HWCTRL,
2669 * 'usb_otg_ss' class
2673 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2675 .sysc_offs = 0x0010,
2676 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2677 SYSC_HAS_SIDLEMODE),
2678 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2679 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2680 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2681 .sysc_fields = &omap_hwmod_sysc_type2,
2684 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2685 .name = "usb_otg_ss",
2686 .sysc = &dra7xx_usb_otg_ss_sysc,
2690 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2691 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2694 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2695 .name = "usb_otg_ss1",
2696 .class = &dra7xx_usb_otg_ss_hwmod_class,
2697 .clkdm_name = "l3init_clkdm",
2698 .main_clk = "dpll_core_h13x2_ck",
2699 .flags = HWMOD_CLKDM_NOAUTO,
2702 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2703 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2704 .modulemode = MODULEMODE_HWCTRL,
2707 .opt_clks = usb_otg_ss1_opt_clks,
2708 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2712 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2713 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2716 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2717 .name = "usb_otg_ss2",
2718 .class = &dra7xx_usb_otg_ss_hwmod_class,
2719 .clkdm_name = "l3init_clkdm",
2720 .main_clk = "dpll_core_h13x2_ck",
2721 .flags = HWMOD_CLKDM_NOAUTO,
2724 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2725 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2726 .modulemode = MODULEMODE_HWCTRL,
2729 .opt_clks = usb_otg_ss2_opt_clks,
2730 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2734 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2735 .name = "usb_otg_ss3",
2736 .class = &dra7xx_usb_otg_ss_hwmod_class,
2737 .clkdm_name = "l3init_clkdm",
2738 .main_clk = "dpll_core_h13x2_ck",
2741 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2742 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2743 .modulemode = MODULEMODE_HWCTRL,
2749 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2750 .name = "usb_otg_ss4",
2751 .class = &dra7xx_usb_otg_ss_hwmod_class,
2752 .clkdm_name = "l3init_clkdm",
2753 .main_clk = "dpll_core_h13x2_ck",
2756 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2757 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2758 .modulemode = MODULEMODE_HWCTRL,
2768 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2773 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2775 .class = &dra7xx_vcp_hwmod_class,
2776 .clkdm_name = "l3main1_clkdm",
2777 .main_clk = "l3_iclk_div",
2780 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2781 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2787 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2789 .class = &dra7xx_vcp_hwmod_class,
2790 .clkdm_name = "l3main1_clkdm",
2791 .main_clk = "l3_iclk_div",
2794 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2795 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2805 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2807 .sysc_offs = 0x0010,
2808 .syss_offs = 0x0014,
2809 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2810 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2811 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2813 .sysc_fields = &omap_hwmod_sysc_type1,
2816 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2818 .sysc = &dra7xx_wd_timer_sysc,
2819 .pre_shutdown = &omap2_wd_timer_disable,
2820 .reset = &omap2_wd_timer_reset,
2824 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2825 .name = "wd_timer2",
2826 .class = &dra7xx_wd_timer_hwmod_class,
2827 .clkdm_name = "wkupaon_clkdm",
2828 .main_clk = "sys_32k_ck",
2831 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2832 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2833 .modulemode = MODULEMODE_SWCTRL,
2843 /* l3_main_1 -> dmm */
2844 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2845 .master = &dra7xx_l3_main_1_hwmod,
2846 .slave = &dra7xx_dmm_hwmod,
2847 .clk = "l3_iclk_div",
2848 .user = OCP_USER_SDMA,
2851 /* l3_main_2 -> l3_instr */
2852 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2853 .master = &dra7xx_l3_main_2_hwmod,
2854 .slave = &dra7xx_l3_instr_hwmod,
2855 .clk = "l3_iclk_div",
2856 .user = OCP_USER_MPU | OCP_USER_SDMA,
2859 /* l4_cfg -> l3_main_1 */
2860 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2861 .master = &dra7xx_l4_cfg_hwmod,
2862 .slave = &dra7xx_l3_main_1_hwmod,
2863 .clk = "l3_iclk_div",
2864 .user = OCP_USER_MPU | OCP_USER_SDMA,
2867 /* mpu -> l3_main_1 */
2868 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2869 .master = &dra7xx_mpu_hwmod,
2870 .slave = &dra7xx_l3_main_1_hwmod,
2871 .clk = "l3_iclk_div",
2872 .user = OCP_USER_MPU,
2875 /* l3_main_1 -> l3_main_2 */
2876 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2877 .master = &dra7xx_l3_main_1_hwmod,
2878 .slave = &dra7xx_l3_main_2_hwmod,
2879 .clk = "l3_iclk_div",
2880 .user = OCP_USER_MPU,
2883 /* l4_cfg -> l3_main_2 */
2884 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2885 .master = &dra7xx_l4_cfg_hwmod,
2886 .slave = &dra7xx_l3_main_2_hwmod,
2887 .clk = "l3_iclk_div",
2888 .user = OCP_USER_MPU | OCP_USER_SDMA,
2891 /* l3_main_1 -> l4_cfg */
2892 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2893 .master = &dra7xx_l3_main_1_hwmod,
2894 .slave = &dra7xx_l4_cfg_hwmod,
2895 .clk = "l3_iclk_div",
2896 .user = OCP_USER_MPU | OCP_USER_SDMA,
2899 /* l3_main_1 -> l4_per1 */
2900 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2901 .master = &dra7xx_l3_main_1_hwmod,
2902 .slave = &dra7xx_l4_per1_hwmod,
2903 .clk = "l3_iclk_div",
2904 .user = OCP_USER_MPU | OCP_USER_SDMA,
2907 /* l3_main_1 -> l4_per2 */
2908 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2909 .master = &dra7xx_l3_main_1_hwmod,
2910 .slave = &dra7xx_l4_per2_hwmod,
2911 .clk = "l3_iclk_div",
2912 .user = OCP_USER_MPU | OCP_USER_SDMA,
2915 /* l3_main_1 -> l4_per3 */
2916 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2917 .master = &dra7xx_l3_main_1_hwmod,
2918 .slave = &dra7xx_l4_per3_hwmod,
2919 .clk = "l3_iclk_div",
2920 .user = OCP_USER_MPU | OCP_USER_SDMA,
2923 /* l3_main_1 -> l4_wkup */
2924 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2925 .master = &dra7xx_l3_main_1_hwmod,
2926 .slave = &dra7xx_l4_wkup_hwmod,
2927 .clk = "wkupaon_iclk_mux",
2928 .user = OCP_USER_MPU | OCP_USER_SDMA,
2931 /* l4_per2 -> atl */
2932 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2933 .master = &dra7xx_l4_per2_hwmod,
2934 .slave = &dra7xx_atl_hwmod,
2935 .clk = "l3_iclk_div",
2936 .user = OCP_USER_MPU | OCP_USER_SDMA,
2939 /* l3_main_1 -> bb2d */
2940 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2941 .master = &dra7xx_l3_main_1_hwmod,
2942 .slave = &dra7xx_bb2d_hwmod,
2943 .clk = "l3_iclk_div",
2944 .user = OCP_USER_MPU | OCP_USER_SDMA,
2947 /* l4_wkup -> counter_32k */
2948 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2949 .master = &dra7xx_l4_wkup_hwmod,
2950 .slave = &dra7xx_counter_32k_hwmod,
2951 .clk = "wkupaon_iclk_mux",
2952 .user = OCP_USER_MPU | OCP_USER_SDMA,
2955 /* l4_wkup -> ctrl_module_wkup */
2956 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2957 .master = &dra7xx_l4_wkup_hwmod,
2958 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2959 .clk = "wkupaon_iclk_mux",
2960 .user = OCP_USER_MPU | OCP_USER_SDMA,
2963 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2964 .master = &dra7xx_l4_per2_hwmod,
2965 .slave = &dra7xx_gmac_hwmod,
2966 .clk = "dpll_gmac_ck",
2967 .user = OCP_USER_MPU,
2970 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2971 .master = &dra7xx_gmac_hwmod,
2972 .slave = &dra7xx_mdio_hwmod,
2973 .user = OCP_USER_MPU,
2976 /* l4_wkup -> dcan1 */
2977 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2978 .master = &dra7xx_l4_wkup_hwmod,
2979 .slave = &dra7xx_dcan1_hwmod,
2980 .clk = "wkupaon_iclk_mux",
2981 .user = OCP_USER_MPU | OCP_USER_SDMA,
2984 /* l4_per2 -> dcan2 */
2985 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2986 .master = &dra7xx_l4_per2_hwmod,
2987 .slave = &dra7xx_dcan2_hwmod,
2988 .clk = "l3_iclk_div",
2989 .user = OCP_USER_MPU | OCP_USER_SDMA,
2992 /* l4_cfg -> dma_system */
2993 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2994 .master = &dra7xx_l4_cfg_hwmod,
2995 .slave = &dra7xx_dma_system_hwmod,
2996 .clk = "l3_iclk_div",
2997 .user = OCP_USER_MPU | OCP_USER_SDMA,
3000 /* l3_main_1 -> tpcc */
3001 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
3002 .master = &dra7xx_l3_main_1_hwmod,
3003 .slave = &dra7xx_tpcc_hwmod,
3004 .clk = "l3_iclk_div",
3005 .user = OCP_USER_MPU,
3008 /* l3_main_1 -> tptc0 */
3009 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
3010 .master = &dra7xx_l3_main_1_hwmod,
3011 .slave = &dra7xx_tptc0_hwmod,
3012 .clk = "l3_iclk_div",
3013 .user = OCP_USER_MPU,
3016 /* l3_main_1 -> tptc1 */
3017 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
3018 .master = &dra7xx_l3_main_1_hwmod,
3019 .slave = &dra7xx_tptc1_hwmod,
3020 .clk = "l3_iclk_div",
3021 .user = OCP_USER_MPU,
3024 /* l3_main_1 -> dss */
3025 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
3026 .master = &dra7xx_l3_main_1_hwmod,
3027 .slave = &dra7xx_dss_hwmod,
3028 .clk = "l3_iclk_div",
3029 .user = OCP_USER_MPU | OCP_USER_SDMA,
3032 /* l3_main_1 -> dispc */
3033 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
3034 .master = &dra7xx_l3_main_1_hwmod,
3035 .slave = &dra7xx_dss_dispc_hwmod,
3036 .clk = "l3_iclk_div",
3037 .user = OCP_USER_MPU | OCP_USER_SDMA,
3040 /* l3_main_1 -> dispc */
3041 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
3042 .master = &dra7xx_l3_main_1_hwmod,
3043 .slave = &dra7xx_dss_hdmi_hwmod,
3044 .clk = "l3_iclk_div",
3045 .user = OCP_USER_MPU | OCP_USER_SDMA,
3048 /* l3_main_1 -> aes1 */
3049 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
3050 .master = &dra7xx_l3_main_1_hwmod,
3051 .slave = &dra7xx_aes1_hwmod,
3052 .clk = "l3_iclk_div",
3053 .user = OCP_USER_MPU | OCP_USER_SDMA,
3056 /* l3_main_1 -> aes2 */
3057 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
3058 .master = &dra7xx_l3_main_1_hwmod,
3059 .slave = &dra7xx_aes2_hwmod,
3060 .clk = "l3_iclk_div",
3061 .user = OCP_USER_MPU | OCP_USER_SDMA,
3064 /* l3_main_1 -> sha0 */
3065 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
3066 .master = &dra7xx_l3_main_1_hwmod,
3067 .slave = &dra7xx_sha0_hwmod,
3068 .clk = "l3_iclk_div",
3069 .user = OCP_USER_MPU | OCP_USER_SDMA,
3072 /* l4_per2 -> mcasp1 */
3073 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
3074 .master = &dra7xx_l4_per2_hwmod,
3075 .slave = &dra7xx_mcasp1_hwmod,
3076 .clk = "l4_root_clk_div",
3077 .user = OCP_USER_MPU | OCP_USER_SDMA,
3080 /* l3_main_1 -> mcasp1 */
3081 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
3082 .master = &dra7xx_l3_main_1_hwmod,
3083 .slave = &dra7xx_mcasp1_hwmod,
3084 .clk = "l3_iclk_div",
3085 .user = OCP_USER_MPU | OCP_USER_SDMA,
3088 /* l4_per2 -> mcasp2 */
3089 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
3090 .master = &dra7xx_l4_per2_hwmod,
3091 .slave = &dra7xx_mcasp2_hwmod,
3092 .clk = "l4_root_clk_div",
3093 .user = OCP_USER_MPU | OCP_USER_SDMA,
3096 /* l3_main_1 -> mcasp2 */
3097 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
3098 .master = &dra7xx_l3_main_1_hwmod,
3099 .slave = &dra7xx_mcasp2_hwmod,
3100 .clk = "l3_iclk_div",
3101 .user = OCP_USER_MPU | OCP_USER_SDMA,
3104 /* l4_per2 -> mcasp3 */
3105 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
3106 .master = &dra7xx_l4_per2_hwmod,
3107 .slave = &dra7xx_mcasp3_hwmod,
3108 .clk = "l4_root_clk_div",
3109 .user = OCP_USER_MPU | OCP_USER_SDMA,
3112 /* l3_main_1 -> mcasp3 */
3113 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
3114 .master = &dra7xx_l3_main_1_hwmod,
3115 .slave = &dra7xx_mcasp3_hwmod,
3116 .clk = "l3_iclk_div",
3117 .user = OCP_USER_MPU | OCP_USER_SDMA,
3120 /* l4_per2 -> mcasp4 */
3121 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
3122 .master = &dra7xx_l4_per2_hwmod,
3123 .slave = &dra7xx_mcasp4_hwmod,
3124 .clk = "l4_root_clk_div",
3125 .user = OCP_USER_MPU | OCP_USER_SDMA,
3128 /* l4_per2 -> mcasp5 */
3129 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
3130 .master = &dra7xx_l4_per2_hwmod,
3131 .slave = &dra7xx_mcasp5_hwmod,
3132 .clk = "l4_root_clk_div",
3133 .user = OCP_USER_MPU | OCP_USER_SDMA,
3136 /* l4_per2 -> mcasp6 */
3137 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
3138 .master = &dra7xx_l4_per2_hwmod,
3139 .slave = &dra7xx_mcasp6_hwmod,
3140 .clk = "l4_root_clk_div",
3141 .user = OCP_USER_MPU | OCP_USER_SDMA,
3144 /* l4_per2 -> mcasp7 */
3145 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
3146 .master = &dra7xx_l4_per2_hwmod,
3147 .slave = &dra7xx_mcasp7_hwmod,
3148 .clk = "l4_root_clk_div",
3149 .user = OCP_USER_MPU | OCP_USER_SDMA,
3152 /* l4_per2 -> mcasp8 */
3153 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
3154 .master = &dra7xx_l4_per2_hwmod,
3155 .slave = &dra7xx_mcasp8_hwmod,
3156 .clk = "l4_root_clk_div",
3157 .user = OCP_USER_MPU | OCP_USER_SDMA,
3160 /* l4_per1 -> elm */
3161 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
3162 .master = &dra7xx_l4_per1_hwmod,
3163 .slave = &dra7xx_elm_hwmod,
3164 .clk = "l3_iclk_div",
3165 .user = OCP_USER_MPU | OCP_USER_SDMA,
3168 /* l4_wkup -> gpio1 */
3169 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
3170 .master = &dra7xx_l4_wkup_hwmod,
3171 .slave = &dra7xx_gpio1_hwmod,
3172 .clk = "wkupaon_iclk_mux",
3173 .user = OCP_USER_MPU | OCP_USER_SDMA,
3176 /* l4_per1 -> gpio2 */
3177 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
3178 .master = &dra7xx_l4_per1_hwmod,
3179 .slave = &dra7xx_gpio2_hwmod,
3180 .clk = "l3_iclk_div",
3181 .user = OCP_USER_MPU | OCP_USER_SDMA,
3184 /* l4_per1 -> gpio3 */
3185 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
3186 .master = &dra7xx_l4_per1_hwmod,
3187 .slave = &dra7xx_gpio3_hwmod,
3188 .clk = "l3_iclk_div",
3189 .user = OCP_USER_MPU | OCP_USER_SDMA,
3192 /* l4_per1 -> gpio4 */
3193 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
3194 .master = &dra7xx_l4_per1_hwmod,
3195 .slave = &dra7xx_gpio4_hwmod,
3196 .clk = "l3_iclk_div",
3197 .user = OCP_USER_MPU | OCP_USER_SDMA,
3200 /* l4_per1 -> gpio5 */
3201 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
3202 .master = &dra7xx_l4_per1_hwmod,
3203 .slave = &dra7xx_gpio5_hwmod,
3204 .clk = "l3_iclk_div",
3205 .user = OCP_USER_MPU | OCP_USER_SDMA,
3208 /* l4_per1 -> gpio6 */
3209 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
3210 .master = &dra7xx_l4_per1_hwmod,
3211 .slave = &dra7xx_gpio6_hwmod,
3212 .clk = "l3_iclk_div",
3213 .user = OCP_USER_MPU | OCP_USER_SDMA,
3216 /* l4_per1 -> gpio7 */
3217 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
3218 .master = &dra7xx_l4_per1_hwmod,
3219 .slave = &dra7xx_gpio7_hwmod,
3220 .clk = "l3_iclk_div",
3221 .user = OCP_USER_MPU | OCP_USER_SDMA,
3224 /* l4_per1 -> gpio8 */
3225 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
3226 .master = &dra7xx_l4_per1_hwmod,
3227 .slave = &dra7xx_gpio8_hwmod,
3228 .clk = "l3_iclk_div",
3229 .user = OCP_USER_MPU | OCP_USER_SDMA,
3232 /* l3_main_1 -> gpmc */
3233 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
3234 .master = &dra7xx_l3_main_1_hwmod,
3235 .slave = &dra7xx_gpmc_hwmod,
3236 .clk = "l3_iclk_div",
3237 .user = OCP_USER_MPU | OCP_USER_SDMA,
3240 /* l4_per1 -> hdq1w */
3241 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
3242 .master = &dra7xx_l4_per1_hwmod,
3243 .slave = &dra7xx_hdq1w_hwmod,
3244 .clk = "l3_iclk_div",
3245 .user = OCP_USER_MPU | OCP_USER_SDMA,
3248 /* l4_per1 -> i2c1 */
3249 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
3250 .master = &dra7xx_l4_per1_hwmod,
3251 .slave = &dra7xx_i2c1_hwmod,
3252 .clk = "l3_iclk_div",
3253 .user = OCP_USER_MPU | OCP_USER_SDMA,
3256 /* l4_per1 -> i2c2 */
3257 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
3258 .master = &dra7xx_l4_per1_hwmod,
3259 .slave = &dra7xx_i2c2_hwmod,
3260 .clk = "l3_iclk_div",
3261 .user = OCP_USER_MPU | OCP_USER_SDMA,
3264 /* l4_per1 -> i2c3 */
3265 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
3266 .master = &dra7xx_l4_per1_hwmod,
3267 .slave = &dra7xx_i2c3_hwmod,
3268 .clk = "l3_iclk_div",
3269 .user = OCP_USER_MPU | OCP_USER_SDMA,
3272 /* l4_per1 -> i2c4 */
3273 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
3274 .master = &dra7xx_l4_per1_hwmod,
3275 .slave = &dra7xx_i2c4_hwmod,
3276 .clk = "l3_iclk_div",
3277 .user = OCP_USER_MPU | OCP_USER_SDMA,
3280 /* l4_per1 -> i2c5 */
3281 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
3282 .master = &dra7xx_l4_per1_hwmod,
3283 .slave = &dra7xx_i2c5_hwmod,
3284 .clk = "l3_iclk_div",
3285 .user = OCP_USER_MPU | OCP_USER_SDMA,
3288 /* l4_cfg -> mailbox1 */
3289 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
3290 .master = &dra7xx_l4_cfg_hwmod,
3291 .slave = &dra7xx_mailbox1_hwmod,
3292 .clk = "l3_iclk_div",
3293 .user = OCP_USER_MPU | OCP_USER_SDMA,
3296 /* l4_per3 -> mailbox2 */
3297 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
3298 .master = &dra7xx_l4_per3_hwmod,
3299 .slave = &dra7xx_mailbox2_hwmod,
3300 .clk = "l3_iclk_div",
3301 .user = OCP_USER_MPU | OCP_USER_SDMA,
3304 /* l4_per3 -> mailbox3 */
3305 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
3306 .master = &dra7xx_l4_per3_hwmod,
3307 .slave = &dra7xx_mailbox3_hwmod,
3308 .clk = "l3_iclk_div",
3309 .user = OCP_USER_MPU | OCP_USER_SDMA,
3312 /* l4_per3 -> mailbox4 */
3313 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
3314 .master = &dra7xx_l4_per3_hwmod,
3315 .slave = &dra7xx_mailbox4_hwmod,
3316 .clk = "l3_iclk_div",
3317 .user = OCP_USER_MPU | OCP_USER_SDMA,
3320 /* l4_per3 -> mailbox5 */
3321 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
3322 .master = &dra7xx_l4_per3_hwmod,
3323 .slave = &dra7xx_mailbox5_hwmod,
3324 .clk = "l3_iclk_div",
3325 .user = OCP_USER_MPU | OCP_USER_SDMA,
3328 /* l4_per3 -> mailbox6 */
3329 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
3330 .master = &dra7xx_l4_per3_hwmod,
3331 .slave = &dra7xx_mailbox6_hwmod,
3332 .clk = "l3_iclk_div",
3333 .user = OCP_USER_MPU | OCP_USER_SDMA,
3336 /* l4_per3 -> mailbox7 */
3337 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
3338 .master = &dra7xx_l4_per3_hwmod,
3339 .slave = &dra7xx_mailbox7_hwmod,
3340 .clk = "l3_iclk_div",
3341 .user = OCP_USER_MPU | OCP_USER_SDMA,
3344 /* l4_per3 -> mailbox8 */
3345 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
3346 .master = &dra7xx_l4_per3_hwmod,
3347 .slave = &dra7xx_mailbox8_hwmod,
3348 .clk = "l3_iclk_div",
3349 .user = OCP_USER_MPU | OCP_USER_SDMA,
3352 /* l4_per3 -> mailbox9 */
3353 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
3354 .master = &dra7xx_l4_per3_hwmod,
3355 .slave = &dra7xx_mailbox9_hwmod,
3356 .clk = "l3_iclk_div",
3357 .user = OCP_USER_MPU | OCP_USER_SDMA,
3360 /* l4_per3 -> mailbox10 */
3361 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
3362 .master = &dra7xx_l4_per3_hwmod,
3363 .slave = &dra7xx_mailbox10_hwmod,
3364 .clk = "l3_iclk_div",
3365 .user = OCP_USER_MPU | OCP_USER_SDMA,
3368 /* l4_per3 -> mailbox11 */
3369 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
3370 .master = &dra7xx_l4_per3_hwmod,
3371 .slave = &dra7xx_mailbox11_hwmod,
3372 .clk = "l3_iclk_div",
3373 .user = OCP_USER_MPU | OCP_USER_SDMA,
3376 /* l4_per3 -> mailbox12 */
3377 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
3378 .master = &dra7xx_l4_per3_hwmod,
3379 .slave = &dra7xx_mailbox12_hwmod,
3380 .clk = "l3_iclk_div",
3381 .user = OCP_USER_MPU | OCP_USER_SDMA,
3384 /* l4_per3 -> mailbox13 */
3385 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
3386 .master = &dra7xx_l4_per3_hwmod,
3387 .slave = &dra7xx_mailbox13_hwmod,
3388 .clk = "l3_iclk_div",
3389 .user = OCP_USER_MPU | OCP_USER_SDMA,
3392 /* l4_per1 -> mcspi1 */
3393 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
3394 .master = &dra7xx_l4_per1_hwmod,
3395 .slave = &dra7xx_mcspi1_hwmod,
3396 .clk = "l3_iclk_div",
3397 .user = OCP_USER_MPU | OCP_USER_SDMA,
3400 /* l4_per1 -> mcspi2 */
3401 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
3402 .master = &dra7xx_l4_per1_hwmod,
3403 .slave = &dra7xx_mcspi2_hwmod,
3404 .clk = "l3_iclk_div",
3405 .user = OCP_USER_MPU | OCP_USER_SDMA,
3408 /* l4_per1 -> mcspi3 */
3409 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
3410 .master = &dra7xx_l4_per1_hwmod,
3411 .slave = &dra7xx_mcspi3_hwmod,
3412 .clk = "l3_iclk_div",
3413 .user = OCP_USER_MPU | OCP_USER_SDMA,
3416 /* l4_per1 -> mcspi4 */
3417 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
3418 .master = &dra7xx_l4_per1_hwmod,
3419 .slave = &dra7xx_mcspi4_hwmod,
3420 .clk = "l3_iclk_div",
3421 .user = OCP_USER_MPU | OCP_USER_SDMA,
3424 /* l4_per1 -> mmc1 */
3425 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
3426 .master = &dra7xx_l4_per1_hwmod,
3427 .slave = &dra7xx_mmc1_hwmod,
3428 .clk = "l3_iclk_div",
3429 .user = OCP_USER_MPU | OCP_USER_SDMA,
3432 /* l4_per1 -> mmc2 */
3433 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
3434 .master = &dra7xx_l4_per1_hwmod,
3435 .slave = &dra7xx_mmc2_hwmod,
3436 .clk = "l3_iclk_div",
3437 .user = OCP_USER_MPU | OCP_USER_SDMA,
3440 /* l4_per1 -> mmc3 */
3441 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
3442 .master = &dra7xx_l4_per1_hwmod,
3443 .slave = &dra7xx_mmc3_hwmod,
3444 .clk = "l3_iclk_div",
3445 .user = OCP_USER_MPU | OCP_USER_SDMA,
3448 /* l4_per1 -> mmc4 */
3449 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
3450 .master = &dra7xx_l4_per1_hwmod,
3451 .slave = &dra7xx_mmc4_hwmod,
3452 .clk = "l3_iclk_div",
3453 .user = OCP_USER_MPU | OCP_USER_SDMA,
3457 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
3458 .master = &dra7xx_l4_cfg_hwmod,
3459 .slave = &dra7xx_mpu_hwmod,
3460 .clk = "l3_iclk_div",
3461 .user = OCP_USER_MPU | OCP_USER_SDMA,
3464 /* l4_cfg -> ocp2scp1 */
3465 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
3466 .master = &dra7xx_l4_cfg_hwmod,
3467 .slave = &dra7xx_ocp2scp1_hwmod,
3468 .clk = "l4_root_clk_div",
3469 .user = OCP_USER_MPU | OCP_USER_SDMA,
3472 /* l4_cfg -> ocp2scp3 */
3473 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
3474 .master = &dra7xx_l4_cfg_hwmod,
3475 .slave = &dra7xx_ocp2scp3_hwmod,
3476 .clk = "l4_root_clk_div",
3477 .user = OCP_USER_MPU | OCP_USER_SDMA,
3480 /* l3_main_1 -> pciess1 */
3481 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
3482 .master = &dra7xx_l3_main_1_hwmod,
3483 .slave = &dra7xx_pciess1_hwmod,
3484 .clk = "l3_iclk_div",
3485 .user = OCP_USER_MPU | OCP_USER_SDMA,
3488 /* l4_cfg -> pciess1 */
3489 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
3490 .master = &dra7xx_l4_cfg_hwmod,
3491 .slave = &dra7xx_pciess1_hwmod,
3492 .clk = "l4_root_clk_div",
3493 .user = OCP_USER_MPU | OCP_USER_SDMA,
3496 /* l3_main_1 -> pciess2 */
3497 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
3498 .master = &dra7xx_l3_main_1_hwmod,
3499 .slave = &dra7xx_pciess2_hwmod,
3500 .clk = "l3_iclk_div",
3501 .user = OCP_USER_MPU | OCP_USER_SDMA,
3504 /* l4_cfg -> pciess2 */
3505 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
3506 .master = &dra7xx_l4_cfg_hwmod,
3507 .slave = &dra7xx_pciess2_hwmod,
3508 .clk = "l4_root_clk_div",
3509 .user = OCP_USER_MPU | OCP_USER_SDMA,
3512 /* l3_main_1 -> qspi */
3513 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
3514 .master = &dra7xx_l3_main_1_hwmod,
3515 .slave = &dra7xx_qspi_hwmod,
3516 .clk = "l3_iclk_div",
3517 .user = OCP_USER_MPU | OCP_USER_SDMA,
3520 /* l4_per3 -> rtcss */
3521 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
3522 .master = &dra7xx_l4_per3_hwmod,
3523 .slave = &dra7xx_rtcss_hwmod,
3524 .clk = "l4_root_clk_div",
3525 .user = OCP_USER_MPU | OCP_USER_SDMA,
3528 /* l4_cfg -> sata */
3529 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
3530 .master = &dra7xx_l4_cfg_hwmod,
3531 .slave = &dra7xx_sata_hwmod,
3532 .clk = "l3_iclk_div",
3533 .user = OCP_USER_MPU | OCP_USER_SDMA,
3536 /* l4_cfg -> smartreflex_core */
3537 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
3538 .master = &dra7xx_l4_cfg_hwmod,
3539 .slave = &dra7xx_smartreflex_core_hwmod,
3540 .clk = "l4_root_clk_div",
3541 .user = OCP_USER_MPU | OCP_USER_SDMA,
3544 /* l4_cfg -> smartreflex_mpu */
3545 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
3546 .master = &dra7xx_l4_cfg_hwmod,
3547 .slave = &dra7xx_smartreflex_mpu_hwmod,
3548 .clk = "l4_root_clk_div",
3549 .user = OCP_USER_MPU | OCP_USER_SDMA,
3552 /* l4_cfg -> spinlock */
3553 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
3554 .master = &dra7xx_l4_cfg_hwmod,
3555 .slave = &dra7xx_spinlock_hwmod,
3556 .clk = "l3_iclk_div",
3557 .user = OCP_USER_MPU | OCP_USER_SDMA,
3560 /* l4_wkup -> timer1 */
3561 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
3562 .master = &dra7xx_l4_wkup_hwmod,
3563 .slave = &dra7xx_timer1_hwmod,
3564 .clk = "wkupaon_iclk_mux",
3565 .user = OCP_USER_MPU | OCP_USER_SDMA,
3568 /* l4_per1 -> timer2 */
3569 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
3570 .master = &dra7xx_l4_per1_hwmod,
3571 .slave = &dra7xx_timer2_hwmod,
3572 .clk = "l3_iclk_div",
3573 .user = OCP_USER_MPU | OCP_USER_SDMA,
3576 /* l4_per1 -> timer3 */
3577 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
3578 .master = &dra7xx_l4_per1_hwmod,
3579 .slave = &dra7xx_timer3_hwmod,
3580 .clk = "l3_iclk_div",
3581 .user = OCP_USER_MPU | OCP_USER_SDMA,
3584 /* l4_per1 -> timer4 */
3585 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
3586 .master = &dra7xx_l4_per1_hwmod,
3587 .slave = &dra7xx_timer4_hwmod,
3588 .clk = "l3_iclk_div",
3589 .user = OCP_USER_MPU | OCP_USER_SDMA,
3592 /* l4_per3 -> timer5 */
3593 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
3594 .master = &dra7xx_l4_per3_hwmod,
3595 .slave = &dra7xx_timer5_hwmod,
3596 .clk = "l3_iclk_div",
3597 .user = OCP_USER_MPU | OCP_USER_SDMA,
3600 /* l4_per3 -> timer6 */
3601 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
3602 .master = &dra7xx_l4_per3_hwmod,
3603 .slave = &dra7xx_timer6_hwmod,
3604 .clk = "l3_iclk_div",
3605 .user = OCP_USER_MPU | OCP_USER_SDMA,
3608 /* l4_per3 -> timer7 */
3609 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
3610 .master = &dra7xx_l4_per3_hwmod,
3611 .slave = &dra7xx_timer7_hwmod,
3612 .clk = "l3_iclk_div",
3613 .user = OCP_USER_MPU | OCP_USER_SDMA,
3616 /* l4_per3 -> timer8 */
3617 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
3618 .master = &dra7xx_l4_per3_hwmod,
3619 .slave = &dra7xx_timer8_hwmod,
3620 .clk = "l3_iclk_div",
3621 .user = OCP_USER_MPU | OCP_USER_SDMA,
3624 /* l4_per1 -> timer9 */
3625 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
3626 .master = &dra7xx_l4_per1_hwmod,
3627 .slave = &dra7xx_timer9_hwmod,
3628 .clk = "l3_iclk_div",
3629 .user = OCP_USER_MPU | OCP_USER_SDMA,
3632 /* l4_per1 -> timer10 */
3633 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
3634 .master = &dra7xx_l4_per1_hwmod,
3635 .slave = &dra7xx_timer10_hwmod,
3636 .clk = "l3_iclk_div",
3637 .user = OCP_USER_MPU | OCP_USER_SDMA,
3640 /* l4_per1 -> timer11 */
3641 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
3642 .master = &dra7xx_l4_per1_hwmod,
3643 .slave = &dra7xx_timer11_hwmod,
3644 .clk = "l3_iclk_div",
3645 .user = OCP_USER_MPU | OCP_USER_SDMA,
3648 /* l4_wkup -> timer12 */
3649 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
3650 .master = &dra7xx_l4_wkup_hwmod,
3651 .slave = &dra7xx_timer12_hwmod,
3652 .clk = "wkupaon_iclk_mux",
3653 .user = OCP_USER_MPU | OCP_USER_SDMA,
3656 /* l4_per3 -> timer13 */
3657 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
3658 .master = &dra7xx_l4_per3_hwmod,
3659 .slave = &dra7xx_timer13_hwmod,
3660 .clk = "l3_iclk_div",
3661 .user = OCP_USER_MPU | OCP_USER_SDMA,
3664 /* l4_per3 -> timer14 */
3665 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
3666 .master = &dra7xx_l4_per3_hwmod,
3667 .slave = &dra7xx_timer14_hwmod,
3668 .clk = "l3_iclk_div",
3669 .user = OCP_USER_MPU | OCP_USER_SDMA,
3672 /* l4_per3 -> timer15 */
3673 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
3674 .master = &dra7xx_l4_per3_hwmod,
3675 .slave = &dra7xx_timer15_hwmod,
3676 .clk = "l3_iclk_div",
3677 .user = OCP_USER_MPU | OCP_USER_SDMA,
3680 /* l4_per3 -> timer16 */
3681 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
3682 .master = &dra7xx_l4_per3_hwmod,
3683 .slave = &dra7xx_timer16_hwmod,
3684 .clk = "l3_iclk_div",
3685 .user = OCP_USER_MPU | OCP_USER_SDMA,
3688 /* l4_per1 -> uart1 */
3689 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
3690 .master = &dra7xx_l4_per1_hwmod,
3691 .slave = &dra7xx_uart1_hwmod,
3692 .clk = "l3_iclk_div",
3693 .user = OCP_USER_MPU | OCP_USER_SDMA,
3696 /* l4_per1 -> uart2 */
3697 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
3698 .master = &dra7xx_l4_per1_hwmod,
3699 .slave = &dra7xx_uart2_hwmod,
3700 .clk = "l3_iclk_div",
3701 .user = OCP_USER_MPU | OCP_USER_SDMA,
3704 /* l4_per1 -> uart3 */
3705 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
3706 .master = &dra7xx_l4_per1_hwmod,
3707 .slave = &dra7xx_uart3_hwmod,
3708 .clk = "l3_iclk_div",
3709 .user = OCP_USER_MPU | OCP_USER_SDMA,
3712 /* l4_per1 -> uart4 */
3713 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
3714 .master = &dra7xx_l4_per1_hwmod,
3715 .slave = &dra7xx_uart4_hwmod,
3716 .clk = "l3_iclk_div",
3717 .user = OCP_USER_MPU | OCP_USER_SDMA,
3720 /* l4_per1 -> uart5 */
3721 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
3722 .master = &dra7xx_l4_per1_hwmod,
3723 .slave = &dra7xx_uart5_hwmod,
3724 .clk = "l3_iclk_div",
3725 .user = OCP_USER_MPU | OCP_USER_SDMA,
3728 /* l4_per1 -> uart6 */
3729 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
3730 .master = &dra7xx_l4_per1_hwmod,
3731 .slave = &dra7xx_uart6_hwmod,
3732 .clk = "l3_iclk_div",
3733 .user = OCP_USER_MPU | OCP_USER_SDMA,
3736 /* l4_per2 -> uart7 */
3737 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart7 = {
3738 .master = &dra7xx_l4_per2_hwmod,
3739 .slave = &dra7xx_uart7_hwmod,
3740 .clk = "l3_iclk_div",
3741 .user = OCP_USER_MPU | OCP_USER_SDMA,
3744 /* l4_per1 -> des */
3745 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
3746 .master = &dra7xx_l4_per1_hwmod,
3747 .slave = &dra7xx_des_hwmod,
3748 .clk = "l3_iclk_div",
3749 .user = OCP_USER_MPU | OCP_USER_SDMA,
3752 /* l4_per2 -> uart8 */
3753 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart8 = {
3754 .master = &dra7xx_l4_per2_hwmod,
3755 .slave = &dra7xx_uart8_hwmod,
3756 .clk = "l3_iclk_div",
3757 .user = OCP_USER_MPU | OCP_USER_SDMA,
3760 /* l4_per2 -> uart9 */
3761 static struct omap_hwmod_ocp_if dra7xx_l4_per2__uart9 = {
3762 .master = &dra7xx_l4_per2_hwmod,
3763 .slave = &dra7xx_uart9_hwmod,
3764 .clk = "l3_iclk_div",
3765 .user = OCP_USER_MPU | OCP_USER_SDMA,
3768 /* l4_wkup -> uart10 */
3769 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__uart10 = {
3770 .master = &dra7xx_l4_wkup_hwmod,
3771 .slave = &dra7xx_uart10_hwmod,
3772 .clk = "wkupaon_iclk_mux",
3773 .user = OCP_USER_MPU | OCP_USER_SDMA,
3776 /* l4_per1 -> rng */
3777 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
3778 .master = &dra7xx_l4_per1_hwmod,
3779 .slave = &dra7xx_rng_hwmod,
3780 .user = OCP_USER_MPU,
3783 /* l4_per3 -> usb_otg_ss1 */
3784 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
3785 .master = &dra7xx_l4_per3_hwmod,
3786 .slave = &dra7xx_usb_otg_ss1_hwmod,
3787 .clk = "dpll_core_h13x2_ck",
3788 .user = OCP_USER_MPU | OCP_USER_SDMA,
3791 /* l4_per3 -> usb_otg_ss2 */
3792 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
3793 .master = &dra7xx_l4_per3_hwmod,
3794 .slave = &dra7xx_usb_otg_ss2_hwmod,
3795 .clk = "dpll_core_h13x2_ck",
3796 .user = OCP_USER_MPU | OCP_USER_SDMA,
3799 /* l4_per3 -> usb_otg_ss3 */
3800 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
3801 .master = &dra7xx_l4_per3_hwmod,
3802 .slave = &dra7xx_usb_otg_ss3_hwmod,
3803 .clk = "dpll_core_h13x2_ck",
3804 .user = OCP_USER_MPU | OCP_USER_SDMA,
3807 /* l4_per3 -> usb_otg_ss4 */
3808 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
3809 .master = &dra7xx_l4_per3_hwmod,
3810 .slave = &dra7xx_usb_otg_ss4_hwmod,
3811 .clk = "dpll_core_h13x2_ck",
3812 .user = OCP_USER_MPU | OCP_USER_SDMA,
3815 /* l3_main_1 -> vcp1 */
3816 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
3817 .master = &dra7xx_l3_main_1_hwmod,
3818 .slave = &dra7xx_vcp1_hwmod,
3819 .clk = "l3_iclk_div",
3820 .user = OCP_USER_MPU | OCP_USER_SDMA,
3823 /* l4_per2 -> vcp1 */
3824 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
3825 .master = &dra7xx_l4_per2_hwmod,
3826 .slave = &dra7xx_vcp1_hwmod,
3827 .clk = "l3_iclk_div",
3828 .user = OCP_USER_MPU | OCP_USER_SDMA,
3831 /* l3_main_1 -> vcp2 */
3832 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
3833 .master = &dra7xx_l3_main_1_hwmod,
3834 .slave = &dra7xx_vcp2_hwmod,
3835 .clk = "l3_iclk_div",
3836 .user = OCP_USER_MPU | OCP_USER_SDMA,
3839 /* l4_per2 -> vcp2 */
3840 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
3841 .master = &dra7xx_l4_per2_hwmod,
3842 .slave = &dra7xx_vcp2_hwmod,
3843 .clk = "l3_iclk_div",
3844 .user = OCP_USER_MPU | OCP_USER_SDMA,
3847 /* l4_wkup -> wd_timer2 */
3848 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
3849 .master = &dra7xx_l4_wkup_hwmod,
3850 .slave = &dra7xx_wd_timer2_hwmod,
3851 .clk = "wkupaon_iclk_mux",
3852 .user = OCP_USER_MPU | OCP_USER_SDMA,
3855 /* l4_per2 -> epwmss0 */
3856 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
3857 .master = &dra7xx_l4_per2_hwmod,
3858 .slave = &dra7xx_epwmss0_hwmod,
3859 .clk = "l4_root_clk_div",
3860 .user = OCP_USER_MPU,
3863 /* l4_per2 -> epwmss1 */
3864 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
3865 .master = &dra7xx_l4_per2_hwmod,
3866 .slave = &dra7xx_epwmss1_hwmod,
3867 .clk = "l4_root_clk_div",
3868 .user = OCP_USER_MPU,
3871 /* l4_per2 -> epwmss2 */
3872 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3873 .master = &dra7xx_l4_per2_hwmod,
3874 .slave = &dra7xx_epwmss2_hwmod,
3875 .clk = "l4_root_clk_div",
3876 .user = OCP_USER_MPU,
3879 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3880 &dra7xx_l3_main_1__dmm,
3881 &dra7xx_l3_main_2__l3_instr,
3882 &dra7xx_l4_cfg__l3_main_1,
3883 &dra7xx_mpu__l3_main_1,
3884 &dra7xx_l3_main_1__l3_main_2,
3885 &dra7xx_l4_cfg__l3_main_2,
3886 &dra7xx_l3_main_1__l4_cfg,
3887 &dra7xx_l3_main_1__l4_per1,
3888 &dra7xx_l3_main_1__l4_per2,
3889 &dra7xx_l3_main_1__l4_per3,
3890 &dra7xx_l3_main_1__l4_wkup,
3891 &dra7xx_l4_per2__atl,
3892 &dra7xx_l3_main_1__bb2d,
3893 &dra7xx_l4_wkup__counter_32k,
3894 &dra7xx_l4_wkup__ctrl_module_wkup,
3895 &dra7xx_l4_wkup__dcan1,
3896 &dra7xx_l4_per2__dcan2,
3897 &dra7xx_l4_per2__cpgmac0,
3898 &dra7xx_l4_per2__mcasp1,
3899 &dra7xx_l3_main_1__mcasp1,
3900 &dra7xx_l4_per2__mcasp2,
3901 &dra7xx_l3_main_1__mcasp2,
3902 &dra7xx_l4_per2__mcasp3,
3903 &dra7xx_l3_main_1__mcasp3,
3904 &dra7xx_l4_per2__mcasp4,
3905 &dra7xx_l4_per2__mcasp5,
3906 &dra7xx_l4_per2__mcasp6,
3907 &dra7xx_l4_per2__mcasp7,
3908 &dra7xx_l4_per2__mcasp8,
3910 &dra7xx_l4_cfg__dma_system,
3911 &dra7xx_l3_main_1__tpcc,
3912 &dra7xx_l3_main_1__tptc0,
3913 &dra7xx_l3_main_1__tptc1,
3914 &dra7xx_l3_main_1__dss,
3915 &dra7xx_l3_main_1__dispc,
3916 &dra7xx_l3_main_1__hdmi,
3917 &dra7xx_l3_main_1__aes1,
3918 &dra7xx_l3_main_1__aes2,
3919 &dra7xx_l3_main_1__sha0,
3920 &dra7xx_l4_per1__elm,
3921 &dra7xx_l4_wkup__gpio1,
3922 &dra7xx_l4_per1__gpio2,
3923 &dra7xx_l4_per1__gpio3,
3924 &dra7xx_l4_per1__gpio4,
3925 &dra7xx_l4_per1__gpio5,
3926 &dra7xx_l4_per1__gpio6,
3927 &dra7xx_l4_per1__gpio7,
3928 &dra7xx_l4_per1__gpio8,
3929 &dra7xx_l3_main_1__gpmc,
3930 &dra7xx_l4_per1__hdq1w,
3931 &dra7xx_l4_per1__i2c1,
3932 &dra7xx_l4_per1__i2c2,
3933 &dra7xx_l4_per1__i2c3,
3934 &dra7xx_l4_per1__i2c4,
3935 &dra7xx_l4_per1__i2c5,
3936 &dra7xx_l4_cfg__mailbox1,
3937 &dra7xx_l4_per3__mailbox2,
3938 &dra7xx_l4_per3__mailbox3,
3939 &dra7xx_l4_per3__mailbox4,
3940 &dra7xx_l4_per3__mailbox5,
3941 &dra7xx_l4_per3__mailbox6,
3942 &dra7xx_l4_per3__mailbox7,
3943 &dra7xx_l4_per3__mailbox8,
3944 &dra7xx_l4_per3__mailbox9,
3945 &dra7xx_l4_per3__mailbox10,
3946 &dra7xx_l4_per3__mailbox11,
3947 &dra7xx_l4_per3__mailbox12,
3948 &dra7xx_l4_per3__mailbox13,
3949 &dra7xx_l4_per1__mcspi1,
3950 &dra7xx_l4_per1__mcspi2,
3951 &dra7xx_l4_per1__mcspi3,
3952 &dra7xx_l4_per1__mcspi4,
3953 &dra7xx_l4_per1__mmc1,
3954 &dra7xx_l4_per1__mmc2,
3955 &dra7xx_l4_per1__mmc3,
3956 &dra7xx_l4_per1__mmc4,
3957 &dra7xx_l4_cfg__mpu,
3958 &dra7xx_l4_cfg__ocp2scp1,
3959 &dra7xx_l4_cfg__ocp2scp3,
3960 &dra7xx_l3_main_1__pciess1,
3961 &dra7xx_l4_cfg__pciess1,
3962 &dra7xx_l3_main_1__pciess2,
3963 &dra7xx_l4_cfg__pciess2,
3964 &dra7xx_l3_main_1__qspi,
3965 &dra7xx_l4_cfg__sata,
3966 &dra7xx_l4_cfg__smartreflex_core,
3967 &dra7xx_l4_cfg__smartreflex_mpu,
3968 &dra7xx_l4_cfg__spinlock,
3969 &dra7xx_l4_wkup__timer1,
3970 &dra7xx_l4_per1__timer2,
3971 &dra7xx_l4_per1__timer3,
3972 &dra7xx_l4_per1__timer4,
3973 &dra7xx_l4_per3__timer5,
3974 &dra7xx_l4_per3__timer6,
3975 &dra7xx_l4_per3__timer7,
3976 &dra7xx_l4_per3__timer8,
3977 &dra7xx_l4_per1__timer9,
3978 &dra7xx_l4_per1__timer10,
3979 &dra7xx_l4_per1__timer11,
3980 &dra7xx_l4_per3__timer13,
3981 &dra7xx_l4_per3__timer14,
3982 &dra7xx_l4_per3__timer15,
3983 &dra7xx_l4_per3__timer16,
3984 &dra7xx_l4_per1__uart1,
3985 &dra7xx_l4_per1__uart2,
3986 &dra7xx_l4_per1__uart3,
3987 &dra7xx_l4_per1__uart4,
3988 &dra7xx_l4_per1__uart5,
3989 &dra7xx_l4_per1__uart6,
3990 &dra7xx_l4_per2__uart7,
3991 &dra7xx_l4_per2__uart8,
3992 &dra7xx_l4_per2__uart9,
3993 &dra7xx_l4_wkup__uart10,
3994 &dra7xx_l4_per1__des,
3995 &dra7xx_l4_per3__usb_otg_ss1,
3996 &dra7xx_l4_per3__usb_otg_ss2,
3997 &dra7xx_l4_per3__usb_otg_ss3,
3998 &dra7xx_l3_main_1__vcp1,
3999 &dra7xx_l4_per2__vcp1,
4000 &dra7xx_l3_main_1__vcp2,
4001 &dra7xx_l4_per2__vcp2,
4002 &dra7xx_l4_wkup__wd_timer2,
4003 &dra7xx_l4_per2__epwmss0,
4004 &dra7xx_l4_per2__epwmss1,
4005 &dra7xx_l4_per2__epwmss2,
4009 /* GP-only hwmod links */
4010 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
4011 &dra7xx_l4_wkup__timer12,
4012 &dra7xx_l4_per1__rng,
4016 /* SoC variant specific hwmod links */
4017 static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
4018 &dra7xx_l4_per3__usb_otg_ss4,
4022 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
4023 &dra7xx_l4_per3__usb_otg_ss4,
4027 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
4031 static struct omap_hwmod_ocp_if *dra74x_dra72x_hwmod_ocp_ifs[] __initdata = {
4032 &dra7xx_l4_per3__rtcss,
4036 int __init dra7xx_hwmod_init(void)
4041 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
4043 if (!ret && soc_is_dra74x())
4044 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
4045 else if (!ret && soc_is_dra72x())
4046 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
4047 else if (!ret && soc_is_dra76x())
4048 ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
4050 if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
4051 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);
4053 /* now for the IPs available only in dra74 and dra72 */
4054 if (!ret && !of_machine_is_compatible("ti,dra718") && !soc_is_dra76x())
4055 ret = omap_hwmod_register_links(dra74x_dra72x_hwmod_ocp_ifs);