arch/arm/mach-omap2/omap_hwmod_7xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the DRA7xx chips
   4  *
   5  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  */
  16
  17 #include <linux/io.h>
  18
  19 #include "omap_hwmod.h"
  20 #include "omap_hwmod_common_data.h"
  21 #include "cm1_7xx.h"
  22 #include "cm2_7xx.h"
  23 #include "prm7xx.h"
  24 #include "soc.h"
  25
  26 /* Base offset for all DRA7XX interrupts external to MPUSS */
  27 #define DRA7XX_IRQ_GIC_START    32
  28
  29 /*
  30  * IP blocks
  31  */
  32
  33 /*
  34  * 'dmm' class
  35  * instance(s): dmm
  36  */
  37 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
  38         .name   = "dmm",
  39 };
  40
  41 /* dmm */
  42 static struct omap_hwmod dra7xx_dmm_hwmod = {
  43         .name           = "dmm",
  44         .class          = &dra7xx_dmm_hwmod_class,
  45         .clkdm_name     = "emif_clkdm",
  46         .prcm = {
  47                 .omap4 = {
  48                         .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
  49                         .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
  50                 },
  51         },
  52 };
  53
  54 /*
  55  * 'l3' class
  56  * instance(s): l3_instr, l3_main_1, l3_main_2
  57  */
  58 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
  59         .name   = "l3",
  60 };
  61
  62 /* l3_instr */
  63 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
  64         .name           = "l3_instr",
  65         .class          = &dra7xx_l3_hwmod_class,
  66         .clkdm_name     = "l3instr_clkdm",
  67         .prcm = {
  68                 .omap4 = {
  69                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  70                         .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  71                         .modulemode   = MODULEMODE_HWCTRL,
  72                 },
  73         },
  74 };
  75
  76 /* l3_main_1 */
  77 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
  78         .name           = "l3_main_1",
  79         .class          = &dra7xx_l3_hwmod_class,
  80         .clkdm_name     = "l3main1_clkdm",
  81         .prcm = {
  82                 .omap4 = {
  83                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  84                         .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  85                 },
  86         },
  87 };
  88
  89 /* l3_main_2 */
  90 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
  91         .name           = "l3_main_2",
  92         .class          = &dra7xx_l3_hwmod_class,
  93         .clkdm_name     = "l3instr_clkdm",
  94         .prcm = {
  95                 .omap4 = {
  96                         .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
  97                         .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
  98                         .modulemode   = MODULEMODE_HWCTRL,
  99                 },
 100         },
 101 };
 102
 103 /*
 104  * 'l4' class
 105  * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
 106  */
 107 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
 108         .name   = "l4",
 109 };
 110
 111 /* l4_cfg */
 112 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
 113         .name           = "l4_cfg",
 114         .class          = &dra7xx_l4_hwmod_class,
 115         .clkdm_name     = "l4cfg_clkdm",
 116         .prcm = {
 117                 .omap4 = {
 118                         .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 119                         .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 120                 },
 121         },
 122 };
 123
 124 /* l4_per1 */
 125 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
 126         .name           = "l4_per1",
 127         .class          = &dra7xx_l4_hwmod_class,
 128         .clkdm_name     = "l4per_clkdm",
 129         .prcm = {
 130                 .omap4 = {
 131                         .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
 132                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 133                 },
 134         },
 135 };
 136
 137 /* l4_per2 */
 138 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
 139         .name           = "l4_per2",
 140         .class          = &dra7xx_l4_hwmod_class,
 141         .clkdm_name     = "l4per2_clkdm",
 142         .prcm = {
 143                 .omap4 = {
 144                         .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
 145                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 146                 },
 147         },
 148 };
 149
 150 /* l4_per3 */
 151 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
 152         .name           = "l4_per3",
 153         .class          = &dra7xx_l4_hwmod_class,
 154         .clkdm_name     = "l4per3_clkdm",
 155         .prcm = {
 156                 .omap4 = {
 157                         .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
 158                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 159                 },
 160         },
 161 };
 162
 163 /* l4_wkup */
 164 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
 165         .name           = "l4_wkup",
 166         .class          = &dra7xx_l4_hwmod_class,
 167         .clkdm_name     = "wkupaon_clkdm",
 168         .prcm = {
 169                 .omap4 = {
 170                         .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 171                         .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 172                 },
 173         },
 174 };
 175
 176 /*
 177  * 'atl' class
 178  *
 179  */
 180
 181 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
 182         .name   = "atl",
 183 };
 184
 185 /* atl */
 186 static struct omap_hwmod dra7xx_atl_hwmod = {
 187         .name           = "atl",
 188         .class          = &dra7xx_atl_hwmod_class,
 189         .clkdm_name     = "atl_clkdm",
 190         .main_clk       = "atl_gfclk_mux",
 191         .prcm = {
 192                 .omap4 = {
 193                         .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
 194                         .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
 195                         .modulemode   = MODULEMODE_SWCTRL,
 196                 },
 197         },
 198 };
 199
 200 /*
 201  * 'bb2d' class
 202  *
 203  */
 204
 205 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
 206         .name   = "bb2d",
 207 };
 208
 209 /* bb2d */
 210 static struct omap_hwmod dra7xx_bb2d_hwmod = {
 211         .name           = "bb2d",
 212         .class          = &dra7xx_bb2d_hwmod_class,
 213         .clkdm_name     = "dss_clkdm",
 214         .main_clk       = "dpll_core_h24x2_ck",
 215         .prcm = {
 216                 .omap4 = {
 217                         .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
 218                         .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
 219                         .modulemode   = MODULEMODE_SWCTRL,
 220                 },
 221         },
 222 };
 223
 224 /*
 225  * 'ctrl_module' class
 226  *
 227  */
 228
 229 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
 230         .name   = "ctrl_module",
 231 };
 232
 233 /* ctrl_module_wkup */
 234 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
 235         .name           = "ctrl_module_wkup",
 236         .class          = &dra7xx_ctrl_module_hwmod_class,
 237         .clkdm_name     = "wkupaon_clkdm",
 238         .prcm = {
 239                 .omap4 = {
 240                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 241                 },
 242         },
 243 };
 244
 245 /*
 246  * 'mpu' class
 247  *
 248  */
 249
 250 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
 251         .name   = "mpu",
 252 };
 253
 254 /* mpu */
 255 static struct omap_hwmod dra7xx_mpu_hwmod = {
 256         .name           = "mpu",
 257         .class          = &dra7xx_mpu_hwmod_class,
 258         .clkdm_name     = "mpu_clkdm",
 259         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
 260         .main_clk       = "dpll_mpu_m2_ck",
 261         .prcm = {
 262                 .omap4 = {
 263                         .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
 264                         .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
 265                 },
 266         },
 267 };
 268
 269 /*
 270  * 'vcp' class
 271  *
 272  */
 273
 274 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
 275         .name   = "vcp",
 276 };
 277
 278 /* vcp1 */
 279 static struct omap_hwmod dra7xx_vcp1_hwmod = {
 280         .name           = "vcp1",
 281         .class          = &dra7xx_vcp_hwmod_class,
 282         .clkdm_name     = "l3main1_clkdm",
 283         .main_clk       = "l3_iclk_div",
 284         .prcm = {
 285                 .omap4 = {
 286                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
 287                         .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
 288                 },
 289         },
 290 };
 291
 292 /* vcp2 */
 293 static struct omap_hwmod dra7xx_vcp2_hwmod = {
 294         .name           = "vcp2",
 295         .class          = &dra7xx_vcp_hwmod_class,
 296         .clkdm_name     = "l3main1_clkdm",
 297         .main_clk       = "l3_iclk_div",
 298         .prcm = {
 299                 .omap4 = {
 300                         .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
 301                         .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
 302                 },
 303         },
 304 };
 305
 306
 307
 308 /*
 309  * Interfaces
 310  */
 311
 312 /* l3_main_1 -> dmm */
 313 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
 314         .master         = &dra7xx_l3_main_1_hwmod,
 315         .slave          = &dra7xx_dmm_hwmod,
 316         .clk            = "l3_iclk_div",
 317         .user           = OCP_USER_SDMA,
 318 };
 319
 320 /* l3_main_2 -> l3_instr */
 321 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
 322         .master         = &dra7xx_l3_main_2_hwmod,
 323         .slave          = &dra7xx_l3_instr_hwmod,
 324         .clk            = "l3_iclk_div",
 325         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 326 };
 327
 328 /* l4_cfg -> l3_main_1 */
 329 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
 330         .master         = &dra7xx_l4_cfg_hwmod,
 331         .slave          = &dra7xx_l3_main_1_hwmod,
 332         .clk            = "l3_iclk_div",
 333         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 334 };
 335
 336 /* mpu -> l3_main_1 */
 337 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
 338         .master         = &dra7xx_mpu_hwmod,
 339         .slave          = &dra7xx_l3_main_1_hwmod,
 340         .clk            = "l3_iclk_div",
 341         .user           = OCP_USER_MPU,
 342 };
 343
 344 /* l3_main_1 -> l3_main_2 */
 345 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
 346         .master         = &dra7xx_l3_main_1_hwmod,
 347         .slave          = &dra7xx_l3_main_2_hwmod,
 348         .clk            = "l3_iclk_div",
 349         .user           = OCP_USER_MPU,
 350 };
 351
 352 /* l4_cfg -> l3_main_2 */
 353 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
 354         .master         = &dra7xx_l4_cfg_hwmod,
 355         .slave          = &dra7xx_l3_main_2_hwmod,
 356         .clk            = "l3_iclk_div",
 357         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 358 };
 359
 360 /* l3_main_1 -> l4_cfg */
 361 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
 362         .master         = &dra7xx_l3_main_1_hwmod,
 363         .slave          = &dra7xx_l4_cfg_hwmod,
 364         .clk            = "l3_iclk_div",
 365         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 366 };
 367
 368 /* l3_main_1 -> l4_per1 */
 369 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
 370         .master         = &dra7xx_l3_main_1_hwmod,
 371         .slave          = &dra7xx_l4_per1_hwmod,
 372         .clk            = "l3_iclk_div",
 373         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 374 };
 375
 376 /* l3_main_1 -> l4_per2 */
 377 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
 378         .master         = &dra7xx_l3_main_1_hwmod,
 379         .slave          = &dra7xx_l4_per2_hwmod,
 380         .clk            = "l3_iclk_div",
 381         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 382 };
 383
 384 /* l3_main_1 -> l4_per3 */
 385 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
 386         .master         = &dra7xx_l3_main_1_hwmod,
 387         .slave          = &dra7xx_l4_per3_hwmod,
 388         .clk            = "l3_iclk_div",
 389         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 390 };
 391
 392 /* l3_main_1 -> l4_wkup */
 393 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
 394         .master         = &dra7xx_l3_main_1_hwmod,
 395         .slave          = &dra7xx_l4_wkup_hwmod,
 396         .clk            = "wkupaon_iclk_mux",
 397         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 398 };
 399
 400 /* l4_per2 -> atl */
 401 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
 402         .master         = &dra7xx_l4_per2_hwmod,
 403         .slave          = &dra7xx_atl_hwmod,
 404         .clk            = "l3_iclk_div",
 405         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 406 };
 407
 408 /* l3_main_1 -> bb2d */
 409 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
 410         .master         = &dra7xx_l3_main_1_hwmod,
 411         .slave          = &dra7xx_bb2d_hwmod,
 412         .clk            = "l3_iclk_div",
 413         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 414 };
 415
 416 /* l4_wkup -> ctrl_module_wkup */
 417 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
 418         .master         = &dra7xx_l4_wkup_hwmod,
 419         .slave          = &dra7xx_ctrl_module_wkup_hwmod,
 420         .clk            = "wkupaon_iclk_mux",
 421         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 422 };
 423
 424 /* l4_cfg -> mpu */
 425 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
 426         .master         = &dra7xx_l4_cfg_hwmod,
 427         .slave          = &dra7xx_mpu_hwmod,
 428         .clk            = "l3_iclk_div",
 429         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 430 };
 431
 432 /* l3_main_1 -> vcp1 */
 433 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
 434         .master         = &dra7xx_l3_main_1_hwmod,
 435         .slave          = &dra7xx_vcp1_hwmod,
 436         .clk            = "l3_iclk_div",
 437         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 438 };
 439
 440 /* l4_per2 -> vcp1 */
 441 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
 442         .master         = &dra7xx_l4_per2_hwmod,
 443         .slave          = &dra7xx_vcp1_hwmod,
 444         .clk            = "l3_iclk_div",
 445         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 446 };
 447
 448 /* l3_main_1 -> vcp2 */
 449 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
 450         .master         = &dra7xx_l3_main_1_hwmod,
 451         .slave          = &dra7xx_vcp2_hwmod,
 452         .clk            = "l3_iclk_div",
 453         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 454 };
 455
 456 /* l4_per2 -> vcp2 */
 457 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
 458         .master         = &dra7xx_l4_per2_hwmod,
 459         .slave          = &dra7xx_vcp2_hwmod,
 460         .clk            = "l3_iclk_div",
 461         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 462 };
 463
 464 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
 465         &dra7xx_l3_main_1__dmm,
 466         &dra7xx_l3_main_2__l3_instr,
 467         &dra7xx_l4_cfg__l3_main_1,
 468         &dra7xx_mpu__l3_main_1,
 469         &dra7xx_l3_main_1__l3_main_2,
 470         &dra7xx_l4_cfg__l3_main_2,
 471         &dra7xx_l3_main_1__l4_cfg,
 472         &dra7xx_l3_main_1__l4_per1,
 473         &dra7xx_l3_main_1__l4_per2,
 474         &dra7xx_l3_main_1__l4_per3,
 475         &dra7xx_l3_main_1__l4_wkup,
 476         &dra7xx_l4_per2__atl,
 477         &dra7xx_l3_main_1__bb2d,
 478         &dra7xx_l4_wkup__ctrl_module_wkup,
 479         &dra7xx_l4_cfg__mpu,
 480         &dra7xx_l3_main_1__vcp1,
 481         &dra7xx_l4_per2__vcp1,
 482         &dra7xx_l3_main_1__vcp2,
 483         &dra7xx_l4_per2__vcp2,
 484         NULL,
 485 };
 486
 487 /* SoC variant specific hwmod links */
 488 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
 489         NULL,
 490 };
 491
 492 static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
 493         NULL,
 494 };
 495
 496 int __init dra7xx_hwmod_init(void)
 497 {
 498         int ret;
 499
 500         omap_hwmod_init();
 501         ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
 502
 503         if (!ret && soc_is_dra74x()) {
 504                 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
 505         } else if (!ret && soc_is_dra72x()) {
 506                 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
 507                 if (!ret && !of_machine_is_compatible("ti,dra718"))
 508                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
 509         } else if (!ret && soc_is_dra76x()) {
 510                 if (!ret && soc_is_dra76x_abz())
 511                         ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
 512         }
 513
 514         return ret;
 515 }