1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hardware modules present on the DRA7xx chips
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
19 #include "omap_hwmod.h"
20 #include "omap_hwmod_common_data.h"
26 /* Base offset for all DRA7XX interrupts external to MPUSS */
27 #define DRA7XX_IRQ_GIC_START 32
37 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
42 static struct omap_hwmod dra7xx_dmm_hwmod = {
44 .class = &dra7xx_dmm_hwmod_class,
45 .clkdm_name = "emif_clkdm",
48 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
49 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
56 * instance(s): l3_instr, l3_main_1, l3_main_2
58 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
63 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
65 .class = &dra7xx_l3_hwmod_class,
66 .clkdm_name = "l3instr_clkdm",
69 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
70 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
71 .modulemode = MODULEMODE_HWCTRL,
77 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
79 .class = &dra7xx_l3_hwmod_class,
80 .clkdm_name = "l3main1_clkdm",
83 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
84 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
90 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
92 .class = &dra7xx_l3_hwmod_class,
93 .clkdm_name = "l3instr_clkdm",
96 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
97 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
98 .modulemode = MODULEMODE_HWCTRL,
105 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
107 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
112 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
114 .class = &dra7xx_l4_hwmod_class,
115 .clkdm_name = "l4cfg_clkdm",
118 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
119 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
125 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
127 .class = &dra7xx_l4_hwmod_class,
128 .clkdm_name = "l4per_clkdm",
131 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
132 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
138 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
140 .class = &dra7xx_l4_hwmod_class,
141 .clkdm_name = "l4per2_clkdm",
144 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
145 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
153 .class = &dra7xx_l4_hwmod_class,
154 .clkdm_name = "l4per3_clkdm",
157 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
158 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
164 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
166 .class = &dra7xx_l4_hwmod_class,
167 .clkdm_name = "wkupaon_clkdm",
170 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
171 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
181 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
186 static struct omap_hwmod dra7xx_atl_hwmod = {
188 .class = &dra7xx_atl_hwmod_class,
189 .clkdm_name = "atl_clkdm",
190 .main_clk = "atl_gfclk_mux",
193 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
194 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
195 .modulemode = MODULEMODE_SWCTRL,
205 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
210 static struct omap_hwmod dra7xx_bb2d_hwmod = {
212 .class = &dra7xx_bb2d_hwmod_class,
213 .clkdm_name = "dss_clkdm",
214 .main_clk = "dpll_core_h24x2_ck",
217 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
218 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
219 .modulemode = MODULEMODE_SWCTRL,
225 * 'ctrl_module' class
229 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
230 .name = "ctrl_module",
233 /* ctrl_module_wkup */
234 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
235 .name = "ctrl_module_wkup",
236 .class = &dra7xx_ctrl_module_hwmod_class,
237 .clkdm_name = "wkupaon_clkdm",
240 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
250 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
254 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
255 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
256 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
257 .sysc_fields = &omap_hwmod_sysc_type1,
260 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
262 .sysc = &dra7xx_gpmc_sysc,
267 static struct omap_hwmod dra7xx_gpmc_hwmod = {
269 .class = &dra7xx_gpmc_hwmod_class,
270 .clkdm_name = "l3main1_clkdm",
271 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
272 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
273 .main_clk = "l3_iclk_div",
276 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
277 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
278 .modulemode = MODULEMODE_HWCTRL,
290 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
295 static struct omap_hwmod dra7xx_mpu_hwmod = {
297 .class = &dra7xx_mpu_hwmod_class,
298 .clkdm_name = "mpu_clkdm",
299 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
300 .main_clk = "dpll_mpu_m2_ck",
303 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
304 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
316 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
317 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
318 * associated with an IP automatically leaving the driver to handle that
319 * by itself. This does not work for PCIeSS which needs the reset lines
320 * deasserted for the driver to start accessing registers.
322 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
323 * lines after asserting them.
325 int dra7xx_pciess_reset(struct omap_hwmod *oh)
329 for (i = 0; i < oh->rst_lines_cnt; i++) {
330 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
331 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
337 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
339 .reset = dra7xx_pciess_reset,
343 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
344 { .name = "pcie", .rst_shift = 0 },
347 static struct omap_hwmod dra7xx_pciess1_hwmod = {
349 .class = &dra7xx_pciess_hwmod_class,
350 .clkdm_name = "pcie_clkdm",
351 .rst_lines = dra7xx_pciess1_resets,
352 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
353 .main_clk = "l4_root_clk_div",
356 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
357 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
358 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
359 .modulemode = MODULEMODE_SWCTRL,
365 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
366 { .name = "pcie", .rst_shift = 1 },
370 static struct omap_hwmod dra7xx_pciess2_hwmod = {
372 .class = &dra7xx_pciess_hwmod_class,
373 .clkdm_name = "pcie_clkdm",
374 .rst_lines = dra7xx_pciess2_resets,
375 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
376 .main_clk = "l4_root_clk_div",
379 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
380 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
381 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
382 .modulemode = MODULEMODE_SWCTRL,
392 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
395 .sysc_flags = SYSC_HAS_SIDLEMODE,
396 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
398 .sysc_fields = &omap_hwmod_sysc_type2,
401 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
403 .sysc = &dra7xx_qspi_sysc,
407 static struct omap_hwmod dra7xx_qspi_hwmod = {
409 .class = &dra7xx_qspi_hwmod_class,
410 .clkdm_name = "l4per2_clkdm",
411 .main_clk = "qspi_gfclk_div",
414 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
415 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
416 .modulemode = MODULEMODE_SWCTRL,
425 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
428 .sysc_flags = SYSC_HAS_SIDLEMODE,
429 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
431 .sysc_fields = &omap_hwmod_sysc_type3,
434 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
436 .sysc = &dra7xx_rtcss_sysc,
437 .unlock = &omap_hwmod_rtc_unlock,
438 .lock = &omap_hwmod_rtc_lock,
442 static struct omap_hwmod dra7xx_rtcss_hwmod = {
444 .class = &dra7xx_rtcss_hwmod_class,
445 .clkdm_name = "rtc_clkdm",
446 .main_clk = "sys_32k_ck",
449 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
450 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
451 .modulemode = MODULEMODE_SWCTRL,
461 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
464 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
465 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
466 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
467 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
468 .sysc_fields = &omap_hwmod_sysc_type2,
471 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
473 .sysc = &dra7xx_sata_sysc,
478 static struct omap_hwmod dra7xx_sata_hwmod = {
480 .class = &dra7xx_sata_hwmod_class,
481 .clkdm_name = "l3init_clkdm",
482 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
483 .main_clk = "func_48m_fclk",
487 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
488 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
489 .modulemode = MODULEMODE_SWCTRL,
499 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
504 static struct omap_hwmod dra7xx_vcp1_hwmod = {
506 .class = &dra7xx_vcp_hwmod_class,
507 .clkdm_name = "l3main1_clkdm",
508 .main_clk = "l3_iclk_div",
511 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
512 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
518 static struct omap_hwmod dra7xx_vcp2_hwmod = {
520 .class = &dra7xx_vcp_hwmod_class,
521 .clkdm_name = "l3main1_clkdm",
522 .main_clk = "l3_iclk_div",
525 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
526 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
537 /* l3_main_1 -> dmm */
538 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
539 .master = &dra7xx_l3_main_1_hwmod,
540 .slave = &dra7xx_dmm_hwmod,
541 .clk = "l3_iclk_div",
542 .user = OCP_USER_SDMA,
545 /* l3_main_2 -> l3_instr */
546 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
547 .master = &dra7xx_l3_main_2_hwmod,
548 .slave = &dra7xx_l3_instr_hwmod,
549 .clk = "l3_iclk_div",
550 .user = OCP_USER_MPU | OCP_USER_SDMA,
553 /* l4_cfg -> l3_main_1 */
554 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
555 .master = &dra7xx_l4_cfg_hwmod,
556 .slave = &dra7xx_l3_main_1_hwmod,
557 .clk = "l3_iclk_div",
558 .user = OCP_USER_MPU | OCP_USER_SDMA,
561 /* mpu -> l3_main_1 */
562 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
563 .master = &dra7xx_mpu_hwmod,
564 .slave = &dra7xx_l3_main_1_hwmod,
565 .clk = "l3_iclk_div",
566 .user = OCP_USER_MPU,
569 /* l3_main_1 -> l3_main_2 */
570 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
571 .master = &dra7xx_l3_main_1_hwmod,
572 .slave = &dra7xx_l3_main_2_hwmod,
573 .clk = "l3_iclk_div",
574 .user = OCP_USER_MPU,
577 /* l4_cfg -> l3_main_2 */
578 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
579 .master = &dra7xx_l4_cfg_hwmod,
580 .slave = &dra7xx_l3_main_2_hwmod,
581 .clk = "l3_iclk_div",
582 .user = OCP_USER_MPU | OCP_USER_SDMA,
585 /* l3_main_1 -> l4_cfg */
586 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
587 .master = &dra7xx_l3_main_1_hwmod,
588 .slave = &dra7xx_l4_cfg_hwmod,
589 .clk = "l3_iclk_div",
590 .user = OCP_USER_MPU | OCP_USER_SDMA,
593 /* l3_main_1 -> l4_per1 */
594 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
595 .master = &dra7xx_l3_main_1_hwmod,
596 .slave = &dra7xx_l4_per1_hwmod,
597 .clk = "l3_iclk_div",
598 .user = OCP_USER_MPU | OCP_USER_SDMA,
601 /* l3_main_1 -> l4_per2 */
602 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
603 .master = &dra7xx_l3_main_1_hwmod,
604 .slave = &dra7xx_l4_per2_hwmod,
605 .clk = "l3_iclk_div",
606 .user = OCP_USER_MPU | OCP_USER_SDMA,
609 /* l3_main_1 -> l4_per3 */
610 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
611 .master = &dra7xx_l3_main_1_hwmod,
612 .slave = &dra7xx_l4_per3_hwmod,
613 .clk = "l3_iclk_div",
614 .user = OCP_USER_MPU | OCP_USER_SDMA,
617 /* l3_main_1 -> l4_wkup */
618 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
619 .master = &dra7xx_l3_main_1_hwmod,
620 .slave = &dra7xx_l4_wkup_hwmod,
621 .clk = "wkupaon_iclk_mux",
622 .user = OCP_USER_MPU | OCP_USER_SDMA,
626 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
627 .master = &dra7xx_l4_per2_hwmod,
628 .slave = &dra7xx_atl_hwmod,
629 .clk = "l3_iclk_div",
630 .user = OCP_USER_MPU | OCP_USER_SDMA,
633 /* l3_main_1 -> bb2d */
634 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
635 .master = &dra7xx_l3_main_1_hwmod,
636 .slave = &dra7xx_bb2d_hwmod,
637 .clk = "l3_iclk_div",
638 .user = OCP_USER_MPU | OCP_USER_SDMA,
641 /* l4_wkup -> ctrl_module_wkup */
642 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
643 .master = &dra7xx_l4_wkup_hwmod,
644 .slave = &dra7xx_ctrl_module_wkup_hwmod,
645 .clk = "wkupaon_iclk_mux",
646 .user = OCP_USER_MPU | OCP_USER_SDMA,
649 /* l3_main_1 -> gpmc */
650 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
651 .master = &dra7xx_l3_main_1_hwmod,
652 .slave = &dra7xx_gpmc_hwmod,
653 .clk = "l3_iclk_div",
654 .user = OCP_USER_MPU | OCP_USER_SDMA,
658 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
659 .master = &dra7xx_l4_cfg_hwmod,
660 .slave = &dra7xx_mpu_hwmod,
661 .clk = "l3_iclk_div",
662 .user = OCP_USER_MPU | OCP_USER_SDMA,
665 /* l3_main_1 -> pciess1 */
666 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
667 .master = &dra7xx_l3_main_1_hwmod,
668 .slave = &dra7xx_pciess1_hwmod,
669 .clk = "l3_iclk_div",
670 .user = OCP_USER_MPU | OCP_USER_SDMA,
673 /* l4_cfg -> pciess1 */
674 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
675 .master = &dra7xx_l4_cfg_hwmod,
676 .slave = &dra7xx_pciess1_hwmod,
677 .clk = "l4_root_clk_div",
678 .user = OCP_USER_MPU | OCP_USER_SDMA,
681 /* l3_main_1 -> pciess2 */
682 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
683 .master = &dra7xx_l3_main_1_hwmod,
684 .slave = &dra7xx_pciess2_hwmod,
685 .clk = "l3_iclk_div",
686 .user = OCP_USER_MPU | OCP_USER_SDMA,
689 /* l4_cfg -> pciess2 */
690 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
691 .master = &dra7xx_l4_cfg_hwmod,
692 .slave = &dra7xx_pciess2_hwmod,
693 .clk = "l4_root_clk_div",
694 .user = OCP_USER_MPU | OCP_USER_SDMA,
697 /* l3_main_1 -> qspi */
698 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
699 .master = &dra7xx_l3_main_1_hwmod,
700 .slave = &dra7xx_qspi_hwmod,
701 .clk = "l3_iclk_div",
702 .user = OCP_USER_MPU | OCP_USER_SDMA,
705 /* l4_per3 -> rtcss */
706 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
707 .master = &dra7xx_l4_per3_hwmod,
708 .slave = &dra7xx_rtcss_hwmod,
709 .clk = "l4_root_clk_div",
710 .user = OCP_USER_MPU | OCP_USER_SDMA,
714 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
715 .master = &dra7xx_l4_cfg_hwmod,
716 .slave = &dra7xx_sata_hwmod,
717 .clk = "l3_iclk_div",
718 .user = OCP_USER_MPU | OCP_USER_SDMA,
721 /* l3_main_1 -> vcp1 */
722 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
723 .master = &dra7xx_l3_main_1_hwmod,
724 .slave = &dra7xx_vcp1_hwmod,
725 .clk = "l3_iclk_div",
726 .user = OCP_USER_MPU | OCP_USER_SDMA,
729 /* l4_per2 -> vcp1 */
730 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
731 .master = &dra7xx_l4_per2_hwmod,
732 .slave = &dra7xx_vcp1_hwmod,
733 .clk = "l3_iclk_div",
734 .user = OCP_USER_MPU | OCP_USER_SDMA,
737 /* l3_main_1 -> vcp2 */
738 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
739 .master = &dra7xx_l3_main_1_hwmod,
740 .slave = &dra7xx_vcp2_hwmod,
741 .clk = "l3_iclk_div",
742 .user = OCP_USER_MPU | OCP_USER_SDMA,
745 /* l4_per2 -> vcp2 */
746 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
747 .master = &dra7xx_l4_per2_hwmod,
748 .slave = &dra7xx_vcp2_hwmod,
749 .clk = "l3_iclk_div",
750 .user = OCP_USER_MPU | OCP_USER_SDMA,
753 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
754 &dra7xx_l3_main_1__dmm,
755 &dra7xx_l3_main_2__l3_instr,
756 &dra7xx_l4_cfg__l3_main_1,
757 &dra7xx_mpu__l3_main_1,
758 &dra7xx_l3_main_1__l3_main_2,
759 &dra7xx_l4_cfg__l3_main_2,
760 &dra7xx_l3_main_1__l4_cfg,
761 &dra7xx_l3_main_1__l4_per1,
762 &dra7xx_l3_main_1__l4_per2,
763 &dra7xx_l3_main_1__l4_per3,
764 &dra7xx_l3_main_1__l4_wkup,
765 &dra7xx_l4_per2__atl,
766 &dra7xx_l3_main_1__bb2d,
767 &dra7xx_l4_wkup__ctrl_module_wkup,
768 &dra7xx_l3_main_1__gpmc,
770 &dra7xx_l3_main_1__pciess1,
771 &dra7xx_l4_cfg__pciess1,
772 &dra7xx_l3_main_1__pciess2,
773 &dra7xx_l4_cfg__pciess2,
774 &dra7xx_l3_main_1__qspi,
775 &dra7xx_l4_cfg__sata,
776 &dra7xx_l3_main_1__vcp1,
777 &dra7xx_l4_per2__vcp1,
778 &dra7xx_l3_main_1__vcp2,
779 &dra7xx_l4_per2__vcp2,
783 /* SoC variant specific hwmod links */
784 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
788 static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
789 &dra7xx_l4_per3__rtcss,
793 int __init dra7xx_hwmod_init(void)
798 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
800 if (!ret && soc_is_dra74x()) {
801 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
802 } else if (!ret && soc_is_dra72x()) {
803 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
804 if (!ret && !of_machine_is_compatible("ti,dra718"))
805 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
806 } else if (!ret && soc_is_dra76x()) {
807 if (!ret && soc_is_dra76x_abz())
808 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);