2 * Hardware modules present on the DRA7xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/platform_data/gpio-omap.h>
22 #include <linux/power/smartreflex.h>
23 #include <linux/i2c-omap.h>
25 #include <linux/omap-dma.h>
26 #include <linux/platform_data/spi-omap2-mcspi.h>
27 #include <linux/platform_data/asoc-ti-mcbsp.h>
28 #include <plat/dmtimer.h>
30 #include "omap_hwmod.h"
31 #include "omap_hwmod_common_data.h"
39 /* Base offset for all DRA7XX interrupts external to MPUSS */
40 #define DRA7XX_IRQ_GIC_START 32
42 /* Base offset for all DRA7XX dma requests */
43 #define DRA7XX_DMA_REQ_START 1
52 * instance(s): l3_instr, l3_main_1, l3_main_2
54 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
59 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
61 .class = &dra7xx_l3_hwmod_class,
62 .clkdm_name = "l3instr_clkdm",
65 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
66 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
67 .modulemode = MODULEMODE_HWCTRL,
73 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
75 .class = &dra7xx_l3_hwmod_class,
76 .clkdm_name = "l3main1_clkdm",
79 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
80 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
86 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
88 .class = &dra7xx_l3_hwmod_class,
89 .clkdm_name = "l3instr_clkdm",
92 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
93 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
94 .modulemode = MODULEMODE_HWCTRL,
101 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
103 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
108 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
110 .class = &dra7xx_l4_hwmod_class,
111 .clkdm_name = "l4cfg_clkdm",
114 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
121 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
123 .class = &dra7xx_l4_hwmod_class,
124 .clkdm_name = "l4per_clkdm",
127 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
128 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
134 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
136 .class = &dra7xx_l4_hwmod_class,
137 .clkdm_name = "l4per2_clkdm",
140 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
141 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
147 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
149 .class = &dra7xx_l4_hwmod_class,
150 .clkdm_name = "l4per3_clkdm",
153 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
154 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
160 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
162 .class = &dra7xx_l4_hwmod_class,
163 .clkdm_name = "wkupaon_clkdm",
166 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
167 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
177 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
182 static struct omap_hwmod dra7xx_atl_hwmod = {
184 .class = &dra7xx_atl_hwmod_class,
185 .clkdm_name = "atl_clkdm",
186 .main_clk = "atl_gfclk_mux",
189 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
190 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
191 .modulemode = MODULEMODE_SWCTRL,
201 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
206 static struct omap_hwmod dra7xx_bb2d_hwmod = {
208 .class = &dra7xx_bb2d_hwmod_class,
209 .clkdm_name = "dss_clkdm",
210 .main_clk = "dpll_core_h24x2_ck",
213 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
214 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
215 .modulemode = MODULEMODE_SWCTRL,
225 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
228 .sysc_flags = SYSC_HAS_SIDLEMODE,
229 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
231 .sysc_fields = &omap_hwmod_sysc_type1,
234 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
236 .sysc = &dra7xx_counter_sysc,
240 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
241 .name = "counter_32k",
242 .class = &dra7xx_counter_hwmod_class,
243 .clkdm_name = "wkupaon_clkdm",
244 .flags = HWMOD_SWSUP_SIDLE,
245 .main_clk = "wkupaon_iclk_mux",
248 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
249 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
255 * 'ctrl_module' class
259 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
260 .name = "ctrl_module",
263 /* ctrl_module_wkup */
264 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
265 .name = "ctrl_module_wkup",
266 .class = &dra7xx_ctrl_module_hwmod_class,
267 .clkdm_name = "wkupaon_clkdm",
270 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
280 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
285 static struct omap_hwmod dra7xx_dcan1_hwmod = {
287 .class = &dra7xx_dcan_hwmod_class,
288 .clkdm_name = "wkupaon_clkdm",
289 .main_clk = "dcan1_sys_clk_mux",
292 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
293 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
294 .modulemode = MODULEMODE_SWCTRL,
300 static struct omap_hwmod dra7xx_dcan2_hwmod = {
302 .class = &dra7xx_dcan_hwmod_class,
303 .clkdm_name = "l4per2_clkdm",
304 .main_clk = "sys_clkin1",
307 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
308 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
309 .modulemode = MODULEMODE_SWCTRL,
319 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
323 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
324 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
325 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
326 SYSS_HAS_RESET_STATUS),
327 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
328 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
329 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
330 .sysc_fields = &omap_hwmod_sysc_type1,
333 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
335 .sysc = &dra7xx_dma_sysc,
339 static struct omap_dma_dev_attr dma_dev_attr = {
340 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
341 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
346 static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
347 { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
348 { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
349 { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
350 { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
354 static struct omap_hwmod dra7xx_dma_system_hwmod = {
355 .name = "dma_system",
356 .class = &dra7xx_dma_hwmod_class,
357 .clkdm_name = "dma_clkdm",
358 .mpu_irqs = dra7xx_dma_system_irqs,
359 .main_clk = "l3_iclk_div",
362 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
363 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
366 .dev_attr = &dma_dev_attr,
374 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
377 .sysc_flags = SYSS_HAS_RESET_STATUS,
380 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
382 .sysc = &dra7xx_dss_sysc,
383 .reset = omap_dss_reset,
387 static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
388 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
392 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
393 { .role = "dss_clk", .clk = "dss_dss_clk" },
394 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
395 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
396 { .role = "video2_clk", .clk = "dss_video2_clk" },
397 { .role = "video1_clk", .clk = "dss_video1_clk" },
398 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
401 static struct omap_hwmod dra7xx_dss_hwmod = {
403 .class = &dra7xx_dss_hwmod_class,
404 .clkdm_name = "dss_clkdm",
405 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
406 .sdma_reqs = dra7xx_dss_sdma_reqs,
407 .main_clk = "dss_dss_clk",
410 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
411 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
412 .modulemode = MODULEMODE_SWCTRL,
415 .opt_clks = dss_opt_clks,
416 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
424 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
428 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
429 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
430 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
431 SYSS_HAS_RESET_STATUS),
432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
433 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
434 .sysc_fields = &omap_hwmod_sysc_type1,
437 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
439 .sysc = &dra7xx_dispc_sysc,
443 /* dss_dispc dev_attr */
444 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
445 .has_framedonetv_irq = 1,
449 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
451 .class = &dra7xx_dispc_hwmod_class,
452 .clkdm_name = "dss_clkdm",
453 .main_clk = "dss_dss_clk",
456 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
457 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
460 .dev_attr = &dss_dispc_dev_attr,
468 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
471 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
473 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
475 .sysc_fields = &omap_hwmod_sysc_type2,
478 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
480 .sysc = &dra7xx_hdmi_sysc,
485 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
486 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
489 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
491 .class = &dra7xx_hdmi_hwmod_class,
492 .clkdm_name = "dss_clkdm",
493 .main_clk = "dss_48mhz_clk",
496 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
497 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
500 .opt_clks = dss_hdmi_opt_clks,
501 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
509 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
513 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
514 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
515 SYSS_HAS_RESET_STATUS),
516 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
518 .sysc_fields = &omap_hwmod_sysc_type1,
521 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
523 .sysc = &dra7xx_elm_sysc,
528 static struct omap_hwmod dra7xx_elm_hwmod = {
530 .class = &dra7xx_elm_hwmod_class,
531 .clkdm_name = "l4per_clkdm",
532 .main_clk = "l3_iclk_div",
535 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
536 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
546 static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
550 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
551 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
552 SYSS_HAS_RESET_STATUS),
553 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
555 .sysc_fields = &omap_hwmod_sysc_type1,
558 static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
560 .sysc = &dra7xx_gpio_sysc,
565 static struct omap_gpio_dev_attr gpio_dev_attr = {
571 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
572 { .role = "dbclk", .clk = "gpio1_dbclk" },
575 static struct omap_hwmod dra7xx_gpio1_hwmod = {
577 .class = &dra7xx_gpio_hwmod_class,
578 .clkdm_name = "wkupaon_clkdm",
579 .main_clk = "wkupaon_iclk_mux",
582 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
583 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
584 .modulemode = MODULEMODE_HWCTRL,
587 .opt_clks = gpio1_opt_clks,
588 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
589 .dev_attr = &gpio_dev_attr,
593 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
594 { .role = "dbclk", .clk = "gpio2_dbclk" },
597 static struct omap_hwmod dra7xx_gpio2_hwmod = {
599 .class = &dra7xx_gpio_hwmod_class,
600 .clkdm_name = "l4per_clkdm",
601 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
602 .main_clk = "l3_iclk_div",
605 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
606 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
607 .modulemode = MODULEMODE_HWCTRL,
610 .opt_clks = gpio2_opt_clks,
611 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
612 .dev_attr = &gpio_dev_attr,
616 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
617 { .role = "dbclk", .clk = "gpio3_dbclk" },
620 static struct omap_hwmod dra7xx_gpio3_hwmod = {
622 .class = &dra7xx_gpio_hwmod_class,
623 .clkdm_name = "l4per_clkdm",
624 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
625 .main_clk = "l3_iclk_div",
628 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
629 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
630 .modulemode = MODULEMODE_HWCTRL,
633 .opt_clks = gpio3_opt_clks,
634 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
635 .dev_attr = &gpio_dev_attr,
639 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
640 { .role = "dbclk", .clk = "gpio4_dbclk" },
643 static struct omap_hwmod dra7xx_gpio4_hwmod = {
645 .class = &dra7xx_gpio_hwmod_class,
646 .clkdm_name = "l4per_clkdm",
647 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
648 .main_clk = "l3_iclk_div",
651 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
652 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
653 .modulemode = MODULEMODE_HWCTRL,
656 .opt_clks = gpio4_opt_clks,
657 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
658 .dev_attr = &gpio_dev_attr,
662 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
663 { .role = "dbclk", .clk = "gpio5_dbclk" },
666 static struct omap_hwmod dra7xx_gpio5_hwmod = {
668 .class = &dra7xx_gpio_hwmod_class,
669 .clkdm_name = "l4per_clkdm",
670 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
671 .main_clk = "l3_iclk_div",
674 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
675 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
676 .modulemode = MODULEMODE_HWCTRL,
679 .opt_clks = gpio5_opt_clks,
680 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
681 .dev_attr = &gpio_dev_attr,
685 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
686 { .role = "dbclk", .clk = "gpio6_dbclk" },
689 static struct omap_hwmod dra7xx_gpio6_hwmod = {
691 .class = &dra7xx_gpio_hwmod_class,
692 .clkdm_name = "l4per_clkdm",
693 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
694 .main_clk = "l3_iclk_div",
697 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
698 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
699 .modulemode = MODULEMODE_HWCTRL,
702 .opt_clks = gpio6_opt_clks,
703 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
704 .dev_attr = &gpio_dev_attr,
708 static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
709 { .role = "dbclk", .clk = "gpio7_dbclk" },
712 static struct omap_hwmod dra7xx_gpio7_hwmod = {
714 .class = &dra7xx_gpio_hwmod_class,
715 .clkdm_name = "l4per_clkdm",
716 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
717 .main_clk = "l3_iclk_div",
720 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
721 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
722 .modulemode = MODULEMODE_HWCTRL,
725 .opt_clks = gpio7_opt_clks,
726 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
727 .dev_attr = &gpio_dev_attr,
731 static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
732 { .role = "dbclk", .clk = "gpio8_dbclk" },
735 static struct omap_hwmod dra7xx_gpio8_hwmod = {
737 .class = &dra7xx_gpio_hwmod_class,
738 .clkdm_name = "l4per_clkdm",
739 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
740 .main_clk = "l3_iclk_div",
743 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
744 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
745 .modulemode = MODULEMODE_HWCTRL,
748 .opt_clks = gpio8_opt_clks,
749 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
750 .dev_attr = &gpio_dev_attr,
758 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
762 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
763 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
764 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
766 .sysc_fields = &omap_hwmod_sysc_type1,
769 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
771 .sysc = &dra7xx_gpmc_sysc,
776 static struct omap_hwmod dra7xx_gpmc_hwmod = {
778 .class = &dra7xx_gpmc_hwmod_class,
779 .clkdm_name = "l3main1_clkdm",
780 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
781 .main_clk = "l3_iclk_div",
784 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
785 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
786 .modulemode = MODULEMODE_HWCTRL,
796 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
800 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
801 SYSS_HAS_RESET_STATUS),
802 .sysc_fields = &omap_hwmod_sysc_type1,
805 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
807 .sysc = &dra7xx_hdq1w_sysc,
812 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
814 .class = &dra7xx_hdq1w_hwmod_class,
815 .clkdm_name = "l4per_clkdm",
816 .flags = HWMOD_INIT_NO_RESET,
817 .main_clk = "func_12m_fclk",
820 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
821 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
822 .modulemode = MODULEMODE_SWCTRL,
832 static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
835 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
836 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
837 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
838 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
840 .clockact = CLOCKACT_TEST_ICLK,
841 .sysc_fields = &omap_hwmod_sysc_type1,
844 static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
846 .sysc = &dra7xx_i2c_sysc,
847 .reset = &omap_i2c_reset,
848 .rev = OMAP_I2C_IP_VERSION_2,
852 static struct omap_i2c_dev_attr i2c_dev_attr = {
853 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
857 static struct omap_hwmod dra7xx_i2c1_hwmod = {
859 .class = &dra7xx_i2c_hwmod_class,
860 .clkdm_name = "l4per_clkdm",
861 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
862 .main_clk = "func_96m_fclk",
865 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
866 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
867 .modulemode = MODULEMODE_SWCTRL,
870 .dev_attr = &i2c_dev_attr,
874 static struct omap_hwmod dra7xx_i2c2_hwmod = {
876 .class = &dra7xx_i2c_hwmod_class,
877 .clkdm_name = "l4per_clkdm",
878 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
879 .main_clk = "func_96m_fclk",
882 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
883 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
884 .modulemode = MODULEMODE_SWCTRL,
887 .dev_attr = &i2c_dev_attr,
891 static struct omap_hwmod dra7xx_i2c3_hwmod = {
893 .class = &dra7xx_i2c_hwmod_class,
894 .clkdm_name = "l4per_clkdm",
895 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
896 .main_clk = "func_96m_fclk",
899 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
900 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
901 .modulemode = MODULEMODE_SWCTRL,
904 .dev_attr = &i2c_dev_attr,
908 static struct omap_hwmod dra7xx_i2c4_hwmod = {
910 .class = &dra7xx_i2c_hwmod_class,
911 .clkdm_name = "l4per_clkdm",
912 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
913 .main_clk = "func_96m_fclk",
916 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
917 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
918 .modulemode = MODULEMODE_SWCTRL,
921 .dev_attr = &i2c_dev_attr,
925 static struct omap_hwmod dra7xx_i2c5_hwmod = {
927 .class = &dra7xx_i2c_hwmod_class,
928 .clkdm_name = "ipu_clkdm",
929 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
930 .main_clk = "func_96m_fclk",
933 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
934 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
935 .modulemode = MODULEMODE_SWCTRL,
938 .dev_attr = &i2c_dev_attr,
946 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
949 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
950 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
951 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
953 .sysc_fields = &omap_hwmod_sysc_type2,
956 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
958 .sysc = &dra7xx_mcspi_sysc,
959 .rev = OMAP4_MCSPI_REV,
963 /* mcspi1 dev_attr */
964 static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
968 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
970 .class = &dra7xx_mcspi_hwmod_class,
971 .clkdm_name = "l4per_clkdm",
972 .main_clk = "func_48m_fclk",
975 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
976 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
977 .modulemode = MODULEMODE_SWCTRL,
980 .dev_attr = &mcspi1_dev_attr,
984 /* mcspi2 dev_attr */
985 static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
989 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
991 .class = &dra7xx_mcspi_hwmod_class,
992 .clkdm_name = "l4per_clkdm",
993 .main_clk = "func_48m_fclk",
996 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
997 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
998 .modulemode = MODULEMODE_SWCTRL,
1001 .dev_attr = &mcspi2_dev_attr,
1005 /* mcspi3 dev_attr */
1006 static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1007 .num_chipselect = 2,
1010 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1012 .class = &dra7xx_mcspi_hwmod_class,
1013 .clkdm_name = "l4per_clkdm",
1014 .main_clk = "func_48m_fclk",
1017 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1018 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1019 .modulemode = MODULEMODE_SWCTRL,
1022 .dev_attr = &mcspi3_dev_attr,
1026 /* mcspi4 dev_attr */
1027 static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1028 .num_chipselect = 1,
1031 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1033 .class = &dra7xx_mcspi_hwmod_class,
1034 .clkdm_name = "l4per_clkdm",
1035 .main_clk = "func_48m_fclk",
1038 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1039 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1040 .modulemode = MODULEMODE_SWCTRL,
1043 .dev_attr = &mcspi4_dev_attr,
1051 static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1053 .sysc_offs = 0x0010,
1054 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1055 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1056 SYSC_HAS_SOFTRESET),
1057 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1058 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1059 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1060 .sysc_fields = &omap_hwmod_sysc_type2,
1063 static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1065 .sysc = &dra7xx_mmc_sysc,
1069 static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1070 { .role = "clk32k", .clk = "mmc1_clk32k" },
1074 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1075 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1078 static struct omap_hwmod dra7xx_mmc1_hwmod = {
1080 .class = &dra7xx_mmc_hwmod_class,
1081 .clkdm_name = "l3init_clkdm",
1082 .main_clk = "mmc1_fclk_div",
1085 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1086 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1090 .opt_clks = mmc1_opt_clks,
1091 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1092 .dev_attr = &mmc1_dev_attr,
1096 static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1097 { .role = "clk32k", .clk = "mmc2_clk32k" },
1100 static struct omap_hwmod dra7xx_mmc2_hwmod = {
1102 .class = &dra7xx_mmc_hwmod_class,
1103 .clkdm_name = "l3init_clkdm",
1104 .main_clk = "mmc2_fclk_div",
1107 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1108 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1109 .modulemode = MODULEMODE_SWCTRL,
1112 .opt_clks = mmc2_opt_clks,
1113 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1117 static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1118 { .role = "clk32k", .clk = "mmc3_clk32k" },
1121 static struct omap_hwmod dra7xx_mmc3_hwmod = {
1123 .class = &dra7xx_mmc_hwmod_class,
1124 .clkdm_name = "l4per_clkdm",
1125 .main_clk = "mmc3_gfclk_div",
1128 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1129 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1130 .modulemode = MODULEMODE_SWCTRL,
1133 .opt_clks = mmc3_opt_clks,
1134 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1138 static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1139 { .role = "clk32k", .clk = "mmc4_clk32k" },
1142 static struct omap_hwmod dra7xx_mmc4_hwmod = {
1144 .class = &dra7xx_mmc_hwmod_class,
1145 .clkdm_name = "l4per_clkdm",
1146 .main_clk = "mmc4_gfclk_div",
1149 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1150 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1151 .modulemode = MODULEMODE_SWCTRL,
1154 .opt_clks = mmc4_opt_clks,
1155 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1163 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1168 static struct omap_hwmod dra7xx_mpu_hwmod = {
1170 .class = &dra7xx_mpu_hwmod_class,
1171 .clkdm_name = "mpu_clkdm",
1172 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1173 .main_clk = "dpll_mpu_m2_ck",
1176 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1177 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1187 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1189 .sysc_offs = 0x0010,
1190 .syss_offs = 0x0014,
1191 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1192 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1193 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1195 .sysc_fields = &omap_hwmod_sysc_type1,
1198 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1200 .sysc = &dra7xx_ocp2scp_sysc,
1204 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1206 .class = &dra7xx_ocp2scp_hwmod_class,
1207 .clkdm_name = "l3init_clkdm",
1208 .main_clk = "l4_root_clk_div",
1211 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1212 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1213 .modulemode = MODULEMODE_HWCTRL,
1223 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1224 .sysc_offs = 0x0010,
1225 .sysc_flags = SYSC_HAS_SIDLEMODE,
1226 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1228 .sysc_fields = &omap_hwmod_sysc_type2,
1231 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1233 .sysc = &dra7xx_qspi_sysc,
1237 static struct omap_hwmod dra7xx_qspi_hwmod = {
1239 .class = &dra7xx_qspi_hwmod_class,
1240 .clkdm_name = "l4per2_clkdm",
1241 .main_clk = "qspi_gfclk_div",
1244 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1245 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1246 .modulemode = MODULEMODE_SWCTRL,
1256 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1257 .sysc_offs = 0x0000,
1258 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1259 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1260 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1261 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1262 .sysc_fields = &omap_hwmod_sysc_type2,
1265 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1267 .sysc = &dra7xx_sata_sysc,
1271 static struct omap_hwmod_opt_clk sata_opt_clks[] = {
1272 { .role = "ref_clk", .clk = "sata_ref_clk" },
1275 static struct omap_hwmod dra7xx_sata_hwmod = {
1277 .class = &dra7xx_sata_hwmod_class,
1278 .clkdm_name = "l3init_clkdm",
1279 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1280 .main_clk = "func_48m_fclk",
1283 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1284 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1285 .modulemode = MODULEMODE_SWCTRL,
1288 .opt_clks = sata_opt_clks,
1289 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
1293 * 'smartreflex' class
1297 /* The IP is not compliant to type1 / type2 scheme */
1298 static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1303 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1304 .sysc_offs = 0x0038,
1305 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1306 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1308 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1311 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1312 .name = "smartreflex",
1313 .sysc = &dra7xx_smartreflex_sysc,
1317 /* smartreflex_core */
1318 /* smartreflex_core dev_attr */
1319 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1320 .sensor_voltdm_name = "core",
1323 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1324 .name = "smartreflex_core",
1325 .class = &dra7xx_smartreflex_hwmod_class,
1326 .clkdm_name = "coreaon_clkdm",
1327 .main_clk = "wkupaon_iclk_mux",
1330 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1331 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1332 .modulemode = MODULEMODE_SWCTRL,
1335 .dev_attr = &smartreflex_core_dev_attr,
1338 /* smartreflex_mpu */
1339 /* smartreflex_mpu dev_attr */
1340 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1341 .sensor_voltdm_name = "mpu",
1344 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1345 .name = "smartreflex_mpu",
1346 .class = &dra7xx_smartreflex_hwmod_class,
1347 .clkdm_name = "coreaon_clkdm",
1348 .main_clk = "wkupaon_iclk_mux",
1351 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1352 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1353 .modulemode = MODULEMODE_SWCTRL,
1356 .dev_attr = &smartreflex_mpu_dev_attr,
1364 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1366 .sysc_offs = 0x0010,
1367 .syss_offs = 0x0014,
1368 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1369 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1370 SYSS_HAS_RESET_STATUS),
1371 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1372 .sysc_fields = &omap_hwmod_sysc_type1,
1375 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1377 .sysc = &dra7xx_spinlock_sysc,
1381 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1383 .class = &dra7xx_spinlock_hwmod_class,
1384 .clkdm_name = "l4cfg_clkdm",
1385 .main_clk = "l3_iclk_div",
1388 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1389 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1397 * This class contains several variants: ['timer_1ms', 'timer_secure',
1401 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1403 .sysc_offs = 0x0010,
1404 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1405 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1406 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1408 .sysc_fields = &omap_hwmod_sysc_type2,
1411 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1413 .sysc = &dra7xx_timer_1ms_sysc,
1416 static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1418 .sysc_offs = 0x0010,
1419 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1420 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1421 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1423 .sysc_fields = &omap_hwmod_sysc_type2,
1426 static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1428 .sysc = &dra7xx_timer_secure_sysc,
1431 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1433 .sysc_offs = 0x0010,
1434 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1435 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1436 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1438 .sysc_fields = &omap_hwmod_sysc_type2,
1441 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1443 .sysc = &dra7xx_timer_sysc,
1447 static struct omap_hwmod dra7xx_timer1_hwmod = {
1449 .class = &dra7xx_timer_1ms_hwmod_class,
1450 .clkdm_name = "wkupaon_clkdm",
1451 .main_clk = "timer1_gfclk_mux",
1454 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1455 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1456 .modulemode = MODULEMODE_SWCTRL,
1462 static struct omap_hwmod dra7xx_timer2_hwmod = {
1464 .class = &dra7xx_timer_1ms_hwmod_class,
1465 .clkdm_name = "l4per_clkdm",
1466 .main_clk = "timer2_gfclk_mux",
1469 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1470 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1471 .modulemode = MODULEMODE_SWCTRL,
1477 static struct omap_hwmod dra7xx_timer3_hwmod = {
1479 .class = &dra7xx_timer_hwmod_class,
1480 .clkdm_name = "l4per_clkdm",
1481 .main_clk = "timer3_gfclk_mux",
1484 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1485 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1486 .modulemode = MODULEMODE_SWCTRL,
1492 static struct omap_hwmod dra7xx_timer4_hwmod = {
1494 .class = &dra7xx_timer_secure_hwmod_class,
1495 .clkdm_name = "l4per_clkdm",
1496 .main_clk = "timer4_gfclk_mux",
1499 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1500 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1501 .modulemode = MODULEMODE_SWCTRL,
1507 static struct omap_hwmod dra7xx_timer5_hwmod = {
1509 .class = &dra7xx_timer_hwmod_class,
1510 .clkdm_name = "ipu_clkdm",
1511 .main_clk = "timer5_gfclk_mux",
1514 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1515 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1516 .modulemode = MODULEMODE_SWCTRL,
1522 static struct omap_hwmod dra7xx_timer6_hwmod = {
1524 .class = &dra7xx_timer_hwmod_class,
1525 .clkdm_name = "ipu_clkdm",
1526 .main_clk = "timer6_gfclk_mux",
1529 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1530 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1531 .modulemode = MODULEMODE_SWCTRL,
1537 static struct omap_hwmod dra7xx_timer7_hwmod = {
1539 .class = &dra7xx_timer_hwmod_class,
1540 .clkdm_name = "ipu_clkdm",
1541 .main_clk = "timer7_gfclk_mux",
1544 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1545 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1546 .modulemode = MODULEMODE_SWCTRL,
1552 static struct omap_hwmod dra7xx_timer8_hwmod = {
1554 .class = &dra7xx_timer_hwmod_class,
1555 .clkdm_name = "ipu_clkdm",
1556 .main_clk = "timer8_gfclk_mux",
1559 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1560 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1561 .modulemode = MODULEMODE_SWCTRL,
1567 static struct omap_hwmod dra7xx_timer9_hwmod = {
1569 .class = &dra7xx_timer_hwmod_class,
1570 .clkdm_name = "l4per_clkdm",
1571 .main_clk = "timer9_gfclk_mux",
1574 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1575 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1576 .modulemode = MODULEMODE_SWCTRL,
1582 static struct omap_hwmod dra7xx_timer10_hwmod = {
1584 .class = &dra7xx_timer_1ms_hwmod_class,
1585 .clkdm_name = "l4per_clkdm",
1586 .main_clk = "timer10_gfclk_mux",
1589 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1590 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1591 .modulemode = MODULEMODE_SWCTRL,
1597 static struct omap_hwmod dra7xx_timer11_hwmod = {
1599 .class = &dra7xx_timer_hwmod_class,
1600 .clkdm_name = "l4per_clkdm",
1601 .main_clk = "timer11_gfclk_mux",
1604 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1605 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1606 .modulemode = MODULEMODE_SWCTRL,
1616 static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1618 .sysc_offs = 0x0054,
1619 .syss_offs = 0x0058,
1620 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1621 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1622 SYSS_HAS_RESET_STATUS),
1623 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1625 .sysc_fields = &omap_hwmod_sysc_type1,
1628 static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1630 .sysc = &dra7xx_uart_sysc,
1634 static struct omap_hwmod dra7xx_uart1_hwmod = {
1636 .class = &dra7xx_uart_hwmod_class,
1637 .clkdm_name = "l4per_clkdm",
1638 .main_clk = "uart1_gfclk_mux",
1639 .flags = HWMOD_SWSUP_SIDLE_ACT | DEBUG_OMAP2UART1_FLAGS,
1642 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1643 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1644 .modulemode = MODULEMODE_SWCTRL,
1650 static struct omap_hwmod dra7xx_uart2_hwmod = {
1652 .class = &dra7xx_uart_hwmod_class,
1653 .clkdm_name = "l4per_clkdm",
1654 .main_clk = "uart2_gfclk_mux",
1655 .flags = HWMOD_SWSUP_SIDLE_ACT,
1658 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1659 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1660 .modulemode = MODULEMODE_SWCTRL,
1666 static struct omap_hwmod dra7xx_uart3_hwmod = {
1668 .class = &dra7xx_uart_hwmod_class,
1669 .clkdm_name = "l4per_clkdm",
1670 .main_clk = "uart3_gfclk_mux",
1671 .flags = HWMOD_SWSUP_SIDLE_ACT,
1674 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1675 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1676 .modulemode = MODULEMODE_SWCTRL,
1682 static struct omap_hwmod dra7xx_uart4_hwmod = {
1684 .class = &dra7xx_uart_hwmod_class,
1685 .clkdm_name = "l4per_clkdm",
1686 .main_clk = "uart4_gfclk_mux",
1687 .flags = HWMOD_SWSUP_SIDLE_ACT,
1690 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1691 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1692 .modulemode = MODULEMODE_SWCTRL,
1698 static struct omap_hwmod dra7xx_uart5_hwmod = {
1700 .class = &dra7xx_uart_hwmod_class,
1701 .clkdm_name = "l4per_clkdm",
1702 .main_clk = "uart5_gfclk_mux",
1703 .flags = HWMOD_SWSUP_SIDLE_ACT,
1706 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1707 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1708 .modulemode = MODULEMODE_SWCTRL,
1714 static struct omap_hwmod dra7xx_uart6_hwmod = {
1716 .class = &dra7xx_uart_hwmod_class,
1717 .clkdm_name = "ipu_clkdm",
1718 .main_clk = "uart6_gfclk_mux",
1719 .flags = HWMOD_SWSUP_SIDLE_ACT,
1722 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
1723 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
1724 .modulemode = MODULEMODE_SWCTRL,
1730 * 'usb_otg_ss' class
1734 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
1735 .name = "usb_otg_ss",
1739 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
1740 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
1743 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
1744 .name = "usb_otg_ss1",
1745 .class = &dra7xx_usb_otg_ss_hwmod_class,
1746 .clkdm_name = "l3init_clkdm",
1747 .main_clk = "dpll_core_h13x2_ck",
1750 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
1751 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
1752 .modulemode = MODULEMODE_HWCTRL,
1755 .opt_clks = usb_otg_ss1_opt_clks,
1756 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
1760 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
1761 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
1764 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
1765 .name = "usb_otg_ss2",
1766 .class = &dra7xx_usb_otg_ss_hwmod_class,
1767 .clkdm_name = "l3init_clkdm",
1768 .main_clk = "dpll_core_h13x2_ck",
1771 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
1772 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
1773 .modulemode = MODULEMODE_HWCTRL,
1776 .opt_clks = usb_otg_ss2_opt_clks,
1777 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
1781 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
1782 .name = "usb_otg_ss3",
1783 .class = &dra7xx_usb_otg_ss_hwmod_class,
1784 .clkdm_name = "l3init_clkdm",
1785 .main_clk = "dpll_core_h13x2_ck",
1788 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
1789 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
1790 .modulemode = MODULEMODE_HWCTRL,
1796 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
1797 .name = "usb_otg_ss4",
1798 .class = &dra7xx_usb_otg_ss_hwmod_class,
1799 .clkdm_name = "l3init_clkdm",
1800 .main_clk = "dpll_core_h13x2_ck",
1803 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
1804 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
1805 .modulemode = MODULEMODE_HWCTRL,
1815 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
1820 static struct omap_hwmod dra7xx_vcp1_hwmod = {
1822 .class = &dra7xx_vcp_hwmod_class,
1823 .clkdm_name = "l3main1_clkdm",
1824 .main_clk = "l3_iclk_div",
1827 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
1828 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
1834 static struct omap_hwmod dra7xx_vcp2_hwmod = {
1836 .class = &dra7xx_vcp_hwmod_class,
1837 .clkdm_name = "l3main1_clkdm",
1838 .main_clk = "l3_iclk_div",
1841 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
1842 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
1852 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
1854 .sysc_offs = 0x0010,
1855 .syss_offs = 0x0014,
1856 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1857 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1858 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1860 .sysc_fields = &omap_hwmod_sysc_type1,
1863 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
1865 .sysc = &dra7xx_wd_timer_sysc,
1866 .pre_shutdown = &omap2_wd_timer_disable,
1867 .reset = &omap2_wd_timer_reset,
1871 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
1872 .name = "wd_timer2",
1873 .class = &dra7xx_wd_timer_hwmod_class,
1874 .clkdm_name = "wkupaon_clkdm",
1875 .main_clk = "sys_32k_ck",
1878 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1879 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1880 .modulemode = MODULEMODE_SWCTRL,
1890 /* l3_main_2 -> l3_instr */
1891 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
1892 .master = &dra7xx_l3_main_2_hwmod,
1893 .slave = &dra7xx_l3_instr_hwmod,
1894 .clk = "l3_iclk_div",
1895 .user = OCP_USER_MPU | OCP_USER_SDMA,
1898 /* l4_cfg -> l3_main_1 */
1899 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
1900 .master = &dra7xx_l4_cfg_hwmod,
1901 .slave = &dra7xx_l3_main_1_hwmod,
1902 .clk = "l3_iclk_div",
1903 .user = OCP_USER_MPU | OCP_USER_SDMA,
1906 /* mpu -> l3_main_1 */
1907 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
1908 .master = &dra7xx_mpu_hwmod,
1909 .slave = &dra7xx_l3_main_1_hwmod,
1910 .clk = "l3_iclk_div",
1911 .user = OCP_USER_MPU,
1914 /* l3_main_1 -> l3_main_2 */
1915 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
1916 .master = &dra7xx_l3_main_1_hwmod,
1917 .slave = &dra7xx_l3_main_2_hwmod,
1918 .clk = "l3_iclk_div",
1919 .user = OCP_USER_MPU,
1922 /* l4_cfg -> l3_main_2 */
1923 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
1924 .master = &dra7xx_l4_cfg_hwmod,
1925 .slave = &dra7xx_l3_main_2_hwmod,
1926 .clk = "l3_iclk_div",
1927 .user = OCP_USER_MPU | OCP_USER_SDMA,
1930 /* l3_main_1 -> l4_cfg */
1931 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
1932 .master = &dra7xx_l3_main_1_hwmod,
1933 .slave = &dra7xx_l4_cfg_hwmod,
1934 .clk = "l3_iclk_div",
1935 .user = OCP_USER_MPU | OCP_USER_SDMA,
1938 /* l3_main_1 -> l4_per1 */
1939 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
1940 .master = &dra7xx_l3_main_1_hwmod,
1941 .slave = &dra7xx_l4_per1_hwmod,
1942 .clk = "l3_iclk_div",
1943 .user = OCP_USER_MPU | OCP_USER_SDMA,
1946 /* l3_main_1 -> l4_per2 */
1947 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
1948 .master = &dra7xx_l3_main_1_hwmod,
1949 .slave = &dra7xx_l4_per2_hwmod,
1950 .clk = "l3_iclk_div",
1951 .user = OCP_USER_MPU | OCP_USER_SDMA,
1954 /* l3_main_1 -> l4_per3 */
1955 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
1956 .master = &dra7xx_l3_main_1_hwmod,
1957 .slave = &dra7xx_l4_per3_hwmod,
1958 .clk = "l3_iclk_div",
1959 .user = OCP_USER_MPU | OCP_USER_SDMA,
1962 /* l3_main_1 -> l4_wkup */
1963 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
1964 .master = &dra7xx_l3_main_1_hwmod,
1965 .slave = &dra7xx_l4_wkup_hwmod,
1966 .clk = "wkupaon_iclk_mux",
1967 .user = OCP_USER_MPU | OCP_USER_SDMA,
1970 /* l4_per2 -> atl */
1971 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
1972 .master = &dra7xx_l4_per2_hwmod,
1973 .slave = &dra7xx_atl_hwmod,
1974 .clk = "l3_iclk_div",
1975 .user = OCP_USER_MPU | OCP_USER_SDMA,
1978 /* l3_main_1 -> bb2d */
1979 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
1980 .master = &dra7xx_l3_main_1_hwmod,
1981 .slave = &dra7xx_bb2d_hwmod,
1982 .clk = "l3_iclk_div",
1983 .user = OCP_USER_MPU | OCP_USER_SDMA,
1986 /* l4_wkup -> counter_32k */
1987 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
1988 .master = &dra7xx_l4_wkup_hwmod,
1989 .slave = &dra7xx_counter_32k_hwmod,
1990 .clk = "wkupaon_iclk_mux",
1991 .user = OCP_USER_MPU | OCP_USER_SDMA,
1994 /* l4_wkup -> ctrl_module_wkup */
1995 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
1996 .master = &dra7xx_l4_wkup_hwmod,
1997 .slave = &dra7xx_ctrl_module_wkup_hwmod,
1998 .clk = "wkupaon_iclk_mux",
1999 .user = OCP_USER_MPU | OCP_USER_SDMA,
2002 /* l4_wkup -> dcan1 */
2003 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2004 .master = &dra7xx_l4_wkup_hwmod,
2005 .slave = &dra7xx_dcan1_hwmod,
2006 .clk = "wkupaon_iclk_mux",
2007 .user = OCP_USER_MPU | OCP_USER_SDMA,
2010 /* l4_per2 -> dcan2 */
2011 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2012 .master = &dra7xx_l4_per2_hwmod,
2013 .slave = &dra7xx_dcan2_hwmod,
2014 .clk = "l3_iclk_div",
2015 .user = OCP_USER_MPU | OCP_USER_SDMA,
2018 static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2020 .pa_start = 0x4a056000,
2021 .pa_end = 0x4a056fff,
2022 .flags = ADDR_TYPE_RT
2027 /* l4_cfg -> dma_system */
2028 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2029 .master = &dra7xx_l4_cfg_hwmod,
2030 .slave = &dra7xx_dma_system_hwmod,
2031 .clk = "l3_iclk_div",
2032 .addr = dra7xx_dma_system_addrs,
2033 .user = OCP_USER_MPU | OCP_USER_SDMA,
2036 static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2039 .pa_start = 0x58000000,
2040 .pa_end = 0x5800007f,
2041 .flags = ADDR_TYPE_RT
2045 /* l3_main_1 -> dss */
2046 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2047 .master = &dra7xx_l3_main_1_hwmod,
2048 .slave = &dra7xx_dss_hwmod,
2049 .clk = "l3_iclk_div",
2050 .addr = dra7xx_dss_addrs,
2051 .user = OCP_USER_MPU | OCP_USER_SDMA,
2054 static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2057 .pa_start = 0x58001000,
2058 .pa_end = 0x58001fff,
2059 .flags = ADDR_TYPE_RT
2063 /* l3_main_1 -> dispc */
2064 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2065 .master = &dra7xx_l3_main_1_hwmod,
2066 .slave = &dra7xx_dss_dispc_hwmod,
2067 .clk = "l3_iclk_div",
2068 .addr = dra7xx_dss_dispc_addrs,
2069 .user = OCP_USER_MPU | OCP_USER_SDMA,
2072 static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2075 .pa_start = 0x58040000,
2076 .pa_end = 0x580400ff,
2077 .flags = ADDR_TYPE_RT
2082 /* l3_main_1 -> dispc */
2083 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2084 .master = &dra7xx_l3_main_1_hwmod,
2085 .slave = &dra7xx_dss_hdmi_hwmod,
2086 .clk = "l3_iclk_div",
2087 .addr = dra7xx_dss_hdmi_addrs,
2088 .user = OCP_USER_MPU | OCP_USER_SDMA,
2091 static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2093 .pa_start = 0x48078000,
2094 .pa_end = 0x48078fff,
2095 .flags = ADDR_TYPE_RT
2100 /* l4_per1 -> elm */
2101 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2102 .master = &dra7xx_l4_per1_hwmod,
2103 .slave = &dra7xx_elm_hwmod,
2104 .clk = "l3_iclk_div",
2105 .addr = dra7xx_elm_addrs,
2106 .user = OCP_USER_MPU | OCP_USER_SDMA,
2109 /* l4_wkup -> gpio1 */
2110 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2111 .master = &dra7xx_l4_wkup_hwmod,
2112 .slave = &dra7xx_gpio1_hwmod,
2113 .clk = "wkupaon_iclk_mux",
2114 .user = OCP_USER_MPU | OCP_USER_SDMA,
2117 /* l4_per1 -> gpio2 */
2118 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2119 .master = &dra7xx_l4_per1_hwmod,
2120 .slave = &dra7xx_gpio2_hwmod,
2121 .clk = "l3_iclk_div",
2122 .user = OCP_USER_MPU | OCP_USER_SDMA,
2125 /* l4_per1 -> gpio3 */
2126 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2127 .master = &dra7xx_l4_per1_hwmod,
2128 .slave = &dra7xx_gpio3_hwmod,
2129 .clk = "l3_iclk_div",
2130 .user = OCP_USER_MPU | OCP_USER_SDMA,
2133 /* l4_per1 -> gpio4 */
2134 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2135 .master = &dra7xx_l4_per1_hwmod,
2136 .slave = &dra7xx_gpio4_hwmod,
2137 .clk = "l3_iclk_div",
2138 .user = OCP_USER_MPU | OCP_USER_SDMA,
2141 /* l4_per1 -> gpio5 */
2142 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2143 .master = &dra7xx_l4_per1_hwmod,
2144 .slave = &dra7xx_gpio5_hwmod,
2145 .clk = "l3_iclk_div",
2146 .user = OCP_USER_MPU | OCP_USER_SDMA,
2149 /* l4_per1 -> gpio6 */
2150 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2151 .master = &dra7xx_l4_per1_hwmod,
2152 .slave = &dra7xx_gpio6_hwmod,
2153 .clk = "l3_iclk_div",
2154 .user = OCP_USER_MPU | OCP_USER_SDMA,
2157 /* l4_per1 -> gpio7 */
2158 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2159 .master = &dra7xx_l4_per1_hwmod,
2160 .slave = &dra7xx_gpio7_hwmod,
2161 .clk = "l3_iclk_div",
2162 .user = OCP_USER_MPU | OCP_USER_SDMA,
2165 /* l4_per1 -> gpio8 */
2166 static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2167 .master = &dra7xx_l4_per1_hwmod,
2168 .slave = &dra7xx_gpio8_hwmod,
2169 .clk = "l3_iclk_div",
2170 .user = OCP_USER_MPU | OCP_USER_SDMA,
2173 static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2175 .pa_start = 0x50000000,
2176 .pa_end = 0x500003ff,
2177 .flags = ADDR_TYPE_RT
2182 /* l3_main_1 -> gpmc */
2183 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2184 .master = &dra7xx_l3_main_1_hwmod,
2185 .slave = &dra7xx_gpmc_hwmod,
2186 .clk = "l3_iclk_div",
2187 .addr = dra7xx_gpmc_addrs,
2188 .user = OCP_USER_MPU | OCP_USER_SDMA,
2191 static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2193 .pa_start = 0x480b2000,
2194 .pa_end = 0x480b201f,
2195 .flags = ADDR_TYPE_RT
2200 /* l4_per1 -> hdq1w */
2201 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2202 .master = &dra7xx_l4_per1_hwmod,
2203 .slave = &dra7xx_hdq1w_hwmod,
2204 .clk = "l3_iclk_div",
2205 .addr = dra7xx_hdq1w_addrs,
2206 .user = OCP_USER_MPU | OCP_USER_SDMA,
2209 /* l4_per1 -> i2c1 */
2210 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2211 .master = &dra7xx_l4_per1_hwmod,
2212 .slave = &dra7xx_i2c1_hwmod,
2213 .clk = "l3_iclk_div",
2214 .user = OCP_USER_MPU | OCP_USER_SDMA,
2217 /* l4_per1 -> i2c2 */
2218 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2219 .master = &dra7xx_l4_per1_hwmod,
2220 .slave = &dra7xx_i2c2_hwmod,
2221 .clk = "l3_iclk_div",
2222 .user = OCP_USER_MPU | OCP_USER_SDMA,
2225 /* l4_per1 -> i2c3 */
2226 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2227 .master = &dra7xx_l4_per1_hwmod,
2228 .slave = &dra7xx_i2c3_hwmod,
2229 .clk = "l3_iclk_div",
2230 .user = OCP_USER_MPU | OCP_USER_SDMA,
2233 /* l4_per1 -> i2c4 */
2234 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2235 .master = &dra7xx_l4_per1_hwmod,
2236 .slave = &dra7xx_i2c4_hwmod,
2237 .clk = "l3_iclk_div",
2238 .user = OCP_USER_MPU | OCP_USER_SDMA,
2241 /* l4_per1 -> i2c5 */
2242 static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2243 .master = &dra7xx_l4_per1_hwmod,
2244 .slave = &dra7xx_i2c5_hwmod,
2245 .clk = "l3_iclk_div",
2246 .user = OCP_USER_MPU | OCP_USER_SDMA,
2249 /* l4_per1 -> mcspi1 */
2250 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2251 .master = &dra7xx_l4_per1_hwmod,
2252 .slave = &dra7xx_mcspi1_hwmod,
2253 .clk = "l3_iclk_div",
2254 .user = OCP_USER_MPU | OCP_USER_SDMA,
2257 /* l4_per1 -> mcspi2 */
2258 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2259 .master = &dra7xx_l4_per1_hwmod,
2260 .slave = &dra7xx_mcspi2_hwmod,
2261 .clk = "l3_iclk_div",
2262 .user = OCP_USER_MPU | OCP_USER_SDMA,
2265 /* l4_per1 -> mcspi3 */
2266 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2267 .master = &dra7xx_l4_per1_hwmod,
2268 .slave = &dra7xx_mcspi3_hwmod,
2269 .clk = "l3_iclk_div",
2270 .user = OCP_USER_MPU | OCP_USER_SDMA,
2273 /* l4_per1 -> mcspi4 */
2274 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2275 .master = &dra7xx_l4_per1_hwmod,
2276 .slave = &dra7xx_mcspi4_hwmod,
2277 .clk = "l3_iclk_div",
2278 .user = OCP_USER_MPU | OCP_USER_SDMA,
2281 /* l4_per1 -> mmc1 */
2282 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2283 .master = &dra7xx_l4_per1_hwmod,
2284 .slave = &dra7xx_mmc1_hwmod,
2285 .clk = "l3_iclk_div",
2286 .user = OCP_USER_MPU | OCP_USER_SDMA,
2289 /* l4_per1 -> mmc2 */
2290 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2291 .master = &dra7xx_l4_per1_hwmod,
2292 .slave = &dra7xx_mmc2_hwmod,
2293 .clk = "l3_iclk_div",
2294 .user = OCP_USER_MPU | OCP_USER_SDMA,
2297 /* l4_per1 -> mmc3 */
2298 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2299 .master = &dra7xx_l4_per1_hwmod,
2300 .slave = &dra7xx_mmc3_hwmod,
2301 .clk = "l3_iclk_div",
2302 .user = OCP_USER_MPU | OCP_USER_SDMA,
2305 /* l4_per1 -> mmc4 */
2306 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2307 .master = &dra7xx_l4_per1_hwmod,
2308 .slave = &dra7xx_mmc4_hwmod,
2309 .clk = "l3_iclk_div",
2310 .user = OCP_USER_MPU | OCP_USER_SDMA,
2314 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2315 .master = &dra7xx_l4_cfg_hwmod,
2316 .slave = &dra7xx_mpu_hwmod,
2317 .clk = "l3_iclk_div",
2318 .user = OCP_USER_MPU | OCP_USER_SDMA,
2321 static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
2323 .pa_start = 0x4a080000,
2324 .pa_end = 0x4a08001f,
2325 .flags = ADDR_TYPE_RT
2330 /* l4_cfg -> ocp2scp1 */
2331 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2332 .master = &dra7xx_l4_cfg_hwmod,
2333 .slave = &dra7xx_ocp2scp1_hwmod,
2334 .clk = "l4_root_clk_div",
2335 .addr = dra7xx_ocp2scp1_addrs,
2336 .user = OCP_USER_MPU | OCP_USER_SDMA,
2339 static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2341 .pa_start = 0x4b300000,
2342 .pa_end = 0x4b30007f,
2343 .flags = ADDR_TYPE_RT
2348 /* l3_main_1 -> qspi */
2349 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2350 .master = &dra7xx_l3_main_1_hwmod,
2351 .slave = &dra7xx_qspi_hwmod,
2352 .clk = "l3_iclk_div",
2353 .addr = dra7xx_qspi_addrs,
2354 .user = OCP_USER_MPU | OCP_USER_SDMA,
2357 static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2360 .pa_start = 0x4a141100,
2361 .pa_end = 0x4a141107,
2362 .flags = ADDR_TYPE_RT
2367 /* l4_cfg -> sata */
2368 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2369 .master = &dra7xx_l4_cfg_hwmod,
2370 .slave = &dra7xx_sata_hwmod,
2371 .clk = "l3_iclk_div",
2372 .addr = dra7xx_sata_addrs,
2373 .user = OCP_USER_MPU | OCP_USER_SDMA,
2376 static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2378 .pa_start = 0x4a0dd000,
2379 .pa_end = 0x4a0dd07f,
2380 .flags = ADDR_TYPE_RT
2385 /* l4_cfg -> smartreflex_core */
2386 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2387 .master = &dra7xx_l4_cfg_hwmod,
2388 .slave = &dra7xx_smartreflex_core_hwmod,
2389 .clk = "l4_root_clk_div",
2390 .addr = dra7xx_smartreflex_core_addrs,
2391 .user = OCP_USER_MPU | OCP_USER_SDMA,
2394 static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2396 .pa_start = 0x4a0d9000,
2397 .pa_end = 0x4a0d907f,
2398 .flags = ADDR_TYPE_RT
2403 /* l4_cfg -> smartreflex_mpu */
2404 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2405 .master = &dra7xx_l4_cfg_hwmod,
2406 .slave = &dra7xx_smartreflex_mpu_hwmod,
2407 .clk = "l4_root_clk_div",
2408 .addr = dra7xx_smartreflex_mpu_addrs,
2409 .user = OCP_USER_MPU | OCP_USER_SDMA,
2412 static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
2414 .pa_start = 0x4a0f6000,
2415 .pa_end = 0x4a0f6fff,
2416 .flags = ADDR_TYPE_RT
2421 /* l4_cfg -> spinlock */
2422 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2423 .master = &dra7xx_l4_cfg_hwmod,
2424 .slave = &dra7xx_spinlock_hwmod,
2425 .clk = "l3_iclk_div",
2426 .addr = dra7xx_spinlock_addrs,
2427 .user = OCP_USER_MPU | OCP_USER_SDMA,
2430 /* l4_wkup -> timer1 */
2431 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2432 .master = &dra7xx_l4_wkup_hwmod,
2433 .slave = &dra7xx_timer1_hwmod,
2434 .clk = "wkupaon_iclk_mux",
2435 .user = OCP_USER_MPU | OCP_USER_SDMA,
2438 /* l4_per1 -> timer2 */
2439 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2440 .master = &dra7xx_l4_per1_hwmod,
2441 .slave = &dra7xx_timer2_hwmod,
2442 .clk = "l3_iclk_div",
2443 .user = OCP_USER_MPU | OCP_USER_SDMA,
2446 /* l4_per1 -> timer3 */
2447 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2448 .master = &dra7xx_l4_per1_hwmod,
2449 .slave = &dra7xx_timer3_hwmod,
2450 .clk = "l3_iclk_div",
2451 .user = OCP_USER_MPU | OCP_USER_SDMA,
2454 /* l4_per1 -> timer4 */
2455 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2456 .master = &dra7xx_l4_per1_hwmod,
2457 .slave = &dra7xx_timer4_hwmod,
2458 .clk = "l3_iclk_div",
2459 .user = OCP_USER_MPU | OCP_USER_SDMA,
2462 /* l4_per3 -> timer5 */
2463 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2464 .master = &dra7xx_l4_per3_hwmod,
2465 .slave = &dra7xx_timer5_hwmod,
2466 .clk = "l3_iclk_div",
2467 .user = OCP_USER_MPU | OCP_USER_SDMA,
2470 /* l4_per3 -> timer6 */
2471 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
2472 .master = &dra7xx_l4_per3_hwmod,
2473 .slave = &dra7xx_timer6_hwmod,
2474 .clk = "l3_iclk_div",
2475 .user = OCP_USER_MPU | OCP_USER_SDMA,
2478 /* l4_per3 -> timer7 */
2479 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
2480 .master = &dra7xx_l4_per3_hwmod,
2481 .slave = &dra7xx_timer7_hwmod,
2482 .clk = "l3_iclk_div",
2483 .user = OCP_USER_MPU | OCP_USER_SDMA,
2486 /* l4_per3 -> timer8 */
2487 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
2488 .master = &dra7xx_l4_per3_hwmod,
2489 .slave = &dra7xx_timer8_hwmod,
2490 .clk = "l3_iclk_div",
2491 .user = OCP_USER_MPU | OCP_USER_SDMA,
2494 /* l4_per1 -> timer9 */
2495 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
2496 .master = &dra7xx_l4_per1_hwmod,
2497 .slave = &dra7xx_timer9_hwmod,
2498 .clk = "l3_iclk_div",
2499 .user = OCP_USER_MPU | OCP_USER_SDMA,
2502 /* l4_per1 -> timer10 */
2503 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
2504 .master = &dra7xx_l4_per1_hwmod,
2505 .slave = &dra7xx_timer10_hwmod,
2506 .clk = "l3_iclk_div",
2507 .user = OCP_USER_MPU | OCP_USER_SDMA,
2510 /* l4_per1 -> timer11 */
2511 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
2512 .master = &dra7xx_l4_per1_hwmod,
2513 .slave = &dra7xx_timer11_hwmod,
2514 .clk = "l3_iclk_div",
2515 .user = OCP_USER_MPU | OCP_USER_SDMA,
2518 /* l4_per1 -> uart1 */
2519 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
2520 .master = &dra7xx_l4_per1_hwmod,
2521 .slave = &dra7xx_uart1_hwmod,
2522 .clk = "l3_iclk_div",
2523 .user = OCP_USER_MPU | OCP_USER_SDMA,
2526 /* l4_per1 -> uart2 */
2527 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
2528 .master = &dra7xx_l4_per1_hwmod,
2529 .slave = &dra7xx_uart2_hwmod,
2530 .clk = "l3_iclk_div",
2531 .user = OCP_USER_MPU | OCP_USER_SDMA,
2534 /* l4_per1 -> uart3 */
2535 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
2536 .master = &dra7xx_l4_per1_hwmod,
2537 .slave = &dra7xx_uart3_hwmod,
2538 .clk = "l3_iclk_div",
2539 .user = OCP_USER_MPU | OCP_USER_SDMA,
2542 /* l4_per1 -> uart4 */
2543 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
2544 .master = &dra7xx_l4_per1_hwmod,
2545 .slave = &dra7xx_uart4_hwmod,
2546 .clk = "l3_iclk_div",
2547 .user = OCP_USER_MPU | OCP_USER_SDMA,
2550 /* l4_per1 -> uart5 */
2551 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
2552 .master = &dra7xx_l4_per1_hwmod,
2553 .slave = &dra7xx_uart5_hwmod,
2554 .clk = "l3_iclk_div",
2555 .user = OCP_USER_MPU | OCP_USER_SDMA,
2558 /* l4_per1 -> uart6 */
2559 static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
2560 .master = &dra7xx_l4_per1_hwmod,
2561 .slave = &dra7xx_uart6_hwmod,
2562 .clk = "l3_iclk_div",
2563 .user = OCP_USER_MPU | OCP_USER_SDMA,
2566 /* l4_per3 -> usb_otg_ss1 */
2567 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
2568 .master = &dra7xx_l4_per3_hwmod,
2569 .slave = &dra7xx_usb_otg_ss1_hwmod,
2570 .clk = "dpll_core_h13x2_ck",
2571 .user = OCP_USER_MPU | OCP_USER_SDMA,
2574 /* l4_per3 -> usb_otg_ss2 */
2575 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
2576 .master = &dra7xx_l4_per3_hwmod,
2577 .slave = &dra7xx_usb_otg_ss2_hwmod,
2578 .clk = "dpll_core_h13x2_ck",
2579 .user = OCP_USER_MPU | OCP_USER_SDMA,
2582 /* l4_per3 -> usb_otg_ss3 */
2583 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
2584 .master = &dra7xx_l4_per3_hwmod,
2585 .slave = &dra7xx_usb_otg_ss3_hwmod,
2586 .clk = "dpll_core_h13x2_ck",
2587 .user = OCP_USER_MPU | OCP_USER_SDMA,
2590 /* l4_per3 -> usb_otg_ss4 */
2591 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
2592 .master = &dra7xx_l4_per3_hwmod,
2593 .slave = &dra7xx_usb_otg_ss4_hwmod,
2594 .clk = "dpll_core_h13x2_ck",
2595 .user = OCP_USER_MPU | OCP_USER_SDMA,
2598 /* l3_main_1 -> vcp1 */
2599 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
2600 .master = &dra7xx_l3_main_1_hwmod,
2601 .slave = &dra7xx_vcp1_hwmod,
2602 .clk = "l3_iclk_div",
2603 .user = OCP_USER_MPU | OCP_USER_SDMA,
2606 /* l4_per2 -> vcp1 */
2607 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
2608 .master = &dra7xx_l4_per2_hwmod,
2609 .slave = &dra7xx_vcp1_hwmod,
2610 .clk = "l3_iclk_div",
2611 .user = OCP_USER_MPU | OCP_USER_SDMA,
2614 /* l3_main_1 -> vcp2 */
2615 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
2616 .master = &dra7xx_l3_main_1_hwmod,
2617 .slave = &dra7xx_vcp2_hwmod,
2618 .clk = "l3_iclk_div",
2619 .user = OCP_USER_MPU | OCP_USER_SDMA,
2622 /* l4_per2 -> vcp2 */
2623 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
2624 .master = &dra7xx_l4_per2_hwmod,
2625 .slave = &dra7xx_vcp2_hwmod,
2626 .clk = "l3_iclk_div",
2627 .user = OCP_USER_MPU | OCP_USER_SDMA,
2630 /* l4_wkup -> wd_timer2 */
2631 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
2632 .master = &dra7xx_l4_wkup_hwmod,
2633 .slave = &dra7xx_wd_timer2_hwmod,
2634 .clk = "wkupaon_iclk_mux",
2635 .user = OCP_USER_MPU | OCP_USER_SDMA,
2638 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2639 &dra7xx_l3_main_2__l3_instr,
2640 &dra7xx_l4_cfg__l3_main_1,
2641 &dra7xx_mpu__l3_main_1,
2642 &dra7xx_l3_main_1__l3_main_2,
2643 &dra7xx_l4_cfg__l3_main_2,
2644 &dra7xx_l3_main_1__l4_cfg,
2645 &dra7xx_l3_main_1__l4_per1,
2646 &dra7xx_l3_main_1__l4_per2,
2647 &dra7xx_l3_main_1__l4_per3,
2648 &dra7xx_l3_main_1__l4_wkup,
2649 &dra7xx_l4_per2__atl,
2650 &dra7xx_l3_main_1__bb2d,
2651 &dra7xx_l4_wkup__counter_32k,
2652 &dra7xx_l4_wkup__ctrl_module_wkup,
2653 &dra7xx_l4_wkup__dcan1,
2654 &dra7xx_l4_per2__dcan2,
2655 &dra7xx_l4_cfg__dma_system,
2656 &dra7xx_l3_main_1__dss,
2657 &dra7xx_l3_main_1__dispc,
2658 &dra7xx_l3_main_1__hdmi,
2659 &dra7xx_l4_per1__elm,
2660 &dra7xx_l4_wkup__gpio1,
2661 &dra7xx_l4_per1__gpio2,
2662 &dra7xx_l4_per1__gpio3,
2663 &dra7xx_l4_per1__gpio4,
2664 &dra7xx_l4_per1__gpio5,
2665 &dra7xx_l4_per1__gpio6,
2666 &dra7xx_l4_per1__gpio7,
2667 &dra7xx_l4_per1__gpio8,
2668 &dra7xx_l3_main_1__gpmc,
2669 &dra7xx_l4_per1__hdq1w,
2670 &dra7xx_l4_per1__i2c1,
2671 &dra7xx_l4_per1__i2c2,
2672 &dra7xx_l4_per1__i2c3,
2673 &dra7xx_l4_per1__i2c4,
2674 &dra7xx_l4_per1__i2c5,
2675 &dra7xx_l4_per1__mcspi1,
2676 &dra7xx_l4_per1__mcspi2,
2677 &dra7xx_l4_per1__mcspi3,
2678 &dra7xx_l4_per1__mcspi4,
2679 &dra7xx_l4_per1__mmc1,
2680 &dra7xx_l4_per1__mmc2,
2681 &dra7xx_l4_per1__mmc3,
2682 &dra7xx_l4_per1__mmc4,
2683 &dra7xx_l4_cfg__mpu,
2684 &dra7xx_l4_cfg__ocp2scp1,
2685 &dra7xx_l3_main_1__qspi,
2686 &dra7xx_l4_cfg__sata,
2687 &dra7xx_l4_cfg__smartreflex_core,
2688 &dra7xx_l4_cfg__smartreflex_mpu,
2689 &dra7xx_l4_cfg__spinlock,
2690 &dra7xx_l4_wkup__timer1,
2691 &dra7xx_l4_per1__timer2,
2692 &dra7xx_l4_per1__timer3,
2693 &dra7xx_l4_per1__timer4,
2694 &dra7xx_l4_per3__timer5,
2695 &dra7xx_l4_per3__timer6,
2696 &dra7xx_l4_per3__timer7,
2697 &dra7xx_l4_per3__timer8,
2698 &dra7xx_l4_per1__timer9,
2699 &dra7xx_l4_per1__timer10,
2700 &dra7xx_l4_per1__timer11,
2701 &dra7xx_l4_per1__uart1,
2702 &dra7xx_l4_per1__uart2,
2703 &dra7xx_l4_per1__uart3,
2704 &dra7xx_l4_per1__uart4,
2705 &dra7xx_l4_per1__uart5,
2706 &dra7xx_l4_per1__uart6,
2707 &dra7xx_l4_per3__usb_otg_ss1,
2708 &dra7xx_l4_per3__usb_otg_ss2,
2709 &dra7xx_l4_per3__usb_otg_ss3,
2710 &dra7xx_l4_per3__usb_otg_ss4,
2711 &dra7xx_l3_main_1__vcp1,
2712 &dra7xx_l4_per2__vcp1,
2713 &dra7xx_l3_main_1__vcp2,
2714 &dra7xx_l4_per2__vcp2,
2715 &dra7xx_l4_wkup__wd_timer2,
2719 int __init dra7xx_hwmod_init(void)
2722 return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);