2 * Hardware modules present on the DRA7xx chips
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
21 #include <linux/power/smartreflex.h>
23 #include <linux/omap-dma.h>
25 #include "omap_hwmod.h"
26 #include "omap_hwmod_common_data.h"
33 /* Base offset for all DRA7XX interrupts external to MPUSS */
34 #define DRA7XX_IRQ_GIC_START 32
36 /* Base offset for all DRA7XX dma requests */
37 #define DRA7XX_DMA_REQ_START 1
48 static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
53 static struct omap_hwmod dra7xx_dmm_hwmod = {
55 .class = &dra7xx_dmm_hwmod_class,
56 .clkdm_name = "emif_clkdm",
59 .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
60 .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
67 * instance(s): l3_instr, l3_main_1, l3_main_2
69 static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
74 static struct omap_hwmod dra7xx_l3_instr_hwmod = {
76 .class = &dra7xx_l3_hwmod_class,
77 .clkdm_name = "l3instr_clkdm",
80 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
81 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
82 .modulemode = MODULEMODE_HWCTRL,
88 static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
90 .class = &dra7xx_l3_hwmod_class,
91 .clkdm_name = "l3main1_clkdm",
94 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
95 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
101 static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
103 .class = &dra7xx_l3_hwmod_class,
104 .clkdm_name = "l3instr_clkdm",
107 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
108 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
109 .modulemode = MODULEMODE_HWCTRL,
116 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
118 static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
123 static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
125 .class = &dra7xx_l4_hwmod_class,
126 .clkdm_name = "l4cfg_clkdm",
129 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
130 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
136 static struct omap_hwmod dra7xx_l4_per1_hwmod = {
138 .class = &dra7xx_l4_hwmod_class,
139 .clkdm_name = "l4per_clkdm",
142 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
143 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
149 static struct omap_hwmod dra7xx_l4_per2_hwmod = {
151 .class = &dra7xx_l4_hwmod_class,
152 .clkdm_name = "l4per2_clkdm",
155 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
156 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
162 static struct omap_hwmod dra7xx_l4_per3_hwmod = {
164 .class = &dra7xx_l4_hwmod_class,
165 .clkdm_name = "l4per3_clkdm",
168 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
169 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
175 static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
177 .class = &dra7xx_l4_hwmod_class,
178 .clkdm_name = "wkupaon_clkdm",
181 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
182 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
192 static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
197 static struct omap_hwmod dra7xx_atl_hwmod = {
199 .class = &dra7xx_atl_hwmod_class,
200 .clkdm_name = "atl_clkdm",
201 .main_clk = "atl_gfclk_mux",
204 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
205 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
206 .modulemode = MODULEMODE_SWCTRL,
216 static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
221 static struct omap_hwmod dra7xx_bb2d_hwmod = {
223 .class = &dra7xx_bb2d_hwmod_class,
224 .clkdm_name = "dss_clkdm",
225 .main_clk = "dpll_core_h24x2_ck",
228 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
229 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
230 .modulemode = MODULEMODE_SWCTRL,
240 static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
243 .sysc_flags = SYSC_HAS_SIDLEMODE,
244 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
246 .sysc_fields = &omap_hwmod_sysc_type1,
249 static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
251 .sysc = &dra7xx_counter_sysc,
255 static struct omap_hwmod dra7xx_counter_32k_hwmod = {
256 .name = "counter_32k",
257 .class = &dra7xx_counter_hwmod_class,
258 .clkdm_name = "wkupaon_clkdm",
259 .flags = HWMOD_SWSUP_SIDLE,
260 .main_clk = "wkupaon_iclk_mux",
263 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
264 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
270 * 'ctrl_module' class
274 static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
275 .name = "ctrl_module",
278 /* ctrl_module_wkup */
279 static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
280 .name = "ctrl_module_wkup",
281 .class = &dra7xx_ctrl_module_hwmod_class,
282 .clkdm_name = "wkupaon_clkdm",
285 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
292 * cpsw/gmac sub system
294 static struct omap_hwmod_class_sysconfig dra7xx_gmac_sysc = {
298 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
299 SYSS_HAS_RESET_STATUS),
300 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
302 .sysc_fields = &omap_hwmod_sysc_type3,
305 static struct omap_hwmod_class dra7xx_gmac_hwmod_class = {
307 .sysc = &dra7xx_gmac_sysc,
310 static struct omap_hwmod dra7xx_gmac_hwmod = {
312 .class = &dra7xx_gmac_hwmod_class,
313 .clkdm_name = "gmac_clkdm",
314 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
315 .main_clk = "dpll_gmac_ck",
319 .clkctrl_offs = DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET,
320 .context_offs = DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET,
321 .modulemode = MODULEMODE_SWCTRL,
329 static struct omap_hwmod_class dra7xx_mdio_hwmod_class = {
330 .name = "davinci_mdio",
333 static struct omap_hwmod dra7xx_mdio_hwmod = {
334 .name = "davinci_mdio",
335 .class = &dra7xx_mdio_hwmod_class,
336 .clkdm_name = "gmac_clkdm",
337 .main_clk = "dpll_gmac_ck",
345 static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
350 static struct omap_hwmod dra7xx_dcan1_hwmod = {
352 .class = &dra7xx_dcan_hwmod_class,
353 .clkdm_name = "wkupaon_clkdm",
354 .main_clk = "dcan1_sys_clk_mux",
355 .flags = HWMOD_CLKDM_NOAUTO,
358 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
359 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
360 .modulemode = MODULEMODE_SWCTRL,
366 static struct omap_hwmod dra7xx_dcan2_hwmod = {
368 .class = &dra7xx_dcan_hwmod_class,
369 .clkdm_name = "l4per2_clkdm",
370 .main_clk = "sys_clkin1",
371 .flags = HWMOD_CLKDM_NOAUTO,
374 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
375 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
376 .modulemode = MODULEMODE_SWCTRL,
382 static struct omap_hwmod_class_sysconfig dra7xx_epwmss_sysc = {
385 .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET,
386 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
387 .sysc_fields = &omap_hwmod_sysc_type2,
393 static struct omap_hwmod_class dra7xx_epwmss_hwmod_class = {
395 .sysc = &dra7xx_epwmss_sysc,
399 static struct omap_hwmod dra7xx_epwmss0_hwmod = {
401 .class = &dra7xx_epwmss_hwmod_class,
402 .clkdm_name = "l4per2_clkdm",
403 .main_clk = "l4_root_clk_div",
406 .modulemode = MODULEMODE_SWCTRL,
407 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET,
408 .context_offs = DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET,
414 static struct omap_hwmod dra7xx_epwmss1_hwmod = {
416 .class = &dra7xx_epwmss_hwmod_class,
417 .clkdm_name = "l4per2_clkdm",
418 .main_clk = "l4_root_clk_div",
421 .modulemode = MODULEMODE_SWCTRL,
422 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET,
423 .context_offs = DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET,
429 static struct omap_hwmod dra7xx_epwmss2_hwmod = {
431 .class = &dra7xx_epwmss_hwmod_class,
432 .clkdm_name = "l4per2_clkdm",
433 .main_clk = "l4_root_clk_div",
436 .modulemode = MODULEMODE_SWCTRL,
437 .clkctrl_offs = DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET,
438 .context_offs = DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET,
448 static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
452 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
453 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
454 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
455 SYSS_HAS_RESET_STATUS),
456 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
457 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
458 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
459 .sysc_fields = &omap_hwmod_sysc_type1,
462 static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
464 .sysc = &dra7xx_dma_sysc,
468 static struct omap_dma_dev_attr dma_dev_attr = {
469 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
470 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
475 static struct omap_hwmod dra7xx_dma_system_hwmod = {
476 .name = "dma_system",
477 .class = &dra7xx_dma_hwmod_class,
478 .clkdm_name = "dma_clkdm",
479 .main_clk = "l3_iclk_div",
482 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
483 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
486 .dev_attr = &dma_dev_attr,
493 static struct omap_hwmod_class dra7xx_tpcc_hwmod_class = {
497 static struct omap_hwmod dra7xx_tpcc_hwmod = {
499 .class = &dra7xx_tpcc_hwmod_class,
500 .clkdm_name = "l3main1_clkdm",
501 .main_clk = "l3_iclk_div",
504 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET,
505 .context_offs = DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET,
514 static struct omap_hwmod_class dra7xx_tptc_hwmod_class = {
519 static struct omap_hwmod dra7xx_tptc0_hwmod = {
521 .class = &dra7xx_tptc_hwmod_class,
522 .clkdm_name = "l3main1_clkdm",
523 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
524 .main_clk = "l3_iclk_div",
527 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET,
528 .context_offs = DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET,
529 .modulemode = MODULEMODE_HWCTRL,
535 static struct omap_hwmod dra7xx_tptc1_hwmod = {
537 .class = &dra7xx_tptc_hwmod_class,
538 .clkdm_name = "l3main1_clkdm",
539 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
540 .main_clk = "l3_iclk_div",
543 .clkctrl_offs = DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET,
544 .context_offs = DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET,
545 .modulemode = MODULEMODE_HWCTRL,
555 static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
558 .sysc_flags = SYSS_HAS_RESET_STATUS,
561 static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
563 .sysc = &dra7xx_dss_sysc,
564 .reset = omap_dss_reset,
568 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
569 { .role = "dss_clk", .clk = "dss_dss_clk" },
570 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
571 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
572 { .role = "video2_clk", .clk = "dss_video2_clk" },
573 { .role = "video1_clk", .clk = "dss_video1_clk" },
574 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
575 { .role = "hdcp_clk", .clk = "dss_deshdcp_clk" },
578 static struct omap_hwmod dra7xx_dss_hwmod = {
580 .class = &dra7xx_dss_hwmod_class,
581 .clkdm_name = "dss_clkdm",
582 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
583 .main_clk = "dss_dss_clk",
586 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
587 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
588 .modulemode = MODULEMODE_SWCTRL,
591 .opt_clks = dss_opt_clks,
592 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
600 static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
604 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
605 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
606 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
607 SYSS_HAS_RESET_STATUS),
608 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
609 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
610 .sysc_fields = &omap_hwmod_sysc_type1,
613 static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
615 .sysc = &dra7xx_dispc_sysc,
619 /* dss_dispc dev_attr */
620 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
621 .has_framedonetv_irq = 1,
625 static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
627 .class = &dra7xx_dispc_hwmod_class,
628 .clkdm_name = "dss_clkdm",
629 .main_clk = "dss_dss_clk",
632 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
633 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
636 .dev_attr = &dss_dispc_dev_attr,
637 .parent_hwmod = &dra7xx_dss_hwmod,
645 static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
648 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
650 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
652 .sysc_fields = &omap_hwmod_sysc_type2,
655 static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
657 .sysc = &dra7xx_hdmi_sysc,
662 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
663 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
666 static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
668 .class = &dra7xx_hdmi_hwmod_class,
669 .clkdm_name = "dss_clkdm",
670 .main_clk = "dss_48mhz_clk",
673 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
674 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
677 .opt_clks = dss_hdmi_opt_clks,
678 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
679 .parent_hwmod = &dra7xx_dss_hwmod,
682 /* AES (the 'P' (public) device) */
683 static struct omap_hwmod_class_sysconfig dra7xx_aes_sysc = {
687 .sysc_flags = SYSS_HAS_RESET_STATUS,
690 static struct omap_hwmod_class dra7xx_aes_hwmod_class = {
692 .sysc = &dra7xx_aes_sysc,
696 static struct omap_hwmod dra7xx_aes1_hwmod = {
698 .class = &dra7xx_aes_hwmod_class,
699 .clkdm_name = "l4sec_clkdm",
700 .main_clk = "l3_iclk_div",
703 .clkctrl_offs = DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET,
704 .context_offs = DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET,
705 .modulemode = MODULEMODE_HWCTRL,
711 static struct omap_hwmod dra7xx_aes2_hwmod = {
713 .class = &dra7xx_aes_hwmod_class,
714 .clkdm_name = "l4sec_clkdm",
715 .main_clk = "l3_iclk_div",
718 .clkctrl_offs = DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET,
719 .context_offs = DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET,
720 .modulemode = MODULEMODE_HWCTRL,
725 /* sha0 HIB2 (the 'P' (public) device) */
726 static struct omap_hwmod_class_sysconfig dra7xx_sha0_sysc = {
730 .sysc_flags = SYSS_HAS_RESET_STATUS,
733 static struct omap_hwmod_class dra7xx_sha0_hwmod_class = {
735 .sysc = &dra7xx_sha0_sysc,
738 struct omap_hwmod dra7xx_sha0_hwmod = {
740 .class = &dra7xx_sha0_hwmod_class,
741 .clkdm_name = "l4sec_clkdm",
742 .main_clk = "l3_iclk_div",
745 .clkctrl_offs = DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
746 .context_offs = DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
747 .modulemode = MODULEMODE_HWCTRL,
757 static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
761 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
762 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
763 SYSS_HAS_RESET_STATUS),
764 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
766 .sysc_fields = &omap_hwmod_sysc_type1,
769 static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
771 .sysc = &dra7xx_elm_sysc,
776 static struct omap_hwmod dra7xx_elm_hwmod = {
778 .class = &dra7xx_elm_hwmod_class,
779 .clkdm_name = "l4per_clkdm",
780 .main_clk = "l3_iclk_div",
783 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
784 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
794 static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
798 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
799 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
800 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
801 .sysc_fields = &omap_hwmod_sysc_type1,
804 static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
806 .sysc = &dra7xx_gpmc_sysc,
811 static struct omap_hwmod dra7xx_gpmc_hwmod = {
813 .class = &dra7xx_gpmc_hwmod_class,
814 .clkdm_name = "l3main1_clkdm",
815 /* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
816 .flags = DEBUG_OMAP_GPMC_HWMOD_FLAGS,
817 .main_clk = "l3_iclk_div",
820 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
821 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
822 .modulemode = MODULEMODE_HWCTRL,
832 static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
836 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
837 SYSS_HAS_RESET_STATUS),
838 .sysc_fields = &omap_hwmod_sysc_type1,
841 static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
843 .sysc = &dra7xx_hdq1w_sysc,
848 static struct omap_hwmod dra7xx_hdq1w_hwmod = {
850 .class = &dra7xx_hdq1w_hwmod_class,
851 .clkdm_name = "l4per_clkdm",
852 .flags = HWMOD_INIT_NO_RESET,
853 .main_clk = "func_12m_fclk",
856 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
857 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
858 .modulemode = MODULEMODE_SWCTRL,
868 static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
871 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
873 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
874 .sysc_fields = &omap_hwmod_sysc_type2,
877 static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
879 .sysc = &dra7xx_mailbox_sysc,
883 static struct omap_hwmod dra7xx_mailbox1_hwmod = {
885 .class = &dra7xx_mailbox_hwmod_class,
886 .clkdm_name = "l4cfg_clkdm",
889 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
890 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
896 static struct omap_hwmod dra7xx_mailbox2_hwmod = {
898 .class = &dra7xx_mailbox_hwmod_class,
899 .clkdm_name = "l4cfg_clkdm",
902 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
903 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
909 static struct omap_hwmod dra7xx_mailbox3_hwmod = {
911 .class = &dra7xx_mailbox_hwmod_class,
912 .clkdm_name = "l4cfg_clkdm",
915 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
916 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
922 static struct omap_hwmod dra7xx_mailbox4_hwmod = {
924 .class = &dra7xx_mailbox_hwmod_class,
925 .clkdm_name = "l4cfg_clkdm",
928 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
929 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
935 static struct omap_hwmod dra7xx_mailbox5_hwmod = {
937 .class = &dra7xx_mailbox_hwmod_class,
938 .clkdm_name = "l4cfg_clkdm",
941 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
942 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
948 static struct omap_hwmod dra7xx_mailbox6_hwmod = {
950 .class = &dra7xx_mailbox_hwmod_class,
951 .clkdm_name = "l4cfg_clkdm",
954 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
955 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
961 static struct omap_hwmod dra7xx_mailbox7_hwmod = {
963 .class = &dra7xx_mailbox_hwmod_class,
964 .clkdm_name = "l4cfg_clkdm",
967 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
968 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
974 static struct omap_hwmod dra7xx_mailbox8_hwmod = {
976 .class = &dra7xx_mailbox_hwmod_class,
977 .clkdm_name = "l4cfg_clkdm",
980 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
981 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
987 static struct omap_hwmod dra7xx_mailbox9_hwmod = {
989 .class = &dra7xx_mailbox_hwmod_class,
990 .clkdm_name = "l4cfg_clkdm",
993 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
994 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1000 static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1001 .name = "mailbox10",
1002 .class = &dra7xx_mailbox_hwmod_class,
1003 .clkdm_name = "l4cfg_clkdm",
1006 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1007 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1013 static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1014 .name = "mailbox11",
1015 .class = &dra7xx_mailbox_hwmod_class,
1016 .clkdm_name = "l4cfg_clkdm",
1019 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1020 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1026 static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1027 .name = "mailbox12",
1028 .class = &dra7xx_mailbox_hwmod_class,
1029 .clkdm_name = "l4cfg_clkdm",
1032 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1033 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1039 static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1040 .name = "mailbox13",
1041 .class = &dra7xx_mailbox_hwmod_class,
1042 .clkdm_name = "l4cfg_clkdm",
1045 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1046 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1056 static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
1058 .sysc_offs = 0x0010,
1059 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1060 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1061 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1063 .sysc_fields = &omap_hwmod_sysc_type2,
1066 static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
1068 .sysc = &dra7xx_mcspi_sysc,
1072 static struct omap_hwmod dra7xx_mcspi1_hwmod = {
1074 .class = &dra7xx_mcspi_hwmod_class,
1075 .clkdm_name = "l4per_clkdm",
1076 .main_clk = "func_48m_fclk",
1079 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1080 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1081 .modulemode = MODULEMODE_SWCTRL,
1087 static struct omap_hwmod dra7xx_mcspi2_hwmod = {
1089 .class = &dra7xx_mcspi_hwmod_class,
1090 .clkdm_name = "l4per_clkdm",
1091 .main_clk = "func_48m_fclk",
1094 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1095 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1096 .modulemode = MODULEMODE_SWCTRL,
1102 static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1104 .class = &dra7xx_mcspi_hwmod_class,
1105 .clkdm_name = "l4per_clkdm",
1106 .main_clk = "func_48m_fclk",
1109 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1110 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1111 .modulemode = MODULEMODE_SWCTRL,
1117 static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1119 .class = &dra7xx_mcspi_hwmod_class,
1120 .clkdm_name = "l4per_clkdm",
1121 .main_clk = "func_48m_fclk",
1124 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1125 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1126 .modulemode = MODULEMODE_SWCTRL,
1135 static struct omap_hwmod_class_sysconfig dra7xx_mcasp_sysc = {
1137 .sysc_offs = 0x0004,
1138 .sysc_flags = SYSC_HAS_SIDLEMODE,
1139 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1140 .sysc_fields = &omap_hwmod_sysc_type3,
1143 static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
1145 .sysc = &dra7xx_mcasp_sysc,
1149 static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1150 { .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1151 { .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1154 static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1156 .class = &dra7xx_mcasp_hwmod_class,
1157 .clkdm_name = "ipu_clkdm",
1158 .main_clk = "mcasp1_aux_gfclk_mux",
1159 .flags = HWMOD_OPT_CLKS_NEEDED,
1162 .clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1163 .context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1164 .modulemode = MODULEMODE_SWCTRL,
1167 .opt_clks = mcasp1_opt_clks,
1168 .opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks),
1172 static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1173 { .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1174 { .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1177 static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1179 .class = &dra7xx_mcasp_hwmod_class,
1180 .clkdm_name = "l4per2_clkdm",
1181 .main_clk = "mcasp2_aux_gfclk_mux",
1182 .flags = HWMOD_OPT_CLKS_NEEDED,
1185 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1186 .context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1187 .modulemode = MODULEMODE_SWCTRL,
1190 .opt_clks = mcasp2_opt_clks,
1191 .opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks),
1195 static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
1196 { .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
1199 static struct omap_hwmod dra7xx_mcasp3_hwmod = {
1201 .class = &dra7xx_mcasp_hwmod_class,
1202 .clkdm_name = "l4per2_clkdm",
1203 .main_clk = "mcasp3_aux_gfclk_mux",
1204 .flags = HWMOD_OPT_CLKS_NEEDED,
1207 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET,
1208 .context_offs = DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET,
1209 .modulemode = MODULEMODE_SWCTRL,
1212 .opt_clks = mcasp3_opt_clks,
1213 .opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
1217 static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1218 { .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1221 static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1223 .class = &dra7xx_mcasp_hwmod_class,
1224 .clkdm_name = "l4per2_clkdm",
1225 .main_clk = "mcasp4_aux_gfclk_mux",
1226 .flags = HWMOD_OPT_CLKS_NEEDED,
1229 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1230 .context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1231 .modulemode = MODULEMODE_SWCTRL,
1234 .opt_clks = mcasp4_opt_clks,
1235 .opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks),
1239 static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1240 { .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1243 static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1245 .class = &dra7xx_mcasp_hwmod_class,
1246 .clkdm_name = "l4per2_clkdm",
1247 .main_clk = "mcasp5_aux_gfclk_mux",
1248 .flags = HWMOD_OPT_CLKS_NEEDED,
1251 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1252 .context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1253 .modulemode = MODULEMODE_SWCTRL,
1256 .opt_clks = mcasp5_opt_clks,
1257 .opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks),
1261 static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1262 { .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1265 static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1267 .class = &dra7xx_mcasp_hwmod_class,
1268 .clkdm_name = "l4per2_clkdm",
1269 .main_clk = "mcasp6_aux_gfclk_mux",
1270 .flags = HWMOD_OPT_CLKS_NEEDED,
1273 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1274 .context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1275 .modulemode = MODULEMODE_SWCTRL,
1278 .opt_clks = mcasp6_opt_clks,
1279 .opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks),
1283 static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1284 { .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1287 static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1289 .class = &dra7xx_mcasp_hwmod_class,
1290 .clkdm_name = "l4per2_clkdm",
1291 .main_clk = "mcasp7_aux_gfclk_mux",
1292 .flags = HWMOD_OPT_CLKS_NEEDED,
1295 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1296 .context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1297 .modulemode = MODULEMODE_SWCTRL,
1300 .opt_clks = mcasp7_opt_clks,
1301 .opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks),
1305 static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1306 { .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1309 static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1311 .class = &dra7xx_mcasp_hwmod_class,
1312 .clkdm_name = "l4per2_clkdm",
1313 .main_clk = "mcasp8_aux_gfclk_mux",
1314 .flags = HWMOD_OPT_CLKS_NEEDED,
1317 .clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1318 .context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1319 .modulemode = MODULEMODE_SWCTRL,
1322 .opt_clks = mcasp8_opt_clks,
1323 .opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks),
1331 static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1336 static struct omap_hwmod dra7xx_mpu_hwmod = {
1338 .class = &dra7xx_mpu_hwmod_class,
1339 .clkdm_name = "mpu_clkdm",
1340 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1341 .main_clk = "dpll_mpu_m2_ck",
1344 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1345 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1355 static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1357 .sysc_offs = 0x0010,
1358 .syss_offs = 0x0014,
1359 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1360 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1361 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1362 .sysc_fields = &omap_hwmod_sysc_type1,
1365 static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1367 .sysc = &dra7xx_ocp2scp_sysc,
1371 static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1373 .class = &dra7xx_ocp2scp_hwmod_class,
1374 .clkdm_name = "l3init_clkdm",
1375 .main_clk = "l4_root_clk_div",
1378 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1379 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1380 .modulemode = MODULEMODE_HWCTRL,
1386 static struct omap_hwmod dra7xx_ocp2scp3_hwmod = {
1388 .class = &dra7xx_ocp2scp_hwmod_class,
1389 .clkdm_name = "l3init_clkdm",
1390 .main_clk = "l4_root_clk_div",
1393 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1394 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1395 .modulemode = MODULEMODE_HWCTRL,
1406 * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
1407 * functionality of OMAP HWMOD layer does not deassert the hardreset lines
1408 * associated with an IP automatically leaving the driver to handle that
1409 * by itself. This does not work for PCIeSS which needs the reset lines
1410 * deasserted for the driver to start accessing registers.
1412 * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
1413 * lines after asserting them.
1415 int dra7xx_pciess_reset(struct omap_hwmod *oh)
1419 for (i = 0; i < oh->rst_lines_cnt; i++) {
1420 omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
1421 omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
1427 static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
1429 .reset = dra7xx_pciess_reset,
1433 static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
1434 { .name = "pcie", .rst_shift = 0 },
1437 static struct omap_hwmod dra7xx_pciess1_hwmod = {
1439 .class = &dra7xx_pciess_hwmod_class,
1440 .clkdm_name = "pcie_clkdm",
1441 .rst_lines = dra7xx_pciess1_resets,
1442 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
1443 .main_clk = "l4_root_clk_div",
1446 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
1447 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1448 .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
1449 .modulemode = MODULEMODE_SWCTRL,
1455 static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
1456 { .name = "pcie", .rst_shift = 1 },
1460 static struct omap_hwmod dra7xx_pciess2_hwmod = {
1462 .class = &dra7xx_pciess_hwmod_class,
1463 .clkdm_name = "pcie_clkdm",
1464 .rst_lines = dra7xx_pciess2_resets,
1465 .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
1466 .main_clk = "l4_root_clk_div",
1469 .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
1470 .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
1471 .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
1472 .modulemode = MODULEMODE_SWCTRL,
1482 static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1484 .sysc_offs = 0x0010,
1485 .sysc_flags = SYSC_HAS_SIDLEMODE,
1486 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1488 .sysc_fields = &omap_hwmod_sysc_type2,
1491 static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1493 .sysc = &dra7xx_qspi_sysc,
1497 static struct omap_hwmod dra7xx_qspi_hwmod = {
1499 .class = &dra7xx_qspi_hwmod_class,
1500 .clkdm_name = "l4per2_clkdm",
1501 .main_clk = "qspi_gfclk_div",
1504 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1505 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1506 .modulemode = MODULEMODE_SWCTRL,
1515 static struct omap_hwmod_class_sysconfig dra7xx_rtcss_sysc = {
1517 .sysc_offs = 0x0078,
1518 .sysc_flags = SYSC_HAS_SIDLEMODE,
1519 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1521 .sysc_fields = &omap_hwmod_sysc_type3,
1524 static struct omap_hwmod_class dra7xx_rtcss_hwmod_class = {
1526 .sysc = &dra7xx_rtcss_sysc,
1527 .unlock = &omap_hwmod_rtc_unlock,
1528 .lock = &omap_hwmod_rtc_lock,
1532 static struct omap_hwmod dra7xx_rtcss_hwmod = {
1534 .class = &dra7xx_rtcss_hwmod_class,
1535 .clkdm_name = "rtc_clkdm",
1536 .main_clk = "sys_32k_ck",
1539 .clkctrl_offs = DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET,
1540 .context_offs = DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET,
1541 .modulemode = MODULEMODE_SWCTRL,
1551 static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1553 .sysc_offs = 0x0000,
1554 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1555 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1556 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1557 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1558 .sysc_fields = &omap_hwmod_sysc_type2,
1561 static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1563 .sysc = &dra7xx_sata_sysc,
1568 static struct omap_hwmod dra7xx_sata_hwmod = {
1570 .class = &dra7xx_sata_hwmod_class,
1571 .clkdm_name = "l3init_clkdm",
1572 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1573 .main_clk = "func_48m_fclk",
1577 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1578 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1579 .modulemode = MODULEMODE_SWCTRL,
1585 * 'smartreflex' class
1589 /* The IP is not compliant to type1 / type2 scheme */
1590 static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1591 .rev_offs = -ENODEV,
1592 .sysc_offs = 0x0038,
1593 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1594 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1596 .sysc_fields = &omap36xx_sr_sysc_fields,
1599 static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1600 .name = "smartreflex",
1601 .sysc = &dra7xx_smartreflex_sysc,
1604 /* smartreflex_core */
1605 /* smartreflex_core dev_attr */
1606 static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1607 .sensor_voltdm_name = "core",
1610 static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1611 .name = "smartreflex_core",
1612 .class = &dra7xx_smartreflex_hwmod_class,
1613 .clkdm_name = "coreaon_clkdm",
1614 .main_clk = "wkupaon_iclk_mux",
1617 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1618 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1619 .modulemode = MODULEMODE_SWCTRL,
1622 .dev_attr = &smartreflex_core_dev_attr,
1625 /* smartreflex_mpu */
1626 /* smartreflex_mpu dev_attr */
1627 static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1628 .sensor_voltdm_name = "mpu",
1631 static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1632 .name = "smartreflex_mpu",
1633 .class = &dra7xx_smartreflex_hwmod_class,
1634 .clkdm_name = "coreaon_clkdm",
1635 .main_clk = "wkupaon_iclk_mux",
1638 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1639 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1640 .modulemode = MODULEMODE_SWCTRL,
1643 .dev_attr = &smartreflex_mpu_dev_attr,
1651 static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1653 .sysc_offs = 0x0010,
1654 .syss_offs = 0x0014,
1655 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1656 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1657 SYSS_HAS_RESET_STATUS),
1658 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1659 .sysc_fields = &omap_hwmod_sysc_type1,
1662 static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1664 .sysc = &dra7xx_spinlock_sysc,
1668 static struct omap_hwmod dra7xx_spinlock_hwmod = {
1670 .class = &dra7xx_spinlock_hwmod_class,
1671 .clkdm_name = "l4cfg_clkdm",
1672 .main_clk = "l3_iclk_div",
1675 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1676 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1684 * This class contains several variants: ['timer_1ms', 'timer_secure',
1688 static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1690 .sysc_offs = 0x0010,
1691 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1692 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1693 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1695 .sysc_fields = &omap_hwmod_sysc_type2,
1698 static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1700 .sysc = &dra7xx_timer_1ms_sysc,
1703 static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1705 .sysc_offs = 0x0010,
1706 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1707 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1708 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1710 .sysc_fields = &omap_hwmod_sysc_type2,
1713 static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1715 .sysc = &dra7xx_timer_sysc,
1719 static struct omap_hwmod dra7xx_timer1_hwmod = {
1721 .class = &dra7xx_timer_1ms_hwmod_class,
1722 .clkdm_name = "wkupaon_clkdm",
1723 .main_clk = "timer1_gfclk_mux",
1726 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1727 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1728 .modulemode = MODULEMODE_SWCTRL,
1734 static struct omap_hwmod dra7xx_timer2_hwmod = {
1736 .class = &dra7xx_timer_1ms_hwmod_class,
1737 .clkdm_name = "l4per_clkdm",
1738 .main_clk = "timer2_gfclk_mux",
1741 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1742 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1743 .modulemode = MODULEMODE_SWCTRL,
1749 static struct omap_hwmod dra7xx_timer3_hwmod = {
1751 .class = &dra7xx_timer_hwmod_class,
1752 .clkdm_name = "l4per_clkdm",
1753 .main_clk = "timer3_gfclk_mux",
1756 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1757 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1758 .modulemode = MODULEMODE_SWCTRL,
1764 static struct omap_hwmod dra7xx_timer4_hwmod = {
1766 .class = &dra7xx_timer_hwmod_class,
1767 .clkdm_name = "l4per_clkdm",
1768 .main_clk = "timer4_gfclk_mux",
1771 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1772 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1773 .modulemode = MODULEMODE_SWCTRL,
1779 static struct omap_hwmod dra7xx_timer5_hwmod = {
1781 .class = &dra7xx_timer_hwmod_class,
1782 .clkdm_name = "ipu_clkdm",
1783 .main_clk = "timer5_gfclk_mux",
1786 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1787 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1788 .modulemode = MODULEMODE_SWCTRL,
1794 static struct omap_hwmod dra7xx_timer6_hwmod = {
1796 .class = &dra7xx_timer_hwmod_class,
1797 .clkdm_name = "ipu_clkdm",
1798 .main_clk = "timer6_gfclk_mux",
1801 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1802 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1803 .modulemode = MODULEMODE_SWCTRL,
1809 static struct omap_hwmod dra7xx_timer7_hwmod = {
1811 .class = &dra7xx_timer_hwmod_class,
1812 .clkdm_name = "ipu_clkdm",
1813 .main_clk = "timer7_gfclk_mux",
1816 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1817 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1818 .modulemode = MODULEMODE_SWCTRL,
1824 static struct omap_hwmod dra7xx_timer8_hwmod = {
1826 .class = &dra7xx_timer_hwmod_class,
1827 .clkdm_name = "ipu_clkdm",
1828 .main_clk = "timer8_gfclk_mux",
1831 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1832 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1833 .modulemode = MODULEMODE_SWCTRL,
1839 static struct omap_hwmod dra7xx_timer9_hwmod = {
1841 .class = &dra7xx_timer_hwmod_class,
1842 .clkdm_name = "l4per_clkdm",
1843 .main_clk = "timer9_gfclk_mux",
1846 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1847 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1848 .modulemode = MODULEMODE_SWCTRL,
1854 static struct omap_hwmod dra7xx_timer10_hwmod = {
1856 .class = &dra7xx_timer_1ms_hwmod_class,
1857 .clkdm_name = "l4per_clkdm",
1858 .main_clk = "timer10_gfclk_mux",
1861 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1862 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1863 .modulemode = MODULEMODE_SWCTRL,
1869 static struct omap_hwmod dra7xx_timer11_hwmod = {
1871 .class = &dra7xx_timer_hwmod_class,
1872 .clkdm_name = "l4per_clkdm",
1873 .main_clk = "timer11_gfclk_mux",
1876 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1877 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1878 .modulemode = MODULEMODE_SWCTRL,
1884 static struct omap_hwmod dra7xx_timer12_hwmod = {
1886 .class = &dra7xx_timer_hwmod_class,
1887 .clkdm_name = "wkupaon_clkdm",
1888 .main_clk = "secure_32k_clk_src_ck",
1891 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET,
1892 .context_offs = DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET,
1898 static struct omap_hwmod dra7xx_timer13_hwmod = {
1900 .class = &dra7xx_timer_hwmod_class,
1901 .clkdm_name = "l4per3_clkdm",
1902 .main_clk = "timer13_gfclk_mux",
1905 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET,
1906 .context_offs = DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET,
1907 .modulemode = MODULEMODE_SWCTRL,
1913 static struct omap_hwmod dra7xx_timer14_hwmod = {
1915 .class = &dra7xx_timer_hwmod_class,
1916 .clkdm_name = "l4per3_clkdm",
1917 .main_clk = "timer14_gfclk_mux",
1920 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET,
1921 .context_offs = DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET,
1922 .modulemode = MODULEMODE_SWCTRL,
1928 static struct omap_hwmod dra7xx_timer15_hwmod = {
1930 .class = &dra7xx_timer_hwmod_class,
1931 .clkdm_name = "l4per3_clkdm",
1932 .main_clk = "timer15_gfclk_mux",
1935 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET,
1936 .context_offs = DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET,
1937 .modulemode = MODULEMODE_SWCTRL,
1943 static struct omap_hwmod dra7xx_timer16_hwmod = {
1945 .class = &dra7xx_timer_hwmod_class,
1946 .clkdm_name = "l4per3_clkdm",
1947 .main_clk = "timer16_gfclk_mux",
1950 .clkctrl_offs = DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET,
1951 .context_offs = DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET,
1952 .modulemode = MODULEMODE_SWCTRL,
1957 /* DES (the 'P' (public) device) */
1958 static struct omap_hwmod_class_sysconfig dra7xx_des_sysc = {
1960 .sysc_offs = 0x0034,
1961 .syss_offs = 0x0038,
1962 .sysc_flags = SYSS_HAS_RESET_STATUS,
1965 static struct omap_hwmod_class dra7xx_des_hwmod_class = {
1967 .sysc = &dra7xx_des_sysc,
1971 static struct omap_hwmod dra7xx_des_hwmod = {
1973 .class = &dra7xx_des_hwmod_class,
1974 .clkdm_name = "l4sec_clkdm",
1975 .main_clk = "l3_iclk_div",
1978 .clkctrl_offs = DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
1979 .context_offs = DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
1980 .modulemode = MODULEMODE_HWCTRL,
1986 static struct omap_hwmod_class_sysconfig dra7xx_rng_sysc = {
1988 .sysc_offs = 0x1fe4,
1989 .sysc_flags = SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE,
1990 .idlemodes = SIDLE_FORCE | SIDLE_NO,
1991 .sysc_fields = &omap_hwmod_sysc_type1,
1994 static struct omap_hwmod_class dra7xx_rng_hwmod_class = {
1996 .sysc = &dra7xx_rng_sysc,
1999 static struct omap_hwmod dra7xx_rng_hwmod = {
2001 .class = &dra7xx_rng_hwmod_class,
2002 .flags = HWMOD_SWSUP_SIDLE,
2003 .clkdm_name = "l4sec_clkdm",
2006 .clkctrl_offs = DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET,
2007 .context_offs = DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET,
2008 .modulemode = MODULEMODE_HWCTRL,
2014 * 'usb_otg_ss' class
2018 static struct omap_hwmod_class_sysconfig dra7xx_usb_otg_ss_sysc = {
2020 .sysc_offs = 0x0010,
2021 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
2022 SYSC_HAS_SIDLEMODE),
2023 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2024 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2025 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2026 .sysc_fields = &omap_hwmod_sysc_type2,
2029 static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
2030 .name = "usb_otg_ss",
2031 .sysc = &dra7xx_usb_otg_ss_sysc,
2035 static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
2036 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
2039 static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
2040 .name = "usb_otg_ss1",
2041 .class = &dra7xx_usb_otg_ss_hwmod_class,
2042 .clkdm_name = "l3init_clkdm",
2043 .main_clk = "dpll_core_h13x2_ck",
2044 .flags = HWMOD_CLKDM_NOAUTO,
2047 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
2048 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
2049 .modulemode = MODULEMODE_HWCTRL,
2052 .opt_clks = usb_otg_ss1_opt_clks,
2053 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
2057 static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
2058 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
2061 static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
2062 .name = "usb_otg_ss2",
2063 .class = &dra7xx_usb_otg_ss_hwmod_class,
2064 .clkdm_name = "l3init_clkdm",
2065 .main_clk = "dpll_core_h13x2_ck",
2066 .flags = HWMOD_CLKDM_NOAUTO,
2069 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
2070 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
2071 .modulemode = MODULEMODE_HWCTRL,
2074 .opt_clks = usb_otg_ss2_opt_clks,
2075 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
2079 static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
2080 .name = "usb_otg_ss3",
2081 .class = &dra7xx_usb_otg_ss_hwmod_class,
2082 .clkdm_name = "l3init_clkdm",
2083 .main_clk = "dpll_core_h13x2_ck",
2086 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
2087 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
2088 .modulemode = MODULEMODE_HWCTRL,
2094 static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
2095 .name = "usb_otg_ss4",
2096 .class = &dra7xx_usb_otg_ss_hwmod_class,
2097 .clkdm_name = "l3init_clkdm",
2098 .main_clk = "dpll_core_h13x2_ck",
2101 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
2102 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
2103 .modulemode = MODULEMODE_HWCTRL,
2113 static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
2118 static struct omap_hwmod dra7xx_vcp1_hwmod = {
2120 .class = &dra7xx_vcp_hwmod_class,
2121 .clkdm_name = "l3main1_clkdm",
2122 .main_clk = "l3_iclk_div",
2125 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
2126 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
2132 static struct omap_hwmod dra7xx_vcp2_hwmod = {
2134 .class = &dra7xx_vcp_hwmod_class,
2135 .clkdm_name = "l3main1_clkdm",
2136 .main_clk = "l3_iclk_div",
2139 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
2140 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
2150 static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
2152 .sysc_offs = 0x0010,
2153 .syss_offs = 0x0014,
2154 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2155 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2156 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2158 .sysc_fields = &omap_hwmod_sysc_type1,
2161 static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
2163 .sysc = &dra7xx_wd_timer_sysc,
2164 .pre_shutdown = &omap2_wd_timer_disable,
2165 .reset = &omap2_wd_timer_reset,
2169 static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
2170 .name = "wd_timer2",
2171 .class = &dra7xx_wd_timer_hwmod_class,
2172 .clkdm_name = "wkupaon_clkdm",
2173 .main_clk = "sys_32k_ck",
2176 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
2177 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
2178 .modulemode = MODULEMODE_SWCTRL,
2188 /* l3_main_1 -> dmm */
2189 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
2190 .master = &dra7xx_l3_main_1_hwmod,
2191 .slave = &dra7xx_dmm_hwmod,
2192 .clk = "l3_iclk_div",
2193 .user = OCP_USER_SDMA,
2196 /* l3_main_2 -> l3_instr */
2197 static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
2198 .master = &dra7xx_l3_main_2_hwmod,
2199 .slave = &dra7xx_l3_instr_hwmod,
2200 .clk = "l3_iclk_div",
2201 .user = OCP_USER_MPU | OCP_USER_SDMA,
2204 /* l4_cfg -> l3_main_1 */
2205 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
2206 .master = &dra7xx_l4_cfg_hwmod,
2207 .slave = &dra7xx_l3_main_1_hwmod,
2208 .clk = "l3_iclk_div",
2209 .user = OCP_USER_MPU | OCP_USER_SDMA,
2212 /* mpu -> l3_main_1 */
2213 static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
2214 .master = &dra7xx_mpu_hwmod,
2215 .slave = &dra7xx_l3_main_1_hwmod,
2216 .clk = "l3_iclk_div",
2217 .user = OCP_USER_MPU,
2220 /* l3_main_1 -> l3_main_2 */
2221 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
2222 .master = &dra7xx_l3_main_1_hwmod,
2223 .slave = &dra7xx_l3_main_2_hwmod,
2224 .clk = "l3_iclk_div",
2225 .user = OCP_USER_MPU,
2228 /* l4_cfg -> l3_main_2 */
2229 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
2230 .master = &dra7xx_l4_cfg_hwmod,
2231 .slave = &dra7xx_l3_main_2_hwmod,
2232 .clk = "l3_iclk_div",
2233 .user = OCP_USER_MPU | OCP_USER_SDMA,
2236 /* l3_main_1 -> l4_cfg */
2237 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
2238 .master = &dra7xx_l3_main_1_hwmod,
2239 .slave = &dra7xx_l4_cfg_hwmod,
2240 .clk = "l3_iclk_div",
2241 .user = OCP_USER_MPU | OCP_USER_SDMA,
2244 /* l3_main_1 -> l4_per1 */
2245 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
2246 .master = &dra7xx_l3_main_1_hwmod,
2247 .slave = &dra7xx_l4_per1_hwmod,
2248 .clk = "l3_iclk_div",
2249 .user = OCP_USER_MPU | OCP_USER_SDMA,
2252 /* l3_main_1 -> l4_per2 */
2253 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
2254 .master = &dra7xx_l3_main_1_hwmod,
2255 .slave = &dra7xx_l4_per2_hwmod,
2256 .clk = "l3_iclk_div",
2257 .user = OCP_USER_MPU | OCP_USER_SDMA,
2260 /* l3_main_1 -> l4_per3 */
2261 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
2262 .master = &dra7xx_l3_main_1_hwmod,
2263 .slave = &dra7xx_l4_per3_hwmod,
2264 .clk = "l3_iclk_div",
2265 .user = OCP_USER_MPU | OCP_USER_SDMA,
2268 /* l3_main_1 -> l4_wkup */
2269 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
2270 .master = &dra7xx_l3_main_1_hwmod,
2271 .slave = &dra7xx_l4_wkup_hwmod,
2272 .clk = "wkupaon_iclk_mux",
2273 .user = OCP_USER_MPU | OCP_USER_SDMA,
2276 /* l4_per2 -> atl */
2277 static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
2278 .master = &dra7xx_l4_per2_hwmod,
2279 .slave = &dra7xx_atl_hwmod,
2280 .clk = "l3_iclk_div",
2281 .user = OCP_USER_MPU | OCP_USER_SDMA,
2284 /* l3_main_1 -> bb2d */
2285 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
2286 .master = &dra7xx_l3_main_1_hwmod,
2287 .slave = &dra7xx_bb2d_hwmod,
2288 .clk = "l3_iclk_div",
2289 .user = OCP_USER_MPU | OCP_USER_SDMA,
2292 /* l4_wkup -> counter_32k */
2293 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
2294 .master = &dra7xx_l4_wkup_hwmod,
2295 .slave = &dra7xx_counter_32k_hwmod,
2296 .clk = "wkupaon_iclk_mux",
2297 .user = OCP_USER_MPU | OCP_USER_SDMA,
2300 /* l4_wkup -> ctrl_module_wkup */
2301 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
2302 .master = &dra7xx_l4_wkup_hwmod,
2303 .slave = &dra7xx_ctrl_module_wkup_hwmod,
2304 .clk = "wkupaon_iclk_mux",
2305 .user = OCP_USER_MPU | OCP_USER_SDMA,
2308 static struct omap_hwmod_ocp_if dra7xx_l4_per2__cpgmac0 = {
2309 .master = &dra7xx_l4_per2_hwmod,
2310 .slave = &dra7xx_gmac_hwmod,
2311 .clk = "dpll_gmac_ck",
2312 .user = OCP_USER_MPU,
2315 static struct omap_hwmod_ocp_if dra7xx_gmac__mdio = {
2316 .master = &dra7xx_gmac_hwmod,
2317 .slave = &dra7xx_mdio_hwmod,
2318 .user = OCP_USER_MPU,
2321 /* l4_wkup -> dcan1 */
2322 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2323 .master = &dra7xx_l4_wkup_hwmod,
2324 .slave = &dra7xx_dcan1_hwmod,
2325 .clk = "wkupaon_iclk_mux",
2326 .user = OCP_USER_MPU | OCP_USER_SDMA,
2329 /* l4_per2 -> dcan2 */
2330 static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2331 .master = &dra7xx_l4_per2_hwmod,
2332 .slave = &dra7xx_dcan2_hwmod,
2333 .clk = "l3_iclk_div",
2334 .user = OCP_USER_MPU | OCP_USER_SDMA,
2337 /* l4_cfg -> dma_system */
2338 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2339 .master = &dra7xx_l4_cfg_hwmod,
2340 .slave = &dra7xx_dma_system_hwmod,
2341 .clk = "l3_iclk_div",
2342 .user = OCP_USER_MPU | OCP_USER_SDMA,
2345 /* l3_main_1 -> tpcc */
2346 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tpcc = {
2347 .master = &dra7xx_l3_main_1_hwmod,
2348 .slave = &dra7xx_tpcc_hwmod,
2349 .clk = "l3_iclk_div",
2350 .user = OCP_USER_MPU,
2353 /* l3_main_1 -> tptc0 */
2354 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc0 = {
2355 .master = &dra7xx_l3_main_1_hwmod,
2356 .slave = &dra7xx_tptc0_hwmod,
2357 .clk = "l3_iclk_div",
2358 .user = OCP_USER_MPU,
2361 /* l3_main_1 -> tptc1 */
2362 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__tptc1 = {
2363 .master = &dra7xx_l3_main_1_hwmod,
2364 .slave = &dra7xx_tptc1_hwmod,
2365 .clk = "l3_iclk_div",
2366 .user = OCP_USER_MPU,
2369 /* l3_main_1 -> dss */
2370 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2371 .master = &dra7xx_l3_main_1_hwmod,
2372 .slave = &dra7xx_dss_hwmod,
2373 .clk = "l3_iclk_div",
2374 .user = OCP_USER_MPU | OCP_USER_SDMA,
2377 /* l3_main_1 -> dispc */
2378 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2379 .master = &dra7xx_l3_main_1_hwmod,
2380 .slave = &dra7xx_dss_dispc_hwmod,
2381 .clk = "l3_iclk_div",
2382 .user = OCP_USER_MPU | OCP_USER_SDMA,
2385 /* l3_main_1 -> dispc */
2386 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2387 .master = &dra7xx_l3_main_1_hwmod,
2388 .slave = &dra7xx_dss_hdmi_hwmod,
2389 .clk = "l3_iclk_div",
2390 .user = OCP_USER_MPU | OCP_USER_SDMA,
2393 /* l3_main_1 -> aes1 */
2394 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes1 = {
2395 .master = &dra7xx_l3_main_1_hwmod,
2396 .slave = &dra7xx_aes1_hwmod,
2397 .clk = "l3_iclk_div",
2398 .user = OCP_USER_MPU | OCP_USER_SDMA,
2401 /* l3_main_1 -> aes2 */
2402 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__aes2 = {
2403 .master = &dra7xx_l3_main_1_hwmod,
2404 .slave = &dra7xx_aes2_hwmod,
2405 .clk = "l3_iclk_div",
2406 .user = OCP_USER_MPU | OCP_USER_SDMA,
2409 /* l3_main_1 -> sha0 */
2410 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__sha0 = {
2411 .master = &dra7xx_l3_main_1_hwmod,
2412 .slave = &dra7xx_sha0_hwmod,
2413 .clk = "l3_iclk_div",
2414 .user = OCP_USER_MPU | OCP_USER_SDMA,
2417 /* l4_per2 -> mcasp1 */
2418 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
2419 .master = &dra7xx_l4_per2_hwmod,
2420 .slave = &dra7xx_mcasp1_hwmod,
2421 .clk = "l4_root_clk_div",
2422 .user = OCP_USER_MPU | OCP_USER_SDMA,
2425 /* l3_main_1 -> mcasp1 */
2426 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
2427 .master = &dra7xx_l3_main_1_hwmod,
2428 .slave = &dra7xx_mcasp1_hwmod,
2429 .clk = "l3_iclk_div",
2430 .user = OCP_USER_MPU | OCP_USER_SDMA,
2433 /* l4_per2 -> mcasp2 */
2434 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
2435 .master = &dra7xx_l4_per2_hwmod,
2436 .slave = &dra7xx_mcasp2_hwmod,
2437 .clk = "l4_root_clk_div",
2438 .user = OCP_USER_MPU | OCP_USER_SDMA,
2441 /* l3_main_1 -> mcasp2 */
2442 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
2443 .master = &dra7xx_l3_main_1_hwmod,
2444 .slave = &dra7xx_mcasp2_hwmod,
2445 .clk = "l3_iclk_div",
2446 .user = OCP_USER_MPU | OCP_USER_SDMA,
2449 /* l4_per2 -> mcasp3 */
2450 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
2451 .master = &dra7xx_l4_per2_hwmod,
2452 .slave = &dra7xx_mcasp3_hwmod,
2453 .clk = "l4_root_clk_div",
2454 .user = OCP_USER_MPU | OCP_USER_SDMA,
2457 /* l3_main_1 -> mcasp3 */
2458 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
2459 .master = &dra7xx_l3_main_1_hwmod,
2460 .slave = &dra7xx_mcasp3_hwmod,
2461 .clk = "l3_iclk_div",
2462 .user = OCP_USER_MPU | OCP_USER_SDMA,
2465 /* l4_per2 -> mcasp4 */
2466 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
2467 .master = &dra7xx_l4_per2_hwmod,
2468 .slave = &dra7xx_mcasp4_hwmod,
2469 .clk = "l4_root_clk_div",
2470 .user = OCP_USER_MPU | OCP_USER_SDMA,
2473 /* l4_per2 -> mcasp5 */
2474 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
2475 .master = &dra7xx_l4_per2_hwmod,
2476 .slave = &dra7xx_mcasp5_hwmod,
2477 .clk = "l4_root_clk_div",
2478 .user = OCP_USER_MPU | OCP_USER_SDMA,
2481 /* l4_per2 -> mcasp6 */
2482 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
2483 .master = &dra7xx_l4_per2_hwmod,
2484 .slave = &dra7xx_mcasp6_hwmod,
2485 .clk = "l4_root_clk_div",
2486 .user = OCP_USER_MPU | OCP_USER_SDMA,
2489 /* l4_per2 -> mcasp7 */
2490 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
2491 .master = &dra7xx_l4_per2_hwmod,
2492 .slave = &dra7xx_mcasp7_hwmod,
2493 .clk = "l4_root_clk_div",
2494 .user = OCP_USER_MPU | OCP_USER_SDMA,
2497 /* l4_per2 -> mcasp8 */
2498 static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
2499 .master = &dra7xx_l4_per2_hwmod,
2500 .slave = &dra7xx_mcasp8_hwmod,
2501 .clk = "l4_root_clk_div",
2502 .user = OCP_USER_MPU | OCP_USER_SDMA,
2505 /* l4_per1 -> elm */
2506 static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2507 .master = &dra7xx_l4_per1_hwmod,
2508 .slave = &dra7xx_elm_hwmod,
2509 .clk = "l3_iclk_div",
2510 .user = OCP_USER_MPU | OCP_USER_SDMA,
2513 /* l3_main_1 -> gpmc */
2514 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2515 .master = &dra7xx_l3_main_1_hwmod,
2516 .slave = &dra7xx_gpmc_hwmod,
2517 .clk = "l3_iclk_div",
2518 .user = OCP_USER_MPU | OCP_USER_SDMA,
2521 /* l4_per1 -> hdq1w */
2522 static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2523 .master = &dra7xx_l4_per1_hwmod,
2524 .slave = &dra7xx_hdq1w_hwmod,
2525 .clk = "l3_iclk_div",
2526 .user = OCP_USER_MPU | OCP_USER_SDMA,
2529 /* l4_cfg -> mailbox1 */
2530 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2531 .master = &dra7xx_l4_cfg_hwmod,
2532 .slave = &dra7xx_mailbox1_hwmod,
2533 .clk = "l3_iclk_div",
2534 .user = OCP_USER_MPU | OCP_USER_SDMA,
2537 /* l4_per3 -> mailbox2 */
2538 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2539 .master = &dra7xx_l4_per3_hwmod,
2540 .slave = &dra7xx_mailbox2_hwmod,
2541 .clk = "l3_iclk_div",
2542 .user = OCP_USER_MPU | OCP_USER_SDMA,
2545 /* l4_per3 -> mailbox3 */
2546 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2547 .master = &dra7xx_l4_per3_hwmod,
2548 .slave = &dra7xx_mailbox3_hwmod,
2549 .clk = "l3_iclk_div",
2550 .user = OCP_USER_MPU | OCP_USER_SDMA,
2553 /* l4_per3 -> mailbox4 */
2554 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2555 .master = &dra7xx_l4_per3_hwmod,
2556 .slave = &dra7xx_mailbox4_hwmod,
2557 .clk = "l3_iclk_div",
2558 .user = OCP_USER_MPU | OCP_USER_SDMA,
2561 /* l4_per3 -> mailbox5 */
2562 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2563 .master = &dra7xx_l4_per3_hwmod,
2564 .slave = &dra7xx_mailbox5_hwmod,
2565 .clk = "l3_iclk_div",
2566 .user = OCP_USER_MPU | OCP_USER_SDMA,
2569 /* l4_per3 -> mailbox6 */
2570 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2571 .master = &dra7xx_l4_per3_hwmod,
2572 .slave = &dra7xx_mailbox6_hwmod,
2573 .clk = "l3_iclk_div",
2574 .user = OCP_USER_MPU | OCP_USER_SDMA,
2577 /* l4_per3 -> mailbox7 */
2578 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2579 .master = &dra7xx_l4_per3_hwmod,
2580 .slave = &dra7xx_mailbox7_hwmod,
2581 .clk = "l3_iclk_div",
2582 .user = OCP_USER_MPU | OCP_USER_SDMA,
2585 /* l4_per3 -> mailbox8 */
2586 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2587 .master = &dra7xx_l4_per3_hwmod,
2588 .slave = &dra7xx_mailbox8_hwmod,
2589 .clk = "l3_iclk_div",
2590 .user = OCP_USER_MPU | OCP_USER_SDMA,
2593 /* l4_per3 -> mailbox9 */
2594 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2595 .master = &dra7xx_l4_per3_hwmod,
2596 .slave = &dra7xx_mailbox9_hwmod,
2597 .clk = "l3_iclk_div",
2598 .user = OCP_USER_MPU | OCP_USER_SDMA,
2601 /* l4_per3 -> mailbox10 */
2602 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2603 .master = &dra7xx_l4_per3_hwmod,
2604 .slave = &dra7xx_mailbox10_hwmod,
2605 .clk = "l3_iclk_div",
2606 .user = OCP_USER_MPU | OCP_USER_SDMA,
2609 /* l4_per3 -> mailbox11 */
2610 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2611 .master = &dra7xx_l4_per3_hwmod,
2612 .slave = &dra7xx_mailbox11_hwmod,
2613 .clk = "l3_iclk_div",
2614 .user = OCP_USER_MPU | OCP_USER_SDMA,
2617 /* l4_per3 -> mailbox12 */
2618 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2619 .master = &dra7xx_l4_per3_hwmod,
2620 .slave = &dra7xx_mailbox12_hwmod,
2621 .clk = "l3_iclk_div",
2622 .user = OCP_USER_MPU | OCP_USER_SDMA,
2625 /* l4_per3 -> mailbox13 */
2626 static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2627 .master = &dra7xx_l4_per3_hwmod,
2628 .slave = &dra7xx_mailbox13_hwmod,
2629 .clk = "l3_iclk_div",
2630 .user = OCP_USER_MPU | OCP_USER_SDMA,
2633 /* l4_per1 -> mcspi1 */
2634 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2635 .master = &dra7xx_l4_per1_hwmod,
2636 .slave = &dra7xx_mcspi1_hwmod,
2637 .clk = "l3_iclk_div",
2638 .user = OCP_USER_MPU | OCP_USER_SDMA,
2641 /* l4_per1 -> mcspi2 */
2642 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2643 .master = &dra7xx_l4_per1_hwmod,
2644 .slave = &dra7xx_mcspi2_hwmod,
2645 .clk = "l3_iclk_div",
2646 .user = OCP_USER_MPU | OCP_USER_SDMA,
2649 /* l4_per1 -> mcspi3 */
2650 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2651 .master = &dra7xx_l4_per1_hwmod,
2652 .slave = &dra7xx_mcspi3_hwmod,
2653 .clk = "l3_iclk_div",
2654 .user = OCP_USER_MPU | OCP_USER_SDMA,
2657 /* l4_per1 -> mcspi4 */
2658 static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2659 .master = &dra7xx_l4_per1_hwmod,
2660 .slave = &dra7xx_mcspi4_hwmod,
2661 .clk = "l3_iclk_div",
2662 .user = OCP_USER_MPU | OCP_USER_SDMA,
2666 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2667 .master = &dra7xx_l4_cfg_hwmod,
2668 .slave = &dra7xx_mpu_hwmod,
2669 .clk = "l3_iclk_div",
2670 .user = OCP_USER_MPU | OCP_USER_SDMA,
2673 /* l4_cfg -> ocp2scp1 */
2674 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2675 .master = &dra7xx_l4_cfg_hwmod,
2676 .slave = &dra7xx_ocp2scp1_hwmod,
2677 .clk = "l4_root_clk_div",
2678 .user = OCP_USER_MPU | OCP_USER_SDMA,
2681 /* l4_cfg -> ocp2scp3 */
2682 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp3 = {
2683 .master = &dra7xx_l4_cfg_hwmod,
2684 .slave = &dra7xx_ocp2scp3_hwmod,
2685 .clk = "l4_root_clk_div",
2686 .user = OCP_USER_MPU | OCP_USER_SDMA,
2689 /* l3_main_1 -> pciess1 */
2690 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
2691 .master = &dra7xx_l3_main_1_hwmod,
2692 .slave = &dra7xx_pciess1_hwmod,
2693 .clk = "l3_iclk_div",
2694 .user = OCP_USER_MPU | OCP_USER_SDMA,
2697 /* l4_cfg -> pciess1 */
2698 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
2699 .master = &dra7xx_l4_cfg_hwmod,
2700 .slave = &dra7xx_pciess1_hwmod,
2701 .clk = "l4_root_clk_div",
2702 .user = OCP_USER_MPU | OCP_USER_SDMA,
2705 /* l3_main_1 -> pciess2 */
2706 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
2707 .master = &dra7xx_l3_main_1_hwmod,
2708 .slave = &dra7xx_pciess2_hwmod,
2709 .clk = "l3_iclk_div",
2710 .user = OCP_USER_MPU | OCP_USER_SDMA,
2713 /* l4_cfg -> pciess2 */
2714 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
2715 .master = &dra7xx_l4_cfg_hwmod,
2716 .slave = &dra7xx_pciess2_hwmod,
2717 .clk = "l4_root_clk_div",
2718 .user = OCP_USER_MPU | OCP_USER_SDMA,
2721 /* l3_main_1 -> qspi */
2722 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2723 .master = &dra7xx_l3_main_1_hwmod,
2724 .slave = &dra7xx_qspi_hwmod,
2725 .clk = "l3_iclk_div",
2726 .user = OCP_USER_MPU | OCP_USER_SDMA,
2729 /* l4_per3 -> rtcss */
2730 static struct omap_hwmod_ocp_if dra7xx_l4_per3__rtcss = {
2731 .master = &dra7xx_l4_per3_hwmod,
2732 .slave = &dra7xx_rtcss_hwmod,
2733 .clk = "l4_root_clk_div",
2734 .user = OCP_USER_MPU | OCP_USER_SDMA,
2737 /* l4_cfg -> sata */
2738 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2739 .master = &dra7xx_l4_cfg_hwmod,
2740 .slave = &dra7xx_sata_hwmod,
2741 .clk = "l3_iclk_div",
2742 .user = OCP_USER_MPU | OCP_USER_SDMA,
2745 /* l4_cfg -> smartreflex_core */
2746 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2747 .master = &dra7xx_l4_cfg_hwmod,
2748 .slave = &dra7xx_smartreflex_core_hwmod,
2749 .clk = "l4_root_clk_div",
2750 .user = OCP_USER_MPU | OCP_USER_SDMA,
2753 /* l4_cfg -> smartreflex_mpu */
2754 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2755 .master = &dra7xx_l4_cfg_hwmod,
2756 .slave = &dra7xx_smartreflex_mpu_hwmod,
2757 .clk = "l4_root_clk_div",
2758 .user = OCP_USER_MPU | OCP_USER_SDMA,
2761 /* l4_cfg -> spinlock */
2762 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2763 .master = &dra7xx_l4_cfg_hwmod,
2764 .slave = &dra7xx_spinlock_hwmod,
2765 .clk = "l3_iclk_div",
2766 .user = OCP_USER_MPU | OCP_USER_SDMA,
2769 /* l4_wkup -> timer1 */
2770 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2771 .master = &dra7xx_l4_wkup_hwmod,
2772 .slave = &dra7xx_timer1_hwmod,
2773 .clk = "wkupaon_iclk_mux",
2774 .user = OCP_USER_MPU | OCP_USER_SDMA,
2777 /* l4_per1 -> timer2 */
2778 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2779 .master = &dra7xx_l4_per1_hwmod,
2780 .slave = &dra7xx_timer2_hwmod,
2781 .clk = "l3_iclk_div",
2782 .user = OCP_USER_MPU | OCP_USER_SDMA,
2785 /* l4_per1 -> timer3 */
2786 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2787 .master = &dra7xx_l4_per1_hwmod,
2788 .slave = &dra7xx_timer3_hwmod,
2789 .clk = "l3_iclk_div",
2790 .user = OCP_USER_MPU | OCP_USER_SDMA,
2793 /* l4_per1 -> timer4 */
2794 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2795 .master = &dra7xx_l4_per1_hwmod,
2796 .slave = &dra7xx_timer4_hwmod,
2797 .clk = "l3_iclk_div",
2798 .user = OCP_USER_MPU | OCP_USER_SDMA,
2801 /* l4_per3 -> timer5 */
2802 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2803 .master = &dra7xx_l4_per3_hwmod,
2804 .slave = &dra7xx_timer5_hwmod,
2805 .clk = "l3_iclk_div",
2806 .user = OCP_USER_MPU | OCP_USER_SDMA,
2809 /* l4_per3 -> timer6 */
2810 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
2811 .master = &dra7xx_l4_per3_hwmod,
2812 .slave = &dra7xx_timer6_hwmod,
2813 .clk = "l3_iclk_div",
2814 .user = OCP_USER_MPU | OCP_USER_SDMA,
2817 /* l4_per3 -> timer7 */
2818 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
2819 .master = &dra7xx_l4_per3_hwmod,
2820 .slave = &dra7xx_timer7_hwmod,
2821 .clk = "l3_iclk_div",
2822 .user = OCP_USER_MPU | OCP_USER_SDMA,
2825 /* l4_per3 -> timer8 */
2826 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
2827 .master = &dra7xx_l4_per3_hwmod,
2828 .slave = &dra7xx_timer8_hwmod,
2829 .clk = "l3_iclk_div",
2830 .user = OCP_USER_MPU | OCP_USER_SDMA,
2833 /* l4_per1 -> timer9 */
2834 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
2835 .master = &dra7xx_l4_per1_hwmod,
2836 .slave = &dra7xx_timer9_hwmod,
2837 .clk = "l3_iclk_div",
2838 .user = OCP_USER_MPU | OCP_USER_SDMA,
2841 /* l4_per1 -> timer10 */
2842 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
2843 .master = &dra7xx_l4_per1_hwmod,
2844 .slave = &dra7xx_timer10_hwmod,
2845 .clk = "l3_iclk_div",
2846 .user = OCP_USER_MPU | OCP_USER_SDMA,
2849 /* l4_per1 -> timer11 */
2850 static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
2851 .master = &dra7xx_l4_per1_hwmod,
2852 .slave = &dra7xx_timer11_hwmod,
2853 .clk = "l3_iclk_div",
2854 .user = OCP_USER_MPU | OCP_USER_SDMA,
2857 /* l4_wkup -> timer12 */
2858 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer12 = {
2859 .master = &dra7xx_l4_wkup_hwmod,
2860 .slave = &dra7xx_timer12_hwmod,
2861 .clk = "wkupaon_iclk_mux",
2862 .user = OCP_USER_MPU | OCP_USER_SDMA,
2865 /* l4_per3 -> timer13 */
2866 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer13 = {
2867 .master = &dra7xx_l4_per3_hwmod,
2868 .slave = &dra7xx_timer13_hwmod,
2869 .clk = "l3_iclk_div",
2870 .user = OCP_USER_MPU | OCP_USER_SDMA,
2873 /* l4_per3 -> timer14 */
2874 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer14 = {
2875 .master = &dra7xx_l4_per3_hwmod,
2876 .slave = &dra7xx_timer14_hwmod,
2877 .clk = "l3_iclk_div",
2878 .user = OCP_USER_MPU | OCP_USER_SDMA,
2881 /* l4_per3 -> timer15 */
2882 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer15 = {
2883 .master = &dra7xx_l4_per3_hwmod,
2884 .slave = &dra7xx_timer15_hwmod,
2885 .clk = "l3_iclk_div",
2886 .user = OCP_USER_MPU | OCP_USER_SDMA,
2889 /* l4_per3 -> timer16 */
2890 static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer16 = {
2891 .master = &dra7xx_l4_per3_hwmod,
2892 .slave = &dra7xx_timer16_hwmod,
2893 .clk = "l3_iclk_div",
2894 .user = OCP_USER_MPU | OCP_USER_SDMA,
2897 /* l4_per1 -> des */
2898 static struct omap_hwmod_ocp_if dra7xx_l4_per1__des = {
2899 .master = &dra7xx_l4_per1_hwmod,
2900 .slave = &dra7xx_des_hwmod,
2901 .clk = "l3_iclk_div",
2902 .user = OCP_USER_MPU | OCP_USER_SDMA,
2905 /* l4_per1 -> rng */
2906 static struct omap_hwmod_ocp_if dra7xx_l4_per1__rng = {
2907 .master = &dra7xx_l4_per1_hwmod,
2908 .slave = &dra7xx_rng_hwmod,
2909 .user = OCP_USER_MPU,
2912 /* l4_per3 -> usb_otg_ss1 */
2913 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
2914 .master = &dra7xx_l4_per3_hwmod,
2915 .slave = &dra7xx_usb_otg_ss1_hwmod,
2916 .clk = "dpll_core_h13x2_ck",
2917 .user = OCP_USER_MPU | OCP_USER_SDMA,
2920 /* l4_per3 -> usb_otg_ss2 */
2921 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
2922 .master = &dra7xx_l4_per3_hwmod,
2923 .slave = &dra7xx_usb_otg_ss2_hwmod,
2924 .clk = "dpll_core_h13x2_ck",
2925 .user = OCP_USER_MPU | OCP_USER_SDMA,
2928 /* l4_per3 -> usb_otg_ss3 */
2929 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
2930 .master = &dra7xx_l4_per3_hwmod,
2931 .slave = &dra7xx_usb_otg_ss3_hwmod,
2932 .clk = "dpll_core_h13x2_ck",
2933 .user = OCP_USER_MPU | OCP_USER_SDMA,
2936 /* l4_per3 -> usb_otg_ss4 */
2937 static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
2938 .master = &dra7xx_l4_per3_hwmod,
2939 .slave = &dra7xx_usb_otg_ss4_hwmod,
2940 .clk = "dpll_core_h13x2_ck",
2941 .user = OCP_USER_MPU | OCP_USER_SDMA,
2944 /* l3_main_1 -> vcp1 */
2945 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
2946 .master = &dra7xx_l3_main_1_hwmod,
2947 .slave = &dra7xx_vcp1_hwmod,
2948 .clk = "l3_iclk_div",
2949 .user = OCP_USER_MPU | OCP_USER_SDMA,
2952 /* l4_per2 -> vcp1 */
2953 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
2954 .master = &dra7xx_l4_per2_hwmod,
2955 .slave = &dra7xx_vcp1_hwmod,
2956 .clk = "l3_iclk_div",
2957 .user = OCP_USER_MPU | OCP_USER_SDMA,
2960 /* l3_main_1 -> vcp2 */
2961 static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
2962 .master = &dra7xx_l3_main_1_hwmod,
2963 .slave = &dra7xx_vcp2_hwmod,
2964 .clk = "l3_iclk_div",
2965 .user = OCP_USER_MPU | OCP_USER_SDMA,
2968 /* l4_per2 -> vcp2 */
2969 static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
2970 .master = &dra7xx_l4_per2_hwmod,
2971 .slave = &dra7xx_vcp2_hwmod,
2972 .clk = "l3_iclk_div",
2973 .user = OCP_USER_MPU | OCP_USER_SDMA,
2976 /* l4_wkup -> wd_timer2 */
2977 static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
2978 .master = &dra7xx_l4_wkup_hwmod,
2979 .slave = &dra7xx_wd_timer2_hwmod,
2980 .clk = "wkupaon_iclk_mux",
2981 .user = OCP_USER_MPU | OCP_USER_SDMA,
2984 /* l4_per2 -> epwmss0 */
2985 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss0 = {
2986 .master = &dra7xx_l4_per2_hwmod,
2987 .slave = &dra7xx_epwmss0_hwmod,
2988 .clk = "l4_root_clk_div",
2989 .user = OCP_USER_MPU,
2992 /* l4_per2 -> epwmss1 */
2993 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss1 = {
2994 .master = &dra7xx_l4_per2_hwmod,
2995 .slave = &dra7xx_epwmss1_hwmod,
2996 .clk = "l4_root_clk_div",
2997 .user = OCP_USER_MPU,
3000 /* l4_per2 -> epwmss2 */
3001 static struct omap_hwmod_ocp_if dra7xx_l4_per2__epwmss2 = {
3002 .master = &dra7xx_l4_per2_hwmod,
3003 .slave = &dra7xx_epwmss2_hwmod,
3004 .clk = "l4_root_clk_div",
3005 .user = OCP_USER_MPU,
3008 static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
3009 &dra7xx_l3_main_1__dmm,
3010 &dra7xx_l3_main_2__l3_instr,
3011 &dra7xx_l4_cfg__l3_main_1,
3012 &dra7xx_mpu__l3_main_1,
3013 &dra7xx_l3_main_1__l3_main_2,
3014 &dra7xx_l4_cfg__l3_main_2,
3015 &dra7xx_l3_main_1__l4_cfg,
3016 &dra7xx_l3_main_1__l4_per1,
3017 &dra7xx_l3_main_1__l4_per2,
3018 &dra7xx_l3_main_1__l4_per3,
3019 &dra7xx_l3_main_1__l4_wkup,
3020 &dra7xx_l4_per2__atl,
3021 &dra7xx_l3_main_1__bb2d,
3022 &dra7xx_l4_wkup__counter_32k,
3023 &dra7xx_l4_wkup__ctrl_module_wkup,
3024 &dra7xx_l4_wkup__dcan1,
3025 &dra7xx_l4_per2__dcan2,
3026 &dra7xx_l4_per2__cpgmac0,
3027 &dra7xx_l4_per2__mcasp1,
3028 &dra7xx_l3_main_1__mcasp1,
3029 &dra7xx_l4_per2__mcasp2,
3030 &dra7xx_l3_main_1__mcasp2,
3031 &dra7xx_l4_per2__mcasp3,
3032 &dra7xx_l3_main_1__mcasp3,
3033 &dra7xx_l4_per2__mcasp4,
3034 &dra7xx_l4_per2__mcasp5,
3035 &dra7xx_l4_per2__mcasp6,
3036 &dra7xx_l4_per2__mcasp7,
3037 &dra7xx_l4_per2__mcasp8,
3039 &dra7xx_l4_cfg__dma_system,
3040 &dra7xx_l3_main_1__tpcc,
3041 &dra7xx_l3_main_1__tptc0,
3042 &dra7xx_l3_main_1__tptc1,
3043 &dra7xx_l3_main_1__dss,
3044 &dra7xx_l3_main_1__dispc,
3045 &dra7xx_l3_main_1__hdmi,
3046 &dra7xx_l3_main_1__aes1,
3047 &dra7xx_l3_main_1__aes2,
3048 &dra7xx_l3_main_1__sha0,
3049 &dra7xx_l4_per1__elm,
3050 &dra7xx_l3_main_1__gpmc,
3051 &dra7xx_l4_per1__hdq1w,
3052 &dra7xx_l4_cfg__mailbox1,
3053 &dra7xx_l4_per3__mailbox2,
3054 &dra7xx_l4_per3__mailbox3,
3055 &dra7xx_l4_per3__mailbox4,
3056 &dra7xx_l4_per3__mailbox5,
3057 &dra7xx_l4_per3__mailbox6,
3058 &dra7xx_l4_per3__mailbox7,
3059 &dra7xx_l4_per3__mailbox8,
3060 &dra7xx_l4_per3__mailbox9,
3061 &dra7xx_l4_per3__mailbox10,
3062 &dra7xx_l4_per3__mailbox11,
3063 &dra7xx_l4_per3__mailbox12,
3064 &dra7xx_l4_per3__mailbox13,
3065 &dra7xx_l4_per1__mcspi1,
3066 &dra7xx_l4_per1__mcspi2,
3067 &dra7xx_l4_per1__mcspi3,
3068 &dra7xx_l4_per1__mcspi4,
3069 &dra7xx_l4_cfg__mpu,
3070 &dra7xx_l4_cfg__ocp2scp1,
3071 &dra7xx_l4_cfg__ocp2scp3,
3072 &dra7xx_l3_main_1__pciess1,
3073 &dra7xx_l4_cfg__pciess1,
3074 &dra7xx_l3_main_1__pciess2,
3075 &dra7xx_l4_cfg__pciess2,
3076 &dra7xx_l3_main_1__qspi,
3077 &dra7xx_l4_cfg__sata,
3078 &dra7xx_l4_cfg__smartreflex_core,
3079 &dra7xx_l4_cfg__smartreflex_mpu,
3080 &dra7xx_l4_cfg__spinlock,
3081 &dra7xx_l4_wkup__timer1,
3082 &dra7xx_l4_per1__timer2,
3083 &dra7xx_l4_per1__timer3,
3084 &dra7xx_l4_per1__timer4,
3085 &dra7xx_l4_per3__timer5,
3086 &dra7xx_l4_per3__timer6,
3087 &dra7xx_l4_per3__timer7,
3088 &dra7xx_l4_per3__timer8,
3089 &dra7xx_l4_per1__timer9,
3090 &dra7xx_l4_per1__timer10,
3091 &dra7xx_l4_per1__timer11,
3092 &dra7xx_l4_per3__timer13,
3093 &dra7xx_l4_per3__timer14,
3094 &dra7xx_l4_per3__timer15,
3095 &dra7xx_l4_per3__timer16,
3096 &dra7xx_l4_per1__des,
3097 &dra7xx_l4_per3__usb_otg_ss1,
3098 &dra7xx_l4_per3__usb_otg_ss2,
3099 &dra7xx_l4_per3__usb_otg_ss3,
3100 &dra7xx_l3_main_1__vcp1,
3101 &dra7xx_l4_per2__vcp1,
3102 &dra7xx_l3_main_1__vcp2,
3103 &dra7xx_l4_per2__vcp2,
3104 &dra7xx_l4_wkup__wd_timer2,
3105 &dra7xx_l4_per2__epwmss0,
3106 &dra7xx_l4_per2__epwmss1,
3107 &dra7xx_l4_per2__epwmss2,
3111 /* GP-only hwmod links */
3112 static struct omap_hwmod_ocp_if *dra7xx_gp_hwmod_ocp_ifs[] __initdata = {
3113 &dra7xx_l4_wkup__timer12,
3114 &dra7xx_l4_per1__rng,
3118 /* SoC variant specific hwmod links */
3119 static struct omap_hwmod_ocp_if *dra76x_hwmod_ocp_ifs[] __initdata = {
3120 &dra7xx_l4_per3__usb_otg_ss4,
3124 static struct omap_hwmod_ocp_if *acd_76x_hwmod_ocp_ifs[] __initdata = {
3128 static struct omap_hwmod_ocp_if *dra74x_hwmod_ocp_ifs[] __initdata = {
3129 &dra7xx_l4_per3__usb_otg_ss4,
3133 static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
3137 static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
3138 &dra7xx_l4_per3__rtcss,
3142 int __init dra7xx_hwmod_init(void)
3147 ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
3149 if (!ret && soc_is_dra74x()) {
3150 ret = omap_hwmod_register_links(dra74x_hwmod_ocp_ifs);
3152 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
3153 } else if (!ret && soc_is_dra72x()) {
3154 ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
3155 if (!ret && !of_machine_is_compatible("ti,dra718"))
3156 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
3157 } else if (!ret && soc_is_dra76x()) {
3158 ret = omap_hwmod_register_links(dra76x_hwmod_ocp_ifs);
3160 if (!ret && soc_is_dra76x_acd()) {
3161 ret = omap_hwmod_register_links(acd_76x_hwmod_ocp_ifs);
3162 } else if (!ret && soc_is_dra76x_abz()) {
3163 ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
3167 if (!ret && omap_type() == OMAP2_DEVICE_TYPE_GP)
3168 ret = omap_hwmod_register_links(dra7xx_gp_hwmod_ocp_ifs);