1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hardware modules present on the OMAP54xx chips
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
18 #include <linux/power/smartreflex.h>
20 #include <linux/omap-dma.h>
22 #include "omap_hwmod.h"
23 #include "omap_hwmod_common_data.h"
29 /* Base offset for all OMAP5 interrupts external to MPUSS */
30 #define OMAP54XX_IRQ_GIC_START 32
32 /* Base offset for all OMAP5 dma requests */
33 #define OMAP54XX_DMA_REQ_START 1
44 static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
49 static struct omap_hwmod omap54xx_dmm_hwmod = {
51 .class = &omap54xx_dmm_hwmod_class,
52 .clkdm_name = "emif_clkdm",
55 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
56 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
63 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
65 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
70 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
72 .class = &omap54xx_l3_hwmod_class,
73 .clkdm_name = "l3instr_clkdm",
76 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
77 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
78 .modulemode = MODULEMODE_HWCTRL,
84 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
86 .class = &omap54xx_l3_hwmod_class,
87 .clkdm_name = "l3main1_clkdm",
90 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
91 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
97 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
99 .class = &omap54xx_l3_hwmod_class,
100 .clkdm_name = "l3main2_clkdm",
103 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
104 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
110 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
112 .class = &omap54xx_l3_hwmod_class,
113 .clkdm_name = "l3instr_clkdm",
116 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
117 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
118 .modulemode = MODULEMODE_HWCTRL,
125 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
127 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
132 static struct omap_hwmod omap54xx_l4_abe_hwmod = {
134 .class = &omap54xx_l4_hwmod_class,
135 .clkdm_name = "abe_clkdm",
138 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
139 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
145 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
147 .class = &omap54xx_l4_hwmod_class,
148 .clkdm_name = "l4cfg_clkdm",
151 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
152 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
158 static struct omap_hwmod omap54xx_l4_per_hwmod = {
160 .class = &omap54xx_l4_hwmod_class,
161 .clkdm_name = "l4per_clkdm",
164 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
165 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
171 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
173 .class = &omap54xx_l4_hwmod_class,
174 .clkdm_name = "wkupaon_clkdm",
177 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
178 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
185 * instance(s): mpu_private
187 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
192 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
193 .name = "mpu_private",
194 .class = &omap54xx_mpu_bus_hwmod_class,
195 .clkdm_name = "mpu_clkdm",
198 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
205 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
208 static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
211 .sysc_flags = SYSC_HAS_SIDLEMODE,
212 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
213 .sysc_fields = &omap_hwmod_sysc_type1,
216 static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
218 .sysc = &omap54xx_counter_sysc,
222 static struct omap_hwmod omap54xx_counter_32k_hwmod = {
223 .name = "counter_32k",
224 .class = &omap54xx_counter_hwmod_class,
225 .clkdm_name = "wkupaon_clkdm",
226 .flags = HWMOD_SWSUP_SIDLE,
227 .main_clk = "wkupaon_iclk_mux",
230 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
231 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
238 * dma controller for data exchange between memory to memory (i.e. internal or
239 * external memory) and gp peripherals to memory or memory to gp peripherals
242 static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
246 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
247 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
248 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
249 SYSS_HAS_RESET_STATUS),
250 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
251 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
252 .sysc_fields = &omap_hwmod_sysc_type1,
255 static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
257 .sysc = &omap54xx_dma_sysc,
261 static struct omap_dma_dev_attr dma_dev_attr = {
262 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
263 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
268 static struct omap_hwmod omap54xx_dma_system_hwmod = {
269 .name = "dma_system",
270 .class = &omap54xx_dma_hwmod_class,
271 .clkdm_name = "dma_clkdm",
272 .main_clk = "l3_iclk_div",
275 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
276 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
279 .dev_attr = &dma_dev_attr,
284 * digital microphone controller
287 static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
290 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
291 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
292 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
294 .sysc_fields = &omap_hwmod_sysc_type2,
297 static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
299 .sysc = &omap54xx_dmic_sysc,
303 static struct omap_hwmod omap54xx_dmic_hwmod = {
305 .class = &omap54xx_dmic_hwmod_class,
306 .clkdm_name = "abe_clkdm",
307 .main_clk = "dmic_gfclk",
310 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
311 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
312 .modulemode = MODULEMODE_SWCTRL,
321 static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
324 .sysc_flags = SYSS_HAS_RESET_STATUS,
327 static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
329 .sysc = &omap54xx_dss_sysc,
330 .reset = omap_dss_reset,
334 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
335 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
336 { .role = "sys_clk", .clk = "dss_sys_clk" },
337 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
340 static struct omap_hwmod omap54xx_dss_hwmod = {
342 .class = &omap54xx_dss_hwmod_class,
343 .clkdm_name = "dss_clkdm",
344 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
345 .main_clk = "dss_dss_clk",
348 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
349 .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
350 .modulemode = MODULEMODE_SWCTRL,
353 .opt_clks = dss_opt_clks,
354 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
362 static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
366 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
367 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
368 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
369 SYSS_HAS_RESET_STATUS),
370 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
371 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
372 .sysc_fields = &omap_hwmod_sysc_type1,
375 static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
377 .sysc = &omap54xx_dispc_sysc,
381 static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
382 { .role = "sys_clk", .clk = "dss_sys_clk" },
385 /* dss_dispc dev_attr */
386 static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
387 .has_framedonetv_irq = 1,
391 static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
393 .class = &omap54xx_dispc_hwmod_class,
394 .clkdm_name = "dss_clkdm",
395 .main_clk = "dss_dss_clk",
398 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
399 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
402 .opt_clks = dss_dispc_opt_clks,
403 .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
404 .dev_attr = &dss_dispc_dev_attr,
405 .parent_hwmod = &omap54xx_dss_hwmod,
410 * display serial interface controller
413 static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
417 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
418 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
419 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
420 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
421 .sysc_fields = &omap_hwmod_sysc_type1,
424 static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
426 .sysc = &omap54xx_dsi1_sysc,
430 static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
431 { .role = "sys_clk", .clk = "dss_sys_clk" },
434 static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
436 .class = &omap54xx_dsi1_hwmod_class,
437 .clkdm_name = "dss_clkdm",
438 .main_clk = "dss_dss_clk",
441 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
442 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
445 .opt_clks = dss_dsi1_a_opt_clks,
446 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_a_opt_clks),
447 .parent_hwmod = &omap54xx_dss_hwmod,
451 static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
452 { .role = "sys_clk", .clk = "dss_sys_clk" },
455 static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
457 .class = &omap54xx_dsi1_hwmod_class,
458 .clkdm_name = "dss_clkdm",
459 .main_clk = "dss_dss_clk",
462 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
463 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
466 .opt_clks = dss_dsi1_c_opt_clks,
467 .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_c_opt_clks),
468 .parent_hwmod = &omap54xx_dss_hwmod,
476 static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
479 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
481 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
483 .sysc_fields = &omap_hwmod_sysc_type2,
486 static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
488 .sysc = &omap54xx_hdmi_sysc,
491 static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
492 { .role = "sys_clk", .clk = "dss_sys_clk" },
495 static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
497 .class = &omap54xx_hdmi_hwmod_class,
498 .clkdm_name = "dss_clkdm",
499 .main_clk = "dss_48mhz_clk",
502 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
503 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
506 .opt_clks = dss_hdmi_opt_clks,
507 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
508 .parent_hwmod = &omap54xx_dss_hwmod,
513 * remote frame buffer interface
516 static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
520 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
521 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
522 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
523 .sysc_fields = &omap_hwmod_sysc_type1,
526 static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
528 .sysc = &omap54xx_rfbi_sysc,
532 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
533 { .role = "ick", .clk = "l3_iclk_div" },
536 static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
538 .class = &omap54xx_rfbi_hwmod_class,
539 .clkdm_name = "dss_clkdm",
542 .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
543 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
546 .opt_clks = dss_rfbi_opt_clks,
547 .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
548 .parent_hwmod = &omap54xx_dss_hwmod,
553 * external memory interface no1 (wrapper)
556 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
560 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
562 .sysc = &omap54xx_emif_sysc,
566 static struct omap_hwmod omap54xx_emif1_hwmod = {
568 .class = &omap54xx_emif_hwmod_class,
569 .clkdm_name = "emif_clkdm",
570 .flags = HWMOD_INIT_NO_IDLE,
571 .main_clk = "dpll_core_h11x2_ck",
574 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
575 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
576 .modulemode = MODULEMODE_HWCTRL,
582 static struct omap_hwmod omap54xx_emif2_hwmod = {
584 .class = &omap54xx_emif_hwmod_class,
585 .clkdm_name = "emif_clkdm",
586 .flags = HWMOD_INIT_NO_IDLE,
587 .main_clk = "dpll_core_h11x2_ck",
590 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
591 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
592 .modulemode = MODULEMODE_HWCTRL,
599 * keyboard controller
602 static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
605 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
607 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
608 .sysc_fields = &omap_hwmod_sysc_type1,
611 static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
613 .sysc = &omap54xx_kbd_sysc,
617 static struct omap_hwmod omap54xx_kbd_hwmod = {
619 .class = &omap54xx_kbd_hwmod_class,
620 .clkdm_name = "wkupaon_clkdm",
621 .main_clk = "sys_32k_ck",
624 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
625 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
626 .modulemode = MODULEMODE_SWCTRL,
633 * mailbox module allowing communication between the on-chip processors using a
634 * queued mailbox-interrupt mechanism.
637 static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
640 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
642 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
643 .sysc_fields = &omap_hwmod_sysc_type2,
646 static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
648 .sysc = &omap54xx_mailbox_sysc,
652 static struct omap_hwmod omap54xx_mailbox_hwmod = {
654 .class = &omap54xx_mailbox_hwmod_class,
655 .clkdm_name = "l4cfg_clkdm",
658 .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
659 .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
666 * multi channel buffered serial port controller
669 static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
672 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
673 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
674 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
675 .sysc_fields = &omap_hwmod_sysc_type1,
678 static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
680 .sysc = &omap54xx_mcbsp_sysc,
684 static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
685 { .role = "pad_fck", .clk = "pad_clks_ck" },
686 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
689 static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
691 .class = &omap54xx_mcbsp_hwmod_class,
692 .clkdm_name = "abe_clkdm",
693 .main_clk = "mcbsp1_gfclk",
696 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
697 .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
698 .modulemode = MODULEMODE_SWCTRL,
701 .opt_clks = mcbsp1_opt_clks,
702 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
706 static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
707 { .role = "pad_fck", .clk = "pad_clks_ck" },
708 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
711 static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
713 .class = &omap54xx_mcbsp_hwmod_class,
714 .clkdm_name = "abe_clkdm",
715 .main_clk = "mcbsp2_gfclk",
718 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
719 .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
720 .modulemode = MODULEMODE_SWCTRL,
723 .opt_clks = mcbsp2_opt_clks,
724 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
728 static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
729 { .role = "pad_fck", .clk = "pad_clks_ck" },
730 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
733 static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
735 .class = &omap54xx_mcbsp_hwmod_class,
736 .clkdm_name = "abe_clkdm",
737 .main_clk = "mcbsp3_gfclk",
740 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
741 .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
742 .modulemode = MODULEMODE_SWCTRL,
745 .opt_clks = mcbsp3_opt_clks,
746 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
751 * multi channel pdm controller (proprietary interface with phoenix power
755 static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
758 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
759 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
760 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
762 .sysc_fields = &omap_hwmod_sysc_type2,
765 static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
767 .sysc = &omap54xx_mcpdm_sysc,
771 static struct omap_hwmod omap54xx_mcpdm_hwmod = {
773 .class = &omap54xx_mcpdm_hwmod_class,
774 .clkdm_name = "abe_clkdm",
776 * It's suspected that the McPDM requires an off-chip main
777 * functional clock, controlled via I2C. This IP block is
778 * currently reset very early during boot, before I2C is
779 * available, so it doesn't seem that we have any choice in
780 * the kernel other than to avoid resetting it. XXX This is
781 * really a hardware issue workaround: every IP block should
782 * be able to source its main functional clock from either
783 * on-chip or off-chip sources. McPDM seems to be the only
787 .flags = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
788 .main_clk = "pad_clks_ck",
791 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
792 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
793 .modulemode = MODULEMODE_SWCTRL,
800 * multichannel serial port interface (mcspi) / master/slave synchronous serial
804 static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
807 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
808 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
809 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
811 .sysc_fields = &omap_hwmod_sysc_type2,
814 static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
816 .sysc = &omap54xx_mcspi_sysc,
820 static struct omap_hwmod omap54xx_mcspi1_hwmod = {
822 .class = &omap54xx_mcspi_hwmod_class,
823 .clkdm_name = "l4per_clkdm",
824 .main_clk = "func_48m_fclk",
827 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
828 .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
829 .modulemode = MODULEMODE_SWCTRL,
835 static struct omap_hwmod omap54xx_mcspi2_hwmod = {
837 .class = &omap54xx_mcspi_hwmod_class,
838 .clkdm_name = "l4per_clkdm",
839 .main_clk = "func_48m_fclk",
842 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
843 .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
844 .modulemode = MODULEMODE_SWCTRL,
850 static struct omap_hwmod omap54xx_mcspi3_hwmod = {
852 .class = &omap54xx_mcspi_hwmod_class,
853 .clkdm_name = "l4per_clkdm",
854 .main_clk = "func_48m_fclk",
857 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
858 .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
859 .modulemode = MODULEMODE_SWCTRL,
865 static struct omap_hwmod omap54xx_mcspi4_hwmod = {
867 .class = &omap54xx_mcspi_hwmod_class,
868 .clkdm_name = "l4per_clkdm",
869 .main_clk = "func_48m_fclk",
872 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
873 .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
874 .modulemode = MODULEMODE_SWCTRL,
881 * The memory management unit performs virtual to physical address translation
882 * for its requestors.
885 static struct omap_hwmod_class_sysconfig omap54xx_mmu_sysc = {
889 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
890 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
891 SYSS_HAS_RESET_STATUS),
892 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
893 .sysc_fields = &omap_hwmod_sysc_type1,
896 static struct omap_hwmod_class omap54xx_mmu_hwmod_class = {
898 .sysc = &omap54xx_mmu_sysc,
901 static struct omap_hwmod_rst_info omap54xx_mmu_dsp_resets[] = {
902 { .name = "mmu_cache", .rst_shift = 1 },
905 static struct omap_hwmod omap54xx_mmu_dsp_hwmod = {
907 .class = &omap54xx_mmu_hwmod_class,
908 .clkdm_name = "dsp_clkdm",
909 .rst_lines = omap54xx_mmu_dsp_resets,
910 .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_dsp_resets),
911 .main_clk = "dpll_iva_h11x2_ck",
914 .clkctrl_offs = OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET,
915 .rstctrl_offs = OMAP54XX_RM_DSP_RSTCTRL_OFFSET,
916 .context_offs = OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET,
917 .modulemode = MODULEMODE_HWCTRL,
923 static struct omap_hwmod_rst_info omap54xx_mmu_ipu_resets[] = {
924 { .name = "mmu_cache", .rst_shift = 2 },
927 static struct omap_hwmod omap54xx_mmu_ipu_hwmod = {
929 .class = &omap54xx_mmu_hwmod_class,
930 .clkdm_name = "ipu_clkdm",
931 .rst_lines = omap54xx_mmu_ipu_resets,
932 .rst_lines_cnt = ARRAY_SIZE(omap54xx_mmu_ipu_resets),
933 .main_clk = "dpll_core_h22x2_ck",
936 .clkctrl_offs = OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET,
937 .rstctrl_offs = OMAP54XX_RM_IPU_RSTCTRL_OFFSET,
938 .context_offs = OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET,
939 .modulemode = MODULEMODE_HWCTRL,
949 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
954 static struct omap_hwmod omap54xx_mpu_hwmod = {
956 .class = &omap54xx_mpu_hwmod_class,
957 .clkdm_name = "mpu_clkdm",
958 .flags = HWMOD_INIT_NO_IDLE,
959 .main_clk = "dpll_mpu_m2_ck",
962 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
963 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
970 * spinlock provides hardware assistance for synchronizing the processes
971 * running on multiple processors
974 static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
978 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
979 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
980 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
981 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
982 .sysc_fields = &omap_hwmod_sysc_type1,
985 static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
987 .sysc = &omap54xx_spinlock_sysc,
991 static struct omap_hwmod omap54xx_spinlock_hwmod = {
993 .class = &omap54xx_spinlock_hwmod_class,
994 .clkdm_name = "l4cfg_clkdm",
997 .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
998 .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1005 * bridge to transform ocp interface protocol to scp (serial control port)
1009 static struct omap_hwmod_class_sysconfig omap54xx_ocp2scp_sysc = {
1011 .sysc_offs = 0x0010,
1012 .syss_offs = 0x0014,
1013 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1014 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1015 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1016 .sysc_fields = &omap_hwmod_sysc_type1,
1019 static struct omap_hwmod_class omap54xx_ocp2scp_hwmod_class = {
1021 .sysc = &omap54xx_ocp2scp_sysc,
1025 static struct omap_hwmod omap54xx_ocp2scp1_hwmod = {
1027 .class = &omap54xx_ocp2scp_hwmod_class,
1028 .clkdm_name = "l3init_clkdm",
1029 .main_clk = "l4_root_clk_div",
1032 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1033 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1034 .modulemode = MODULEMODE_HWCTRL,
1041 * general purpose timer module with accurate 1ms tick
1042 * This class contains several variants: ['timer_1ms', 'timer']
1045 static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1047 .sysc_offs = 0x0010,
1048 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1049 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1050 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1052 .sysc_fields = &omap_hwmod_sysc_type2,
1055 static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1057 .sysc = &omap54xx_timer_1ms_sysc,
1060 static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1062 .sysc_offs = 0x0010,
1063 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1064 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1065 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1067 .sysc_fields = &omap_hwmod_sysc_type2,
1070 static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1072 .sysc = &omap54xx_timer_sysc,
1076 static struct omap_hwmod omap54xx_timer1_hwmod = {
1078 .class = &omap54xx_timer_1ms_hwmod_class,
1079 .clkdm_name = "wkupaon_clkdm",
1080 .main_clk = "timer1_gfclk_mux",
1081 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1084 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1085 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1086 .modulemode = MODULEMODE_SWCTRL,
1092 static struct omap_hwmod omap54xx_timer2_hwmod = {
1094 .class = &omap54xx_timer_1ms_hwmod_class,
1095 .clkdm_name = "l4per_clkdm",
1096 .main_clk = "timer2_gfclk_mux",
1097 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1100 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1101 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1102 .modulemode = MODULEMODE_SWCTRL,
1108 static struct omap_hwmod omap54xx_timer3_hwmod = {
1110 .class = &omap54xx_timer_hwmod_class,
1111 .clkdm_name = "l4per_clkdm",
1112 .main_clk = "timer3_gfclk_mux",
1115 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1116 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1117 .modulemode = MODULEMODE_SWCTRL,
1123 static struct omap_hwmod omap54xx_timer4_hwmod = {
1125 .class = &omap54xx_timer_hwmod_class,
1126 .clkdm_name = "l4per_clkdm",
1127 .main_clk = "timer4_gfclk_mux",
1130 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1131 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1132 .modulemode = MODULEMODE_SWCTRL,
1138 static struct omap_hwmod omap54xx_timer5_hwmod = {
1140 .class = &omap54xx_timer_hwmod_class,
1141 .clkdm_name = "abe_clkdm",
1142 .main_clk = "timer5_gfclk_mux",
1145 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1146 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1147 .modulemode = MODULEMODE_SWCTRL,
1153 static struct omap_hwmod omap54xx_timer6_hwmod = {
1155 .class = &omap54xx_timer_hwmod_class,
1156 .clkdm_name = "abe_clkdm",
1157 .main_clk = "timer6_gfclk_mux",
1160 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1161 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1162 .modulemode = MODULEMODE_SWCTRL,
1168 static struct omap_hwmod omap54xx_timer7_hwmod = {
1170 .class = &omap54xx_timer_hwmod_class,
1171 .clkdm_name = "abe_clkdm",
1172 .main_clk = "timer7_gfclk_mux",
1175 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1176 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1177 .modulemode = MODULEMODE_SWCTRL,
1183 static struct omap_hwmod omap54xx_timer8_hwmod = {
1185 .class = &omap54xx_timer_hwmod_class,
1186 .clkdm_name = "abe_clkdm",
1187 .main_clk = "timer8_gfclk_mux",
1190 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1191 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1192 .modulemode = MODULEMODE_SWCTRL,
1198 static struct omap_hwmod omap54xx_timer9_hwmod = {
1200 .class = &omap54xx_timer_hwmod_class,
1201 .clkdm_name = "l4per_clkdm",
1202 .main_clk = "timer9_gfclk_mux",
1205 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1206 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1207 .modulemode = MODULEMODE_SWCTRL,
1213 static struct omap_hwmod omap54xx_timer10_hwmod = {
1215 .class = &omap54xx_timer_1ms_hwmod_class,
1216 .clkdm_name = "l4per_clkdm",
1217 .main_clk = "timer10_gfclk_mux",
1218 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1221 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1222 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1223 .modulemode = MODULEMODE_SWCTRL,
1229 static struct omap_hwmod omap54xx_timer11_hwmod = {
1231 .class = &omap54xx_timer_hwmod_class,
1232 .clkdm_name = "l4per_clkdm",
1233 .main_clk = "timer11_gfclk_mux",
1236 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1237 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1238 .modulemode = MODULEMODE_SWCTRL,
1244 * 'usb_host_hs' class
1245 * high-speed multi-port usb host controller
1248 static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
1250 .sysc_offs = 0x0010,
1251 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1252 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1253 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1254 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1255 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1256 .sysc_fields = &omap_hwmod_sysc_type2,
1259 static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
1260 .name = "usb_host_hs",
1261 .sysc = &omap54xx_usb_host_hs_sysc,
1264 static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
1265 .name = "usb_host_hs",
1266 .class = &omap54xx_usb_host_hs_hwmod_class,
1267 .clkdm_name = "l3init_clkdm",
1269 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1273 * In the following configuration :
1274 * - USBHOST module is set to smart-idle mode
1275 * - PRCM asserts idle_req to the USBHOST module ( This typically
1276 * happens when the system is going to a low power mode : all ports
1277 * have been suspended, the master part of the USBHOST module has
1278 * entered the standby state, and SW has cut the functional clocks)
1279 * - an USBHOST interrupt occurs before the module is able to answer
1280 * idle_ack, typically a remote wakeup IRQ.
1281 * Then the USB HOST module will enter a deadlock situation where it
1282 * is no more accessible nor functional.
1285 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1289 * Errata: USB host EHCI may stall when entering smart-standby mode
1293 * When the USBHOST module is set to smart-standby mode, and when it is
1294 * ready to enter the standby state (i.e. all ports are suspended and
1295 * all attached devices are in suspend mode), then it can wrongly assert
1296 * the Mstandby signal too early while there are still some residual OCP
1297 * transactions ongoing. If this condition occurs, the internal state
1298 * machine may go to an undefined state and the USB link may be stuck
1299 * upon the next resume.
1302 * Don't use smart standby; use only force standby,
1303 * hence HWMOD_SWSUP_MSTANDBY
1306 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1307 .main_clk = "l3init_60m_fclk",
1310 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
1311 .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
1312 .modulemode = MODULEMODE_SWCTRL,
1318 * 'usb_tll_hs' class
1319 * usb_tll_hs module is the adapter on the usb_host_hs ports
1322 static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
1324 .sysc_offs = 0x0010,
1325 .syss_offs = 0x0014,
1326 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1327 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1328 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1329 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1330 .sysc_fields = &omap_hwmod_sysc_type1,
1333 static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
1334 .name = "usb_tll_hs",
1335 .sysc = &omap54xx_usb_tll_hs_sysc,
1338 static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
1339 .name = "usb_tll_hs",
1340 .class = &omap54xx_usb_tll_hs_hwmod_class,
1341 .clkdm_name = "l3init_clkdm",
1342 .main_clk = "l4_root_clk_div",
1345 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
1346 .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
1347 .modulemode = MODULEMODE_HWCTRL,
1353 * 'usb_otg_ss' class
1354 * 2.0 super speed (usb_otg_ss) controller
1357 static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1359 .sysc_offs = 0x0010,
1360 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1361 SYSC_HAS_SIDLEMODE),
1362 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1363 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1364 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1365 .sysc_fields = &omap_hwmod_sysc_type2,
1368 static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1369 .name = "usb_otg_ss",
1370 .sysc = &omap54xx_usb_otg_ss_sysc,
1374 static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1375 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1378 static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1379 .name = "usb_otg_ss",
1380 .class = &omap54xx_usb_otg_ss_hwmod_class,
1381 .clkdm_name = "l3init_clkdm",
1382 .flags = HWMOD_SWSUP_SIDLE,
1383 .main_clk = "dpll_core_h13x2_ck",
1386 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1387 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1388 .modulemode = MODULEMODE_HWCTRL,
1391 .opt_clks = usb_otg_ss_opt_clks,
1392 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
1397 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1398 * overflow condition
1401 static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1403 .sysc_offs = 0x0010,
1404 .syss_offs = 0x0014,
1405 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1406 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1407 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1409 .sysc_fields = &omap_hwmod_sysc_type1,
1412 static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
1414 .sysc = &omap54xx_wd_timer_sysc,
1415 .pre_shutdown = &omap2_wd_timer_disable,
1419 static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
1420 .name = "wd_timer2",
1421 .class = &omap54xx_wd_timer_hwmod_class,
1422 .clkdm_name = "wkupaon_clkdm",
1423 .main_clk = "sys_32k_ck",
1426 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1427 .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1428 .modulemode = MODULEMODE_SWCTRL,
1435 * bridge to transform ocp interface protocol to scp (serial control port)
1439 static struct omap_hwmod omap54xx_ocp2scp3_hwmod;
1440 /* l4_cfg -> ocp2scp3 */
1441 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp3 = {
1442 .master = &omap54xx_l4_cfg_hwmod,
1443 .slave = &omap54xx_ocp2scp3_hwmod,
1444 .clk = "l4_root_clk_div",
1445 .user = OCP_USER_MPU | OCP_USER_SDMA,
1448 static struct omap_hwmod omap54xx_ocp2scp3_hwmod = {
1450 .class = &omap54xx_ocp2scp_hwmod_class,
1451 .clkdm_name = "l3init_clkdm",
1454 .clkctrl_offs = OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET,
1455 .context_offs = OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET,
1456 .modulemode = MODULEMODE_HWCTRL,
1463 * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
1466 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
1468 .sysc_offs = 0x0000,
1469 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1470 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1471 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1472 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1473 .sysc_fields = &omap_hwmod_sysc_type2,
1476 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
1478 .sysc = &omap54xx_sata_sysc,
1482 static struct omap_hwmod omap54xx_sata_hwmod = {
1484 .class = &omap54xx_sata_hwmod_class,
1485 .clkdm_name = "l3init_clkdm",
1486 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1487 .main_clk = "func_48m_fclk",
1491 .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1492 .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1493 .modulemode = MODULEMODE_SWCTRL,
1498 /* l4_cfg -> sata */
1499 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
1500 .master = &omap54xx_l4_cfg_hwmod,
1501 .slave = &omap54xx_sata_hwmod,
1502 .clk = "l3_iclk_div",
1503 .user = OCP_USER_MPU | OCP_USER_SDMA,
1510 /* l3_main_1 -> dmm */
1511 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
1512 .master = &omap54xx_l3_main_1_hwmod,
1513 .slave = &omap54xx_dmm_hwmod,
1514 .clk = "l3_iclk_div",
1515 .user = OCP_USER_SDMA,
1518 /* l3_main_3 -> l3_instr */
1519 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
1520 .master = &omap54xx_l3_main_3_hwmod,
1521 .slave = &omap54xx_l3_instr_hwmod,
1522 .clk = "l3_iclk_div",
1523 .user = OCP_USER_MPU | OCP_USER_SDMA,
1526 /* l3_main_2 -> l3_main_1 */
1527 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
1528 .master = &omap54xx_l3_main_2_hwmod,
1529 .slave = &omap54xx_l3_main_1_hwmod,
1530 .clk = "l3_iclk_div",
1531 .user = OCP_USER_MPU | OCP_USER_SDMA,
1534 /* l4_cfg -> l3_main_1 */
1535 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
1536 .master = &omap54xx_l4_cfg_hwmod,
1537 .slave = &omap54xx_l3_main_1_hwmod,
1538 .clk = "l3_iclk_div",
1539 .user = OCP_USER_MPU | OCP_USER_SDMA,
1542 /* l4_cfg -> mmu_dsp */
1543 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mmu_dsp = {
1544 .master = &omap54xx_l4_cfg_hwmod,
1545 .slave = &omap54xx_mmu_dsp_hwmod,
1546 .clk = "l4_root_clk_div",
1547 .user = OCP_USER_MPU | OCP_USER_SDMA,
1550 /* mpu -> l3_main_1 */
1551 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
1552 .master = &omap54xx_mpu_hwmod,
1553 .slave = &omap54xx_l3_main_1_hwmod,
1554 .clk = "l3_iclk_div",
1555 .user = OCP_USER_MPU,
1558 /* l3_main_1 -> l3_main_2 */
1559 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
1560 .master = &omap54xx_l3_main_1_hwmod,
1561 .slave = &omap54xx_l3_main_2_hwmod,
1562 .clk = "l3_iclk_div",
1563 .user = OCP_USER_MPU,
1566 /* l4_cfg -> l3_main_2 */
1567 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
1568 .master = &omap54xx_l4_cfg_hwmod,
1569 .slave = &omap54xx_l3_main_2_hwmod,
1570 .clk = "l3_iclk_div",
1571 .user = OCP_USER_MPU | OCP_USER_SDMA,
1574 /* l3_main_2 -> mmu_ipu */
1575 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__mmu_ipu = {
1576 .master = &omap54xx_l3_main_2_hwmod,
1577 .slave = &omap54xx_mmu_ipu_hwmod,
1578 .clk = "l3_iclk_div",
1579 .user = OCP_USER_MPU | OCP_USER_SDMA,
1582 /* l3_main_1 -> l3_main_3 */
1583 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
1584 .master = &omap54xx_l3_main_1_hwmod,
1585 .slave = &omap54xx_l3_main_3_hwmod,
1586 .clk = "l3_iclk_div",
1587 .user = OCP_USER_MPU,
1590 /* l3_main_2 -> l3_main_3 */
1591 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
1592 .master = &omap54xx_l3_main_2_hwmod,
1593 .slave = &omap54xx_l3_main_3_hwmod,
1594 .clk = "l3_iclk_div",
1595 .user = OCP_USER_MPU | OCP_USER_SDMA,
1598 /* l4_cfg -> l3_main_3 */
1599 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
1600 .master = &omap54xx_l4_cfg_hwmod,
1601 .slave = &omap54xx_l3_main_3_hwmod,
1602 .clk = "l3_iclk_div",
1603 .user = OCP_USER_MPU | OCP_USER_SDMA,
1606 /* l3_main_1 -> l4_abe */
1607 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
1608 .master = &omap54xx_l3_main_1_hwmod,
1609 .slave = &omap54xx_l4_abe_hwmod,
1611 .user = OCP_USER_MPU | OCP_USER_SDMA,
1615 static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
1616 .master = &omap54xx_mpu_hwmod,
1617 .slave = &omap54xx_l4_abe_hwmod,
1619 .user = OCP_USER_MPU | OCP_USER_SDMA,
1622 /* l3_main_1 -> l4_cfg */
1623 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
1624 .master = &omap54xx_l3_main_1_hwmod,
1625 .slave = &omap54xx_l4_cfg_hwmod,
1626 .clk = "l4_root_clk_div",
1627 .user = OCP_USER_MPU | OCP_USER_SDMA,
1630 /* l3_main_2 -> l4_per */
1631 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
1632 .master = &omap54xx_l3_main_2_hwmod,
1633 .slave = &omap54xx_l4_per_hwmod,
1634 .clk = "l4_root_clk_div",
1635 .user = OCP_USER_MPU | OCP_USER_SDMA,
1638 /* l3_main_1 -> l4_wkup */
1639 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
1640 .master = &omap54xx_l3_main_1_hwmod,
1641 .slave = &omap54xx_l4_wkup_hwmod,
1642 .clk = "wkupaon_iclk_mux",
1643 .user = OCP_USER_MPU | OCP_USER_SDMA,
1646 /* mpu -> mpu_private */
1647 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
1648 .master = &omap54xx_mpu_hwmod,
1649 .slave = &omap54xx_mpu_private_hwmod,
1650 .clk = "l3_iclk_div",
1651 .user = OCP_USER_MPU | OCP_USER_SDMA,
1654 /* l4_wkup -> counter_32k */
1655 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
1656 .master = &omap54xx_l4_wkup_hwmod,
1657 .slave = &omap54xx_counter_32k_hwmod,
1658 .clk = "wkupaon_iclk_mux",
1659 .user = OCP_USER_MPU | OCP_USER_SDMA,
1662 /* l4_cfg -> dma_system */
1663 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
1664 .master = &omap54xx_l4_cfg_hwmod,
1665 .slave = &omap54xx_dma_system_hwmod,
1666 .clk = "l4_root_clk_div",
1667 .user = OCP_USER_MPU | OCP_USER_SDMA,
1670 /* l4_abe -> dmic */
1671 static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
1672 .master = &omap54xx_l4_abe_hwmod,
1673 .slave = &omap54xx_dmic_hwmod,
1675 .user = OCP_USER_MPU,
1678 /* l3_main_2 -> dss */
1679 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
1680 .master = &omap54xx_l3_main_2_hwmod,
1681 .slave = &omap54xx_dss_hwmod,
1682 .clk = "l3_iclk_div",
1683 .user = OCP_USER_MPU | OCP_USER_SDMA,
1686 /* l3_main_2 -> dss_dispc */
1687 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
1688 .master = &omap54xx_l3_main_2_hwmod,
1689 .slave = &omap54xx_dss_dispc_hwmod,
1690 .clk = "l3_iclk_div",
1691 .user = OCP_USER_MPU | OCP_USER_SDMA,
1694 /* l3_main_2 -> dss_dsi1_a */
1695 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
1696 .master = &omap54xx_l3_main_2_hwmod,
1697 .slave = &omap54xx_dss_dsi1_a_hwmod,
1698 .clk = "l3_iclk_div",
1699 .user = OCP_USER_MPU | OCP_USER_SDMA,
1702 /* l3_main_2 -> dss_dsi1_c */
1703 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
1704 .master = &omap54xx_l3_main_2_hwmod,
1705 .slave = &omap54xx_dss_dsi1_c_hwmod,
1706 .clk = "l3_iclk_div",
1707 .user = OCP_USER_MPU | OCP_USER_SDMA,
1710 /* l3_main_2 -> dss_hdmi */
1711 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
1712 .master = &omap54xx_l3_main_2_hwmod,
1713 .slave = &omap54xx_dss_hdmi_hwmod,
1714 .clk = "l3_iclk_div",
1715 .user = OCP_USER_MPU | OCP_USER_SDMA,
1718 /* l3_main_2 -> dss_rfbi */
1719 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
1720 .master = &omap54xx_l3_main_2_hwmod,
1721 .slave = &omap54xx_dss_rfbi_hwmod,
1722 .clk = "l3_iclk_div",
1723 .user = OCP_USER_MPU | OCP_USER_SDMA,
1727 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
1728 .master = &omap54xx_mpu_hwmod,
1729 .slave = &omap54xx_emif1_hwmod,
1730 .clk = "dpll_core_h11x2_ck",
1731 .user = OCP_USER_MPU | OCP_USER_SDMA,
1735 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
1736 .master = &omap54xx_mpu_hwmod,
1737 .slave = &omap54xx_emif2_hwmod,
1738 .clk = "dpll_core_h11x2_ck",
1739 .user = OCP_USER_MPU | OCP_USER_SDMA,
1742 /* l4_wkup -> kbd */
1743 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
1744 .master = &omap54xx_l4_wkup_hwmod,
1745 .slave = &omap54xx_kbd_hwmod,
1746 .clk = "wkupaon_iclk_mux",
1747 .user = OCP_USER_MPU | OCP_USER_SDMA,
1750 /* l4_cfg -> mailbox */
1751 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
1752 .master = &omap54xx_l4_cfg_hwmod,
1753 .slave = &omap54xx_mailbox_hwmod,
1754 .clk = "l4_root_clk_div",
1755 .user = OCP_USER_MPU | OCP_USER_SDMA,
1758 /* l4_abe -> mcbsp1 */
1759 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
1760 .master = &omap54xx_l4_abe_hwmod,
1761 .slave = &omap54xx_mcbsp1_hwmod,
1763 .user = OCP_USER_MPU,
1766 /* l4_abe -> mcbsp2 */
1767 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
1768 .master = &omap54xx_l4_abe_hwmod,
1769 .slave = &omap54xx_mcbsp2_hwmod,
1771 .user = OCP_USER_MPU,
1774 /* l4_abe -> mcbsp3 */
1775 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
1776 .master = &omap54xx_l4_abe_hwmod,
1777 .slave = &omap54xx_mcbsp3_hwmod,
1779 .user = OCP_USER_MPU,
1782 /* l4_abe -> mcpdm */
1783 static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
1784 .master = &omap54xx_l4_abe_hwmod,
1785 .slave = &omap54xx_mcpdm_hwmod,
1787 .user = OCP_USER_MPU,
1790 /* l4_per -> mcspi1 */
1791 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
1792 .master = &omap54xx_l4_per_hwmod,
1793 .slave = &omap54xx_mcspi1_hwmod,
1794 .clk = "l4_root_clk_div",
1795 .user = OCP_USER_MPU | OCP_USER_SDMA,
1798 /* l4_per -> mcspi2 */
1799 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
1800 .master = &omap54xx_l4_per_hwmod,
1801 .slave = &omap54xx_mcspi2_hwmod,
1802 .clk = "l4_root_clk_div",
1803 .user = OCP_USER_MPU | OCP_USER_SDMA,
1806 /* l4_per -> mcspi3 */
1807 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
1808 .master = &omap54xx_l4_per_hwmod,
1809 .slave = &omap54xx_mcspi3_hwmod,
1810 .clk = "l4_root_clk_div",
1811 .user = OCP_USER_MPU | OCP_USER_SDMA,
1814 /* l4_per -> mcspi4 */
1815 static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
1816 .master = &omap54xx_l4_per_hwmod,
1817 .slave = &omap54xx_mcspi4_hwmod,
1818 .clk = "l4_root_clk_div",
1819 .user = OCP_USER_MPU | OCP_USER_SDMA,
1823 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
1824 .master = &omap54xx_l4_cfg_hwmod,
1825 .slave = &omap54xx_mpu_hwmod,
1826 .clk = "l4_root_clk_div",
1827 .user = OCP_USER_MPU | OCP_USER_SDMA,
1830 /* l4_cfg -> spinlock */
1831 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
1832 .master = &omap54xx_l4_cfg_hwmod,
1833 .slave = &omap54xx_spinlock_hwmod,
1834 .clk = "l4_root_clk_div",
1835 .user = OCP_USER_MPU | OCP_USER_SDMA,
1838 /* l4_cfg -> ocp2scp1 */
1839 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__ocp2scp1 = {
1840 .master = &omap54xx_l4_cfg_hwmod,
1841 .slave = &omap54xx_ocp2scp1_hwmod,
1842 .clk = "l4_root_clk_div",
1843 .user = OCP_USER_MPU | OCP_USER_SDMA,
1846 /* l4_wkup -> timer1 */
1847 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
1848 .master = &omap54xx_l4_wkup_hwmod,
1849 .slave = &omap54xx_timer1_hwmod,
1850 .clk = "wkupaon_iclk_mux",
1851 .user = OCP_USER_MPU | OCP_USER_SDMA,
1854 /* l4_per -> timer2 */
1855 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
1856 .master = &omap54xx_l4_per_hwmod,
1857 .slave = &omap54xx_timer2_hwmod,
1858 .clk = "l4_root_clk_div",
1859 .user = OCP_USER_MPU | OCP_USER_SDMA,
1862 /* l4_per -> timer3 */
1863 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
1864 .master = &omap54xx_l4_per_hwmod,
1865 .slave = &omap54xx_timer3_hwmod,
1866 .clk = "l4_root_clk_div",
1867 .user = OCP_USER_MPU | OCP_USER_SDMA,
1870 /* l4_per -> timer4 */
1871 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
1872 .master = &omap54xx_l4_per_hwmod,
1873 .slave = &omap54xx_timer4_hwmod,
1874 .clk = "l4_root_clk_div",
1875 .user = OCP_USER_MPU | OCP_USER_SDMA,
1878 /* l4_abe -> timer5 */
1879 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
1880 .master = &omap54xx_l4_abe_hwmod,
1881 .slave = &omap54xx_timer5_hwmod,
1883 .user = OCP_USER_MPU,
1886 /* l4_abe -> timer6 */
1887 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
1888 .master = &omap54xx_l4_abe_hwmod,
1889 .slave = &omap54xx_timer6_hwmod,
1891 .user = OCP_USER_MPU,
1894 /* l4_abe -> timer7 */
1895 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
1896 .master = &omap54xx_l4_abe_hwmod,
1897 .slave = &omap54xx_timer7_hwmod,
1899 .user = OCP_USER_MPU,
1902 /* l4_abe -> timer8 */
1903 static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
1904 .master = &omap54xx_l4_abe_hwmod,
1905 .slave = &omap54xx_timer8_hwmod,
1907 .user = OCP_USER_MPU,
1910 /* l4_per -> timer9 */
1911 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
1912 .master = &omap54xx_l4_per_hwmod,
1913 .slave = &omap54xx_timer9_hwmod,
1914 .clk = "l4_root_clk_div",
1915 .user = OCP_USER_MPU | OCP_USER_SDMA,
1918 /* l4_per -> timer10 */
1919 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
1920 .master = &omap54xx_l4_per_hwmod,
1921 .slave = &omap54xx_timer10_hwmod,
1922 .clk = "l4_root_clk_div",
1923 .user = OCP_USER_MPU | OCP_USER_SDMA,
1926 /* l4_per -> timer11 */
1927 static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
1928 .master = &omap54xx_l4_per_hwmod,
1929 .slave = &omap54xx_timer11_hwmod,
1930 .clk = "l4_root_clk_div",
1931 .user = OCP_USER_MPU | OCP_USER_SDMA,
1934 /* l4_cfg -> usb_host_hs */
1935 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
1936 .master = &omap54xx_l4_cfg_hwmod,
1937 .slave = &omap54xx_usb_host_hs_hwmod,
1938 .clk = "l3_iclk_div",
1939 .user = OCP_USER_MPU | OCP_USER_SDMA,
1942 /* l4_cfg -> usb_tll_hs */
1943 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
1944 .master = &omap54xx_l4_cfg_hwmod,
1945 .slave = &omap54xx_usb_tll_hs_hwmod,
1946 .clk = "l4_root_clk_div",
1947 .user = OCP_USER_MPU | OCP_USER_SDMA,
1950 /* l4_cfg -> usb_otg_ss */
1951 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
1952 .master = &omap54xx_l4_cfg_hwmod,
1953 .slave = &omap54xx_usb_otg_ss_hwmod,
1954 .clk = "dpll_core_h13x2_ck",
1955 .user = OCP_USER_MPU | OCP_USER_SDMA,
1958 /* l4_wkup -> wd_timer2 */
1959 static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
1960 .master = &omap54xx_l4_wkup_hwmod,
1961 .slave = &omap54xx_wd_timer2_hwmod,
1962 .clk = "wkupaon_iclk_mux",
1963 .user = OCP_USER_MPU | OCP_USER_SDMA,
1966 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
1967 &omap54xx_l3_main_1__dmm,
1968 &omap54xx_l3_main_3__l3_instr,
1969 &omap54xx_l3_main_2__l3_main_1,
1970 &omap54xx_l4_cfg__l3_main_1,
1971 &omap54xx_mpu__l3_main_1,
1972 &omap54xx_l3_main_1__l3_main_2,
1973 &omap54xx_l4_cfg__l3_main_2,
1974 &omap54xx_l3_main_1__l3_main_3,
1975 &omap54xx_l3_main_2__l3_main_3,
1976 &omap54xx_l4_cfg__l3_main_3,
1977 &omap54xx_l3_main_1__l4_abe,
1978 &omap54xx_mpu__l4_abe,
1979 &omap54xx_l3_main_1__l4_cfg,
1980 &omap54xx_l3_main_2__l4_per,
1981 &omap54xx_l3_main_1__l4_wkup,
1982 &omap54xx_mpu__mpu_private,
1983 &omap54xx_l4_wkup__counter_32k,
1984 &omap54xx_l4_cfg__dma_system,
1985 &omap54xx_l4_abe__dmic,
1986 &omap54xx_l4_cfg__mmu_dsp,
1987 &omap54xx_l3_main_2__dss,
1988 &omap54xx_l3_main_2__dss_dispc,
1989 &omap54xx_l3_main_2__dss_dsi1_a,
1990 &omap54xx_l3_main_2__dss_dsi1_c,
1991 &omap54xx_l3_main_2__dss_hdmi,
1992 &omap54xx_l3_main_2__dss_rfbi,
1993 &omap54xx_mpu__emif1,
1994 &omap54xx_mpu__emif2,
1995 &omap54xx_l3_main_2__mmu_ipu,
1996 &omap54xx_l4_wkup__kbd,
1997 &omap54xx_l4_cfg__mailbox,
1998 &omap54xx_l4_abe__mcbsp1,
1999 &omap54xx_l4_abe__mcbsp2,
2000 &omap54xx_l4_abe__mcbsp3,
2001 &omap54xx_l4_abe__mcpdm,
2002 &omap54xx_l4_per__mcspi1,
2003 &omap54xx_l4_per__mcspi2,
2004 &omap54xx_l4_per__mcspi3,
2005 &omap54xx_l4_per__mcspi4,
2006 &omap54xx_l4_cfg__mpu,
2007 &omap54xx_l4_cfg__spinlock,
2008 &omap54xx_l4_cfg__ocp2scp1,
2009 &omap54xx_l4_wkup__timer1,
2010 &omap54xx_l4_per__timer2,
2011 &omap54xx_l4_per__timer3,
2012 &omap54xx_l4_per__timer4,
2013 &omap54xx_l4_abe__timer5,
2014 &omap54xx_l4_abe__timer6,
2015 &omap54xx_l4_abe__timer7,
2016 &omap54xx_l4_abe__timer8,
2017 &omap54xx_l4_per__timer9,
2018 &omap54xx_l4_per__timer10,
2019 &omap54xx_l4_per__timer11,
2020 &omap54xx_l4_cfg__usb_host_hs,
2021 &omap54xx_l4_cfg__usb_tll_hs,
2022 &omap54xx_l4_cfg__usb_otg_ss,
2023 &omap54xx_l4_wkup__wd_timer2,
2024 &omap54xx_l4_cfg__ocp2scp3,
2025 &omap54xx_l4_cfg__sata,
2029 int __init omap54xx_hwmod_init(void)
2032 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);