arch/arm/mach-omap2/omap_hwmod_54xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP54xx chips
   4  *
   5  * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Paul Walmsley
   8  * Benoit Cousson
   9  *
  10  * This file is automatically generated from the OMAP hardware databases.
  11  * We respectfully ask that any modifications to this file be coordinated
  12  * with the public linux-omap@vger.kernel.org mailing list and the
  13  * authors above to ensure that the autogeneration scripts are kept
  14  * up-to-date with the file contents.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/power/smartreflex.h>
  19
  20 #include "omap_hwmod.h"
  21 #include "omap_hwmod_common_data.h"
  22 #include "cm1_54xx.h"
  23 #include "cm2_54xx.h"
  24 #include "prm54xx.h"
  25
  26 /* Base offset for all OMAP5 interrupts external to MPUSS */
  27 #define OMAP54XX_IRQ_GIC_START  32
  28
  29 /*
  30  * IP blocks
  31  */
  32
  33 /*
  34  * 'l3' class
  35  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  36  */
  37 static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
  38         .name   = "l3",
  39 };
  40
  41 /* l3_instr */
  42 static struct omap_hwmod omap54xx_l3_instr_hwmod = {
  43         .name           = "l3_instr",
  44         .class          = &omap54xx_l3_hwmod_class,
  45         .clkdm_name     = "l3instr_clkdm",
  46         .prcm = {
  47                 .omap4 = {
  48                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  49                         .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  50                         .modulemode   = MODULEMODE_HWCTRL,
  51                 },
  52         },
  53 };
  54
  55 /* l3_main_1 */
  56 static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
  57         .name           = "l3_main_1",
  58         .class          = &omap54xx_l3_hwmod_class,
  59         .clkdm_name     = "l3main1_clkdm",
  60         .prcm = {
  61                 .omap4 = {
  62                         .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
  63                         .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
  64                 },
  65         },
  66 };
  67
  68 /* l3_main_2 */
  69 static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
  70         .name           = "l3_main_2",
  71         .class          = &omap54xx_l3_hwmod_class,
  72         .clkdm_name     = "l3main2_clkdm",
  73         .prcm = {
  74                 .omap4 = {
  75                         .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
  76                         .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
  77                 },
  78         },
  79 };
  80
  81 /* l3_main_3 */
  82 static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
  83         .name           = "l3_main_3",
  84         .class          = &omap54xx_l3_hwmod_class,
  85         .clkdm_name     = "l3instr_clkdm",
  86         .prcm = {
  87                 .omap4 = {
  88                         .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
  89                         .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
  90                         .modulemode   = MODULEMODE_HWCTRL,
  91                 },
  92         },
  93 };
  94
  95 /*
  96  * 'l4' class
  97  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
  98  */
  99 static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
 100         .name   = "l4",
 101 };
 102
 103 /* l4_cfg */
 104 static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
 105         .name           = "l4_cfg",
 106         .class          = &omap54xx_l4_hwmod_class,
 107         .clkdm_name     = "l4cfg_clkdm",
 108         .prcm = {
 109                 .omap4 = {
 110                         .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 111                         .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 112                 },
 113         },
 114 };
 115
 116 /* l4_per */
 117 static struct omap_hwmod omap54xx_l4_per_hwmod = {
 118         .name           = "l4_per",
 119         .class          = &omap54xx_l4_hwmod_class,
 120         .clkdm_name     = "l4per_clkdm",
 121         .prcm = {
 122                 .omap4 = {
 123                         .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
 124                         .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 125                 },
 126         },
 127 };
 128
 129 /* l4_wkup */
 130 static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
 131         .name           = "l4_wkup",
 132         .class          = &omap54xx_l4_hwmod_class,
 133         .clkdm_name     = "wkupaon_clkdm",
 134         .prcm = {
 135                 .omap4 = {
 136                         .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
 137                         .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
 138                 },
 139         },
 140 };
 141
 142 /*
 143  * 'mpu_bus' class
 144  * instance(s): mpu_private
 145  */
 146 static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
 147         .name   = "mpu_bus",
 148 };
 149
 150 /* mpu_private */
 151 static struct omap_hwmod omap54xx_mpu_private_hwmod = {
 152         .name           = "mpu_private",
 153         .class          = &omap54xx_mpu_bus_hwmod_class,
 154         .clkdm_name     = "mpu_clkdm",
 155         .prcm = {
 156                 .omap4 = {
 157                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 158                 },
 159         },
 160 };
 161
 162 /*
 163  * 'emif' class
 164  * external memory interface no1 (wrapper)
 165  */
 166
 167 static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
 168         .rev_offs       = 0x0000,
 169 };
 170
 171 static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
 172         .name   = "emif",
 173         .sysc   = &omap54xx_emif_sysc,
 174 };
 175
 176 /* emif1 */
 177 static struct omap_hwmod omap54xx_emif1_hwmod = {
 178         .name           = "emif1",
 179         .class          = &omap54xx_emif_hwmod_class,
 180         .clkdm_name     = "emif_clkdm",
 181         .flags          = HWMOD_INIT_NO_IDLE,
 182         .main_clk       = "dpll_core_h11x2_ck",
 183         .prcm = {
 184                 .omap4 = {
 185                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
 186                         .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
 187                         .modulemode   = MODULEMODE_HWCTRL,
 188                 },
 189         },
 190 };
 191
 192 /* emif2 */
 193 static struct omap_hwmod omap54xx_emif2_hwmod = {
 194         .name           = "emif2",
 195         .class          = &omap54xx_emif_hwmod_class,
 196         .clkdm_name     = "emif_clkdm",
 197         .flags          = HWMOD_INIT_NO_IDLE,
 198         .main_clk       = "dpll_core_h11x2_ck",
 199         .prcm = {
 200                 .omap4 = {
 201                         .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
 202                         .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
 203                         .modulemode   = MODULEMODE_HWCTRL,
 204                 },
 205         },
 206 };
 207
 208
 209
 210
 211 /*
 212  * 'mpu' class
 213  * mpu sub-system
 214  */
 215
 216 static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
 217         .name   = "mpu",
 218 };
 219
 220 /* mpu */
 221 static struct omap_hwmod omap54xx_mpu_hwmod = {
 222         .name           = "mpu",
 223         .class          = &omap54xx_mpu_hwmod_class,
 224         .clkdm_name     = "mpu_clkdm",
 225         .flags          = HWMOD_INIT_NO_IDLE,
 226         .main_clk       = "dpll_mpu_m2_ck",
 227         .prcm = {
 228                 .omap4 = {
 229                         .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
 230                         .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
 231                 },
 232         },
 233 };
 234
 235 /*
 236  * 'sata' class
 237  * sata:  serial ata interface  gen2 compliant   ( 1 rx/ 1 tx)
 238  */
 239
 240 static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
 241         .rev_offs       = 0x00fc,
 242         .sysc_offs      = 0x0000,
 243         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 244         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 245                            SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
 246                            MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
 247         .sysc_fields    = &omap_hwmod_sysc_type2,
 248 };
 249
 250 static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
 251         .name   = "sata",
 252         .sysc   = &omap54xx_sata_sysc,
 253 };
 254
 255 /* sata */
 256 static struct omap_hwmod omap54xx_sata_hwmod = {
 257         .name           = "sata",
 258         .class          = &omap54xx_sata_hwmod_class,
 259         .clkdm_name     = "l3init_clkdm",
 260         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
 261         .main_clk       = "func_48m_fclk",
 262         .mpu_rt_idx     = 1,
 263         .prcm = {
 264                 .omap4 = {
 265                         .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
 266                         .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
 267                         .modulemode   = MODULEMODE_SWCTRL,
 268                 },
 269         },
 270 };
 271
 272 /* l4_cfg -> sata */
 273 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
 274         .master         = &omap54xx_l4_cfg_hwmod,
 275         .slave          = &omap54xx_sata_hwmod,
 276         .clk            = "l3_iclk_div",
 277         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 278 };
 279
 280 /*
 281  * Interfaces
 282  */
 283
 284 /* l3_main_3 -> l3_instr */
 285 static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
 286         .master         = &omap54xx_l3_main_3_hwmod,
 287         .slave          = &omap54xx_l3_instr_hwmod,
 288         .clk            = "l3_iclk_div",
 289         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 290 };
 291
 292 /* l3_main_2 -> l3_main_1 */
 293 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
 294         .master         = &omap54xx_l3_main_2_hwmod,
 295         .slave          = &omap54xx_l3_main_1_hwmod,
 296         .clk            = "l3_iclk_div",
 297         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 298 };
 299
 300 /* l4_cfg -> l3_main_1 */
 301 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
 302         .master         = &omap54xx_l4_cfg_hwmod,
 303         .slave          = &omap54xx_l3_main_1_hwmod,
 304         .clk            = "l3_iclk_div",
 305         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 306 };
 307
 308 /* mpu -> l3_main_1 */
 309 static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
 310         .master         = &omap54xx_mpu_hwmod,
 311         .slave          = &omap54xx_l3_main_1_hwmod,
 312         .clk            = "l3_iclk_div",
 313         .user           = OCP_USER_MPU,
 314 };
 315
 316 /* l3_main_1 -> l3_main_2 */
 317 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
 318         .master         = &omap54xx_l3_main_1_hwmod,
 319         .slave          = &omap54xx_l3_main_2_hwmod,
 320         .clk            = "l3_iclk_div",
 321         .user           = OCP_USER_MPU,
 322 };
 323
 324 /* l4_cfg -> l3_main_2 */
 325 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
 326         .master         = &omap54xx_l4_cfg_hwmod,
 327         .slave          = &omap54xx_l3_main_2_hwmod,
 328         .clk            = "l3_iclk_div",
 329         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 330 };
 331
 332 /* l3_main_1 -> l3_main_3 */
 333 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
 334         .master         = &omap54xx_l3_main_1_hwmod,
 335         .slave          = &omap54xx_l3_main_3_hwmod,
 336         .clk            = "l3_iclk_div",
 337         .user           = OCP_USER_MPU,
 338 };
 339
 340 /* l3_main_2 -> l3_main_3 */
 341 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
 342         .master         = &omap54xx_l3_main_2_hwmod,
 343         .slave          = &omap54xx_l3_main_3_hwmod,
 344         .clk            = "l3_iclk_div",
 345         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 346 };
 347
 348 /* l4_cfg -> l3_main_3 */
 349 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
 350         .master         = &omap54xx_l4_cfg_hwmod,
 351         .slave          = &omap54xx_l3_main_3_hwmod,
 352         .clk            = "l3_iclk_div",
 353         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 354 };
 355
 356 /* l3_main_1 -> l4_cfg */
 357 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
 358         .master         = &omap54xx_l3_main_1_hwmod,
 359         .slave          = &omap54xx_l4_cfg_hwmod,
 360         .clk            = "l4_root_clk_div",
 361         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 362 };
 363
 364 /* l3_main_2 -> l4_per */
 365 static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
 366         .master         = &omap54xx_l3_main_2_hwmod,
 367         .slave          = &omap54xx_l4_per_hwmod,
 368         .clk            = "l4_root_clk_div",
 369         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 370 };
 371
 372 /* l3_main_1 -> l4_wkup */
 373 static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
 374         .master         = &omap54xx_l3_main_1_hwmod,
 375         .slave          = &omap54xx_l4_wkup_hwmod,
 376         .clk            = "wkupaon_iclk_mux",
 377         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 378 };
 379
 380 /* mpu -> mpu_private */
 381 static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
 382         .master         = &omap54xx_mpu_hwmod,
 383         .slave          = &omap54xx_mpu_private_hwmod,
 384         .clk            = "l3_iclk_div",
 385         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 386 };
 387
 388 /* mpu -> emif1 */
 389 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
 390         .master         = &omap54xx_mpu_hwmod,
 391         .slave          = &omap54xx_emif1_hwmod,
 392         .clk            = "dpll_core_h11x2_ck",
 393         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 394 };
 395
 396 /* mpu -> emif2 */
 397 static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
 398         .master         = &omap54xx_mpu_hwmod,
 399         .slave          = &omap54xx_emif2_hwmod,
 400         .clk            = "dpll_core_h11x2_ck",
 401         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 402 };
 403
 404 /* l4_cfg -> mpu */
 405 static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
 406         .master         = &omap54xx_l4_cfg_hwmod,
 407         .slave          = &omap54xx_mpu_hwmod,
 408         .clk            = "l4_root_clk_div",
 409         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 410 };
 411
 412 static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
 413         &omap54xx_l3_main_3__l3_instr,
 414         &omap54xx_l3_main_2__l3_main_1,
 415         &omap54xx_l4_cfg__l3_main_1,
 416         &omap54xx_mpu__l3_main_1,
 417         &omap54xx_l3_main_1__l3_main_2,
 418         &omap54xx_l4_cfg__l3_main_2,
 419         &omap54xx_l3_main_1__l3_main_3,
 420         &omap54xx_l3_main_2__l3_main_3,
 421         &omap54xx_l4_cfg__l3_main_3,
 422         &omap54xx_l3_main_1__l4_cfg,
 423         &omap54xx_l3_main_2__l4_per,
 424         &omap54xx_l3_main_1__l4_wkup,
 425         &omap54xx_mpu__mpu_private,
 426         &omap54xx_mpu__emif1,
 427         &omap54xx_mpu__emif2,
 428         &omap54xx_l4_cfg__mpu,
 429         &omap54xx_l4_cfg__sata,
 430         NULL,
 431 };
 432
 433 int __init omap54xx_hwmod_init(void)
 434 {
 435         omap_hwmod_init();
 436         return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
 437 }