arch/arm/mach-omap2/omap_hwmod_44xx_data.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hardware modules present on the OMAP44xx chips
   4  *
   5  * Copyright (C) 2009-2012 Texas Instruments, Inc.
   6  * Copyright (C) 2009-2010 Nokia Corporation
   7  *
   8  * Paul Walmsley
   9  * Benoit Cousson
  10  *
  11  * This file is automatically generated from the OMAP hardware databases.
  12  * We respectfully ask that any modifications to this file be coordinated
  13  * with the public linux-omap@vger.kernel.org mailing list and the
  14  * authors above to ensure that the autogeneration scripts are kept
  15  * up-to-date with the file contents.
  16  * Note that this file is currently not in sync with autogeneration scripts.
  17  * The above note to be removed, once it is synced up.
  18  */
  19
  20 #include <linux/io.h>
  21
  22 #include "omap_hwmod.h"
  23 #include "omap_hwmod_common_data.h"
  24 #include "cm1_44xx.h"
  25 #include "cm2_44xx.h"
  26 #include "prm44xx.h"
  27 #include "prm-regbits-44xx.h"
  28
  29 /* Base offset for all OMAP4 interrupts external to MPUSS */
  30 #define OMAP44XX_IRQ_GIC_START  32
  31
  32 /*
  33  * IP blocks
  34  */
  35
  36 /*
  37  * 'l3' class
  38  * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  39  */
  40 static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  41         .name   = "l3",
  42 };
  43
  44 /* l3_instr */
  45 static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  46         .name           = "l3_instr",
  47         .class          = &omap44xx_l3_hwmod_class,
  48         .clkdm_name     = "l3_instr_clkdm",
  49         .prcm = {
  50                 .omap4 = {
  51                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  52                         .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  53                         .modulemode   = MODULEMODE_HWCTRL,
  54                 },
  55         },
  56 };
  57
  58 /* l3_main_1 */
  59 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  60         .name           = "l3_main_1",
  61         .class          = &omap44xx_l3_hwmod_class,
  62         .clkdm_name     = "l3_1_clkdm",
  63         .prcm = {
  64                 .omap4 = {
  65                         .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
  66                         .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
  67                 },
  68         },
  69 };
  70
  71 /* l3_main_2 */
  72 static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
  73         .name           = "l3_main_2",
  74         .class          = &omap44xx_l3_hwmod_class,
  75         .clkdm_name     = "l3_2_clkdm",
  76         .prcm = {
  77                 .omap4 = {
  78                         .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
  79                         .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
  80                 },
  81         },
  82 };
  83
  84 /* l3_main_3 */
  85 static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
  86         .name           = "l3_main_3",
  87         .class          = &omap44xx_l3_hwmod_class,
  88         .clkdm_name     = "l3_instr_clkdm",
  89         .prcm = {
  90                 .omap4 = {
  91                         .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
  92                         .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
  93                         .modulemode   = MODULEMODE_HWCTRL,
  94                 },
  95         },
  96 };
  97
  98 /*
  99  * 'l4' class
 100  * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 101  */
 102 static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 103         .name   = "l4",
 104 };
 105
 106 /* l4_cfg */
 107 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 108         .name           = "l4_cfg",
 109         .class          = &omap44xx_l4_hwmod_class,
 110         .clkdm_name     = "l4_cfg_clkdm",
 111         .prcm = {
 112                 .omap4 = {
 113                         .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 114                         .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 115                 },
 116         },
 117 };
 118
 119 /* l4_per */
 120 static struct omap_hwmod omap44xx_l4_per_hwmod = {
 121         .name           = "l4_per",
 122         .class          = &omap44xx_l4_hwmod_class,
 123         .clkdm_name     = "l4_per_clkdm",
 124         .prcm = {
 125                 .omap4 = {
 126                         .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 127                         .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 128                 },
 129         },
 130 };
 131
 132 /* l4_wkup */
 133 static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 134         .name           = "l4_wkup",
 135         .class          = &omap44xx_l4_hwmod_class,
 136         .clkdm_name     = "l4_wkup_clkdm",
 137         .prcm = {
 138                 .omap4 = {
 139                         .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 140                         .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 141                 },
 142         },
 143 };
 144
 145 /*
 146  * 'mpu_bus' class
 147  * instance(s): mpu_private
 148  */
 149 static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 150         .name   = "mpu_bus",
 151 };
 152
 153 /* mpu_private */
 154 static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 155         .name           = "mpu_private",
 156         .class          = &omap44xx_mpu_bus_hwmod_class,
 157         .clkdm_name     = "mpuss_clkdm",
 158         .prcm = {
 159                 .omap4 = {
 160                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 161                 },
 162         },
 163 };
 164
 165 /*
 166  * 'ocp_wp_noc' class
 167  * instance(s): ocp_wp_noc
 168  */
 169 static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 170         .name   = "ocp_wp_noc",
 171 };
 172
 173 /* ocp_wp_noc */
 174 static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 175         .name           = "ocp_wp_noc",
 176         .class          = &omap44xx_ocp_wp_noc_hwmod_class,
 177         .clkdm_name     = "l3_instr_clkdm",
 178         .prcm = {
 179                 .omap4 = {
 180                         .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 181                         .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 182                         .modulemode   = MODULEMODE_HWCTRL,
 183                 },
 184         },
 185 };
 186
 187 /*
 188  * Modules omap_hwmod structures
 189  *
 190  * The following IPs are excluded for the moment because:
 191  * - They do not need an explicit SW control using omap_hwmod API.
 192  * - They still need to be validated with the driver
 193  *   properly adapted to omap_hwmod / omap_device
 194  *
 195  * usim
 196  */
 197
 198 /*
 199  * 'debugss' class
 200  * debug and emulation sub system
 201  */
 202
 203 static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 204         .name   = "debugss",
 205 };
 206
 207 /* debugss */
 208 static struct omap_hwmod omap44xx_debugss_hwmod = {
 209         .name           = "debugss",
 210         .class          = &omap44xx_debugss_hwmod_class,
 211         .clkdm_name     = "emu_sys_clkdm",
 212         .main_clk       = "trace_clk_div_ck",
 213         .prcm = {
 214                 .omap4 = {
 215                         .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 216                         .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 217                 },
 218         },
 219 };
 220
 221 /*
 222  * 'emif' class
 223  * external memory interface no1
 224  */
 225
 226 static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 227         .rev_offs       = 0x0000,
 228 };
 229
 230 static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 231         .name   = "emif",
 232         .sysc   = &omap44xx_emif_sysc,
 233 };
 234
 235 /* emif1 */
 236 static struct omap_hwmod omap44xx_emif1_hwmod = {
 237         .name           = "emif1",
 238         .class          = &omap44xx_emif_hwmod_class,
 239         .clkdm_name     = "l3_emif_clkdm",
 240         .flags          = HWMOD_INIT_NO_IDLE,
 241         .main_clk       = "ddrphy_ck",
 242         .prcm = {
 243                 .omap4 = {
 244                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 245                         .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 246                         .modulemode   = MODULEMODE_HWCTRL,
 247                 },
 248         },
 249 };
 250
 251 /* emif2 */
 252 static struct omap_hwmod omap44xx_emif2_hwmod = {
 253         .name           = "emif2",
 254         .class          = &omap44xx_emif_hwmod_class,
 255         .clkdm_name     = "l3_emif_clkdm",
 256         .flags          = HWMOD_INIT_NO_IDLE,
 257         .main_clk       = "ddrphy_ck",
 258         .prcm = {
 259                 .omap4 = {
 260                         .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 261                         .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 262                         .modulemode   = MODULEMODE_HWCTRL,
 263                 },
 264         },
 265 };
 266
 267 /*
 268  * 'mpu' class
 269  * mpu sub-system
 270  */
 271
 272 static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 273         .name   = "mpu",
 274 };
 275
 276 /* mpu */
 277 static struct omap_hwmod omap44xx_mpu_hwmod = {
 278         .name           = "mpu",
 279         .class          = &omap44xx_mpu_hwmod_class,
 280         .clkdm_name     = "mpuss_clkdm",
 281         .flags          = HWMOD_INIT_NO_IDLE,
 282         .main_clk       = "dpll_mpu_m2_ck",
 283         .prcm = {
 284                 .omap4 = {
 285                         .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
 286                         .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
 287                 },
 288         },
 289 };
 290
 291 /*
 292  * 'ocmc_ram' class
 293  * top-level core on-chip ram
 294  */
 295
 296 static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
 297         .name   = "ocmc_ram",
 298 };
 299
 300 /* ocmc_ram */
 301 static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
 302         .name           = "ocmc_ram",
 303         .class          = &omap44xx_ocmc_ram_hwmod_class,
 304         .clkdm_name     = "l3_2_clkdm",
 305         .prcm = {
 306                 .omap4 = {
 307                         .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
 308                         .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
 309                 },
 310         },
 311 };
 312
 313
 314 /*
 315  * 'prcm' class
 316  * power and reset manager (part of the prcm infrastructure) + clock manager 2
 317  * + clock manager 1 (in always on power domain) + local prm in mpu
 318  */
 319
 320 static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
 321         .name   = "prcm",
 322 };
 323
 324 /* prcm_mpu */
 325 static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
 326         .name           = "prcm_mpu",
 327         .class          = &omap44xx_prcm_hwmod_class,
 328         .clkdm_name     = "l4_wkup_clkdm",
 329         .flags          = HWMOD_NO_IDLEST,
 330         .prcm = {
 331                 .omap4 = {
 332                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 333                 },
 334         },
 335 };
 336
 337 /* cm_core_aon */
 338 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
 339         .name           = "cm_core_aon",
 340         .class          = &omap44xx_prcm_hwmod_class,
 341         .flags          = HWMOD_NO_IDLEST,
 342         .prcm = {
 343                 .omap4 = {
 344                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 345                 },
 346         },
 347 };
 348
 349 /* cm_core */
 350 static struct omap_hwmod omap44xx_cm_core_hwmod = {
 351         .name           = "cm_core",
 352         .class          = &omap44xx_prcm_hwmod_class,
 353         .flags          = HWMOD_NO_IDLEST,
 354         .prcm = {
 355                 .omap4 = {
 356                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 357                 },
 358         },
 359 };
 360
 361 /* prm */
 362 static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
 363         { .name = "rst_global_warm_sw", .rst_shift = 0 },
 364         { .name = "rst_global_cold_sw", .rst_shift = 1 },
 365 };
 366
 367 static struct omap_hwmod omap44xx_prm_hwmod = {
 368         .name           = "prm",
 369         .class          = &omap44xx_prcm_hwmod_class,
 370         .rst_lines      = omap44xx_prm_resets,
 371         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
 372 };
 373
 374 /*
 375  * 'scrm' class
 376  * system clock and reset manager
 377  */
 378
 379 static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
 380         .name   = "scrm",
 381 };
 382
 383 /* scrm */
 384 static struct omap_hwmod omap44xx_scrm_hwmod = {
 385         .name           = "scrm",
 386         .class          = &omap44xx_scrm_hwmod_class,
 387         .clkdm_name     = "l4_wkup_clkdm",
 388         .prcm = {
 389                 .omap4 = {
 390                         .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 391                 },
 392         },
 393 };
 394
 395 /*
 396  * 'sl2if' class
 397  * shared level 2 memory interface
 398  */
 399
 400 static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
 401         .name   = "sl2if",
 402 };
 403
 404 /* sl2if */
 405 static struct omap_hwmod omap44xx_sl2if_hwmod = {
 406         .name           = "sl2if",
 407         .class          = &omap44xx_sl2if_hwmod_class,
 408         .clkdm_name     = "ivahd_clkdm",
 409         .prcm = {
 410                 .omap4 = {
 411                         .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
 412                         .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
 413                         .modulemode   = MODULEMODE_HWCTRL,
 414                 },
 415         },
 416 };
 417
 418 /*
 419  * interfaces
 420  */
 421
 422 /* l3_main_3 -> l3_instr */
 423 static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
 424         .master         = &omap44xx_l3_main_3_hwmod,
 425         .slave          = &omap44xx_l3_instr_hwmod,
 426         .clk            = "l3_div_ck",
 427         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 428 };
 429
 430 /* ocp_wp_noc -> l3_instr */
 431 static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
 432         .master         = &omap44xx_ocp_wp_noc_hwmod,
 433         .slave          = &omap44xx_l3_instr_hwmod,
 434         .clk            = "l3_div_ck",
 435         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 436 };
 437
 438 /* l3_main_2 -> l3_main_1 */
 439 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
 440         .master         = &omap44xx_l3_main_2_hwmod,
 441         .slave          = &omap44xx_l3_main_1_hwmod,
 442         .clk            = "l3_div_ck",
 443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 444 };
 445
 446 /* l4_cfg -> l3_main_1 */
 447 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
 448         .master         = &omap44xx_l4_cfg_hwmod,
 449         .slave          = &omap44xx_l3_main_1_hwmod,
 450         .clk            = "l4_div_ck",
 451         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 452 };
 453
 454 /* mpu -> l3_main_1 */
 455 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
 456         .master         = &omap44xx_mpu_hwmod,
 457         .slave          = &omap44xx_l3_main_1_hwmod,
 458         .clk            = "l3_div_ck",
 459         .user           = OCP_USER_MPU,
 460 };
 461
 462 /* debugss -> l3_main_2 */
 463 static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
 464         .master         = &omap44xx_debugss_hwmod,
 465         .slave          = &omap44xx_l3_main_2_hwmod,
 466         .clk            = "dbgclk_mux_ck",
 467         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 468 };
 469
 470 /* l3_main_1 -> l3_main_2 */
 471 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
 472         .master         = &omap44xx_l3_main_1_hwmod,
 473         .slave          = &omap44xx_l3_main_2_hwmod,
 474         .clk            = "l3_div_ck",
 475         .user           = OCP_USER_MPU,
 476 };
 477
 478 /* l4_cfg -> l3_main_2 */
 479 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
 480         .master         = &omap44xx_l4_cfg_hwmod,
 481         .slave          = &omap44xx_l3_main_2_hwmod,
 482         .clk            = "l4_div_ck",
 483         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 484 };
 485
 486 /* l3_main_1 -> l3_main_3 */
 487 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
 488         .master         = &omap44xx_l3_main_1_hwmod,
 489         .slave          = &omap44xx_l3_main_3_hwmod,
 490         .clk            = "l3_div_ck",
 491         .user           = OCP_USER_MPU,
 492 };
 493
 494 /* l3_main_2 -> l3_main_3 */
 495 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
 496         .master         = &omap44xx_l3_main_2_hwmod,
 497         .slave          = &omap44xx_l3_main_3_hwmod,
 498         .clk            = "l3_div_ck",
 499         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 500 };
 501
 502 /* l4_cfg -> l3_main_3 */
 503 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
 504         .master         = &omap44xx_l4_cfg_hwmod,
 505         .slave          = &omap44xx_l3_main_3_hwmod,
 506         .clk            = "l4_div_ck",
 507         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 508 };
 509
 510 /* l3_main_1 -> l4_cfg */
 511 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
 512         .master         = &omap44xx_l3_main_1_hwmod,
 513         .slave          = &omap44xx_l4_cfg_hwmod,
 514         .clk            = "l3_div_ck",
 515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 516 };
 517
 518 /* l3_main_2 -> l4_per */
 519 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
 520         .master         = &omap44xx_l3_main_2_hwmod,
 521         .slave          = &omap44xx_l4_per_hwmod,
 522         .clk            = "l3_div_ck",
 523         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 524 };
 525
 526 /* l4_cfg -> l4_wkup */
 527 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
 528         .master         = &omap44xx_l4_cfg_hwmod,
 529         .slave          = &omap44xx_l4_wkup_hwmod,
 530         .clk            = "l4_div_ck",
 531         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 532 };
 533
 534 /* mpu -> mpu_private */
 535 static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
 536         .master         = &omap44xx_mpu_hwmod,
 537         .slave          = &omap44xx_mpu_private_hwmod,
 538         .clk            = "l3_div_ck",
 539         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 540 };
 541
 542 /* l4_cfg -> ocp_wp_noc */
 543 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
 544         .master         = &omap44xx_l4_cfg_hwmod,
 545         .slave          = &omap44xx_ocp_wp_noc_hwmod,
 546         .clk            = "l4_div_ck",
 547         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 548 };
 549
 550 /* l3_instr -> debugss */
 551 static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
 552         .master         = &omap44xx_l3_instr_hwmod,
 553         .slave          = &omap44xx_debugss_hwmod,
 554         .clk            = "l3_div_ck",
 555         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 556 };
 557
 558 /* l3_main_2 -> ocmc_ram */
 559 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
 560         .master         = &omap44xx_l3_main_2_hwmod,
 561         .slave          = &omap44xx_ocmc_ram_hwmod,
 562         .clk            = "l3_div_ck",
 563         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 564 };
 565
 566 /* mpu_private -> prcm_mpu */
 567 static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
 568         .master         = &omap44xx_mpu_private_hwmod,
 569         .slave          = &omap44xx_prcm_mpu_hwmod,
 570         .clk            = "l3_div_ck",
 571         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 572 };
 573
 574 /* l4_wkup -> cm_core_aon */
 575 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
 576         .master         = &omap44xx_l4_wkup_hwmod,
 577         .slave          = &omap44xx_cm_core_aon_hwmod,
 578         .clk            = "l4_wkup_clk_mux_ck",
 579         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 580 };
 581
 582 /* l4_cfg -> cm_core */
 583 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
 584         .master         = &omap44xx_l4_cfg_hwmod,
 585         .slave          = &omap44xx_cm_core_hwmod,
 586         .clk            = "l4_div_ck",
 587         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 588 };
 589
 590 /* l4_wkup -> prm */
 591 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
 592         .master         = &omap44xx_l4_wkup_hwmod,
 593         .slave          = &omap44xx_prm_hwmod,
 594         .clk            = "l4_wkup_clk_mux_ck",
 595         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 596 };
 597
 598 /* l4_wkup -> scrm */
 599 static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
 600         .master         = &omap44xx_l4_wkup_hwmod,
 601         .slave          = &omap44xx_scrm_hwmod,
 602         .clk            = "l4_wkup_clk_mux_ck",
 603         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 604 };
 605
 606 /* l3_main_2 -> sl2if */
 607 static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
 608         .master         = &omap44xx_l3_main_2_hwmod,
 609         .slave          = &omap44xx_sl2if_hwmod,
 610         .clk            = "l3_div_ck",
 611         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 612 };
 613
 614 /* mpu -> emif1 */
 615 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
 616         .master         = &omap44xx_mpu_hwmod,
 617         .slave          = &omap44xx_emif1_hwmod,
 618         .clk            = "l3_div_ck",
 619         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 620 };
 621
 622 /* mpu -> emif2 */
 623 static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
 624         .master         = &omap44xx_mpu_hwmod,
 625         .slave          = &omap44xx_emif2_hwmod,
 626         .clk            = "l3_div_ck",
 627         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 628 };
 629
 630 static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 631         &omap44xx_l3_main_3__l3_instr,
 632         &omap44xx_ocp_wp_noc__l3_instr,
 633         &omap44xx_l3_main_2__l3_main_1,
 634         &omap44xx_l4_cfg__l3_main_1,
 635         &omap44xx_mpu__l3_main_1,
 636         &omap44xx_debugss__l3_main_2,
 637         &omap44xx_l3_main_1__l3_main_2,
 638         &omap44xx_l4_cfg__l3_main_2,
 639         &omap44xx_l3_main_1__l3_main_3,
 640         &omap44xx_l3_main_2__l3_main_3,
 641         &omap44xx_l4_cfg__l3_main_3,
 642         &omap44xx_l3_main_1__l4_cfg,
 643         &omap44xx_l3_main_2__l4_per,
 644         &omap44xx_l4_cfg__l4_wkup,
 645         &omap44xx_mpu__mpu_private,
 646         &omap44xx_l4_cfg__ocp_wp_noc,
 647         &omap44xx_l3_instr__debugss,
 648         &omap44xx_l3_main_2__ocmc_ram,
 649         &omap44xx_mpu_private__prcm_mpu,
 650         &omap44xx_l4_wkup__cm_core_aon,
 651         &omap44xx_l4_cfg__cm_core,
 652         &omap44xx_l4_wkup__prm,
 653         &omap44xx_l4_wkup__scrm,
 654         /* &omap44xx_l3_main_2__sl2if, */
 655         &omap44xx_mpu__emif1,
 656         &omap44xx_mpu__emif2,
 657         NULL,
 658 };
 659
 660 int __init omap44xx_hwmod_init(void)
 661 {
 662         omap_hwmod_init();
 663         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
 664 }
 665