arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17 #include <plat/omap_hwmod.h>
  18 #include <mach/irqs.h>
  19 #include <plat/cpu.h>
  20 #include <plat/dma.h>
  21 #include <plat/serial.h>
  22 #include <plat/l3_3xxx.h>
  23 #include <plat/l4_3xxx.h>
  24 #include <plat/i2c.h>
  25 #include <plat/gpio.h>
  26 #include <plat/mmc.h>
  27 #include <plat/mcbsp.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod_common_data.h"
  32
  33 #include "smartreflex.h"
  34 #include "prm-regbits-34xx.h"
  35 #include "cm-regbits-34xx.h"
  36 #include "wd_timer.h"
  37 #include <mach/am35xx.h>
  38
  39 /*
  40  * OMAP3xxx hardware module integration data
  41  *
  42  * All of the data in this section should be autogeneratable from the
  43  * TI hardware database or other technical documentation.  Data that
  44  * is driver-specific or driver-kernel integration-specific belongs
  45  * elsewhere.
  46  */
  47
  48 /*
  49  * IP blocks
  50  */
  51
  52 /* L3 */
  53 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  54         { .irq = INT_34XX_L3_DBG_IRQ },
  55         { .irq = INT_34XX_L3_APP_IRQ },
  56         { .irq = -1 }
  57 };
  58
  59 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  60         .name           = "l3_main",
  61         .class          = &l3_hwmod_class,
  62         .mpu_irqs       = omap3xxx_l3_main_irqs,
  63         .flags          = HWMOD_NO_IDLEST,
  64 };
  65
  66 /* L4 CORE */
  67 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  68         .name           = "l4_core",
  69         .class          = &l4_hwmod_class,
  70         .flags          = HWMOD_NO_IDLEST,
  71 };
  72
  73 /* L4 PER */
  74 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  75         .name           = "l4_per",
  76         .class          = &l4_hwmod_class,
  77         .flags          = HWMOD_NO_IDLEST,
  78 };
  79
  80 /* L4 WKUP */
  81 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  82         .name           = "l4_wkup",
  83         .class          = &l4_hwmod_class,
  84         .flags          = HWMOD_NO_IDLEST,
  85 };
  86
  87 /* L4 SEC */
  88 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  89         .name           = "l4_sec",
  90         .class          = &l4_hwmod_class,
  91         .flags          = HWMOD_NO_IDLEST,
  92 };
  93
  94 /* MPU */
  95 static struct omap_hwmod omap3xxx_mpu_hwmod = {
  96         .name           = "mpu",
  97         .class          = &mpu_hwmod_class,
  98         .main_clk       = "arm_fck",
  99 };
 100
 101 /* IVA2 (IVA2) */
 102 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 103         { .name = "logic", .rst_shift = 0 },
 104         { .name = "seq0", .rst_shift = 1 },
 105         { .name = "seq1", .rst_shift = 2 },
 106 };
 107
 108 static struct omap_hwmod omap3xxx_iva_hwmod = {
 109         .name           = "iva",
 110         .class          = &iva_hwmod_class,
 111         .clkdm_name     = "iva2_clkdm",
 112         .rst_lines      = omap3xxx_iva_resets,
 113         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 114         .main_clk       = "iva2_ck",
 115 };
 116
 117 /* timer class */
 118 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 119         .rev_offs       = 0x0000,
 120         .sysc_offs      = 0x0010,
 121         .syss_offs      = 0x0014,
 122         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 123                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 124                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 125         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 126         .sysc_fields    = &omap_hwmod_sysc_type1,
 127 };
 128
 129 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 130         .name = "timer",
 131         .sysc = &omap3xxx_timer_1ms_sysc,
 132         .rev = OMAP_TIMER_IP_VERSION_1,
 133 };
 134
 135 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 136         .rev_offs       = 0x0000,
 137         .sysc_offs      = 0x0010,
 138         .syss_offs      = 0x0014,
 139         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 140                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 141         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 142         .sysc_fields    = &omap_hwmod_sysc_type1,
 143 };
 144
 145 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 146         .name = "timer",
 147         .sysc = &omap3xxx_timer_sysc,
 148         .rev =  OMAP_TIMER_IP_VERSION_1,
 149 };
 150
 151 /* secure timers dev attribute */
 152 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 153         .timer_capability       = OMAP_TIMER_SECURE,
 154 };
 155
 156 /* always-on timers dev attribute */
 157 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 158         .timer_capability       = OMAP_TIMER_ALWON,
 159 };
 160
 161 /* pwm timers dev attribute */
 162 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 163         .timer_capability       = OMAP_TIMER_HAS_PWM,
 164 };
 165
 166 /* timer1 */
 167 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 168         .name           = "timer1",
 169         .mpu_irqs       = omap2_timer1_mpu_irqs,
 170         .main_clk       = "gpt1_fck",
 171         .prcm           = {
 172                 .omap2 = {
 173                         .prcm_reg_id = 1,
 174                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 175                         .module_offs = WKUP_MOD,
 176                         .idlest_reg_id = 1,
 177                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 178                 },
 179         },
 180         .dev_attr       = &capability_alwon_dev_attr,
 181         .class          = &omap3xxx_timer_1ms_hwmod_class,
 182 };
 183
 184 /* timer2 */
 185 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 186         .name           = "timer2",
 187         .mpu_irqs       = omap2_timer2_mpu_irqs,
 188         .main_clk       = "gpt2_fck",
 189         .prcm           = {
 190                 .omap2 = {
 191                         .prcm_reg_id = 1,
 192                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 193                         .module_offs = OMAP3430_PER_MOD,
 194                         .idlest_reg_id = 1,
 195                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 196                 },
 197         },
 198         .dev_attr       = &capability_alwon_dev_attr,
 199         .class          = &omap3xxx_timer_1ms_hwmod_class,
 200 };
 201
 202 /* timer3 */
 203 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 204         .name           = "timer3",
 205         .mpu_irqs       = omap2_timer3_mpu_irqs,
 206         .main_clk       = "gpt3_fck",
 207         .prcm           = {
 208                 .omap2 = {
 209                         .prcm_reg_id = 1,
 210                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 211                         .module_offs = OMAP3430_PER_MOD,
 212                         .idlest_reg_id = 1,
 213                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 214                 },
 215         },
 216         .dev_attr       = &capability_alwon_dev_attr,
 217         .class          = &omap3xxx_timer_hwmod_class,
 218 };
 219
 220 /* timer4 */
 221 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 222         .name           = "timer4",
 223         .mpu_irqs       = omap2_timer4_mpu_irqs,
 224         .main_clk       = "gpt4_fck",
 225         .prcm           = {
 226                 .omap2 = {
 227                         .prcm_reg_id = 1,
 228                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 229                         .module_offs = OMAP3430_PER_MOD,
 230                         .idlest_reg_id = 1,
 231                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 232                 },
 233         },
 234         .dev_attr       = &capability_alwon_dev_attr,
 235         .class          = &omap3xxx_timer_hwmod_class,
 236 };
 237
 238 /* timer5 */
 239 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 240         .name           = "timer5",
 241         .mpu_irqs       = omap2_timer5_mpu_irqs,
 242         .main_clk       = "gpt5_fck",
 243         .prcm           = {
 244                 .omap2 = {
 245                         .prcm_reg_id = 1,
 246                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 247                         .module_offs = OMAP3430_PER_MOD,
 248                         .idlest_reg_id = 1,
 249                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 250                 },
 251         },
 252         .dev_attr       = &capability_alwon_dev_attr,
 253         .class          = &omap3xxx_timer_hwmod_class,
 254 };
 255
 256 /* timer6 */
 257 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 258         .name           = "timer6",
 259         .mpu_irqs       = omap2_timer6_mpu_irqs,
 260         .main_clk       = "gpt6_fck",
 261         .prcm           = {
 262                 .omap2 = {
 263                         .prcm_reg_id = 1,
 264                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 265                         .module_offs = OMAP3430_PER_MOD,
 266                         .idlest_reg_id = 1,
 267                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 268                 },
 269         },
 270         .dev_attr       = &capability_alwon_dev_attr,
 271         .class          = &omap3xxx_timer_hwmod_class,
 272 };
 273
 274 /* timer7 */
 275 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 276         .name           = "timer7",
 277         .mpu_irqs       = omap2_timer7_mpu_irqs,
 278         .main_clk       = "gpt7_fck",
 279         .prcm           = {
 280                 .omap2 = {
 281                         .prcm_reg_id = 1,
 282                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 283                         .module_offs = OMAP3430_PER_MOD,
 284                         .idlest_reg_id = 1,
 285                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 286                 },
 287         },
 288         .dev_attr       = &capability_alwon_dev_attr,
 289         .class          = &omap3xxx_timer_hwmod_class,
 290 };
 291
 292 /* timer8 */
 293 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 294         .name           = "timer8",
 295         .mpu_irqs       = omap2_timer8_mpu_irqs,
 296         .main_clk       = "gpt8_fck",
 297         .prcm           = {
 298                 .omap2 = {
 299                         .prcm_reg_id = 1,
 300                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 301                         .module_offs = OMAP3430_PER_MOD,
 302                         .idlest_reg_id = 1,
 303                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 304                 },
 305         },
 306         .dev_attr       = &capability_pwm_dev_attr,
 307         .class          = &omap3xxx_timer_hwmod_class,
 308 };
 309
 310 /* timer9 */
 311 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 312         .name           = "timer9",
 313         .mpu_irqs       = omap2_timer9_mpu_irqs,
 314         .main_clk       = "gpt9_fck",
 315         .prcm           = {
 316                 .omap2 = {
 317                         .prcm_reg_id = 1,
 318                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 319                         .module_offs = OMAP3430_PER_MOD,
 320                         .idlest_reg_id = 1,
 321                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 322                 },
 323         },
 324         .dev_attr       = &capability_pwm_dev_attr,
 325         .class          = &omap3xxx_timer_hwmod_class,
 326 };
 327
 328 /* timer10 */
 329 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 330         .name           = "timer10",
 331         .mpu_irqs       = omap2_timer10_mpu_irqs,
 332         .main_clk       = "gpt10_fck",
 333         .prcm           = {
 334                 .omap2 = {
 335                         .prcm_reg_id = 1,
 336                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 337                         .module_offs = CORE_MOD,
 338                         .idlest_reg_id = 1,
 339                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 340                 },
 341         },
 342         .dev_attr       = &capability_pwm_dev_attr,
 343         .class          = &omap3xxx_timer_1ms_hwmod_class,
 344 };
 345
 346 /* timer11 */
 347 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 348         .name           = "timer11",
 349         .mpu_irqs       = omap2_timer11_mpu_irqs,
 350         .main_clk       = "gpt11_fck",
 351         .prcm           = {
 352                 .omap2 = {
 353                         .prcm_reg_id = 1,
 354                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 355                         .module_offs = CORE_MOD,
 356                         .idlest_reg_id = 1,
 357                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 358                 },
 359         },
 360         .dev_attr       = &capability_pwm_dev_attr,
 361         .class          = &omap3xxx_timer_hwmod_class,
 362 };
 363
 364 /* timer12 */
 365 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 366         { .irq = 95, },
 367         { .irq = -1 }
 368 };
 369
 370 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 371         .name           = "timer12",
 372         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 373         .main_clk       = "gpt12_fck",
 374         .prcm           = {
 375                 .omap2 = {
 376                         .prcm_reg_id = 1,
 377                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 378                         .module_offs = WKUP_MOD,
 379                         .idlest_reg_id = 1,
 380                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 381                 },
 382         },
 383         .dev_attr       = &capability_secure_dev_attr,
 384         .class          = &omap3xxx_timer_hwmod_class,
 385 };
 386
 387 /*
 388  * 'wd_timer' class
 389  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 390  * overflow condition
 391  */
 392
 393 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 394         .rev_offs       = 0x0000,
 395         .sysc_offs      = 0x0010,
 396         .syss_offs      = 0x0014,
 397         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 398                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 399                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 400                            SYSS_HAS_RESET_STATUS),
 401         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 402         .sysc_fields    = &omap_hwmod_sysc_type1,
 403 };
 404
 405 /* I2C common */
 406 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 407         .rev_offs       = 0x00,
 408         .sysc_offs      = 0x20,
 409         .syss_offs      = 0x10,
 410         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 411                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 412                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 413         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 414         .clockact       = CLOCKACT_TEST_ICLK,
 415         .sysc_fields    = &omap_hwmod_sysc_type1,
 416 };
 417
 418 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 419         .name           = "wd_timer",
 420         .sysc           = &omap3xxx_wd_timer_sysc,
 421         .pre_shutdown   = &omap2_wd_timer_disable,
 422         .reset          = &omap2_wd_timer_reset,
 423 };
 424
 425 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 426         .name           = "wd_timer2",
 427         .class          = &omap3xxx_wd_timer_hwmod_class,
 428         .main_clk       = "wdt2_fck",
 429         .prcm           = {
 430                 .omap2 = {
 431                         .prcm_reg_id = 1,
 432                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 433                         .module_offs = WKUP_MOD,
 434                         .idlest_reg_id = 1,
 435                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 436                 },
 437         },
 438         /*
 439          * XXX: Use software supervised mode, HW supervised smartidle seems to
 440          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 441          */
 442         .flags          = HWMOD_SWSUP_SIDLE,
 443 };
 444
 445 /* UART1 */
 446 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 447         .name           = "uart1",
 448         .mpu_irqs       = omap2_uart1_mpu_irqs,
 449         .sdma_reqs      = omap2_uart1_sdma_reqs,
 450         .main_clk       = "uart1_fck",
 451         .prcm           = {
 452                 .omap2 = {
 453                         .module_offs = CORE_MOD,
 454                         .prcm_reg_id = 1,
 455                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 456                         .idlest_reg_id = 1,
 457                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 458                 },
 459         },
 460         .class          = &omap2_uart_class,
 461 };
 462
 463 /* UART2 */
 464 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 465         .name           = "uart2",
 466         .mpu_irqs       = omap2_uart2_mpu_irqs,
 467         .sdma_reqs      = omap2_uart2_sdma_reqs,
 468         .main_clk       = "uart2_fck",
 469         .prcm           = {
 470                 .omap2 = {
 471                         .module_offs = CORE_MOD,
 472                         .prcm_reg_id = 1,
 473                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 474                         .idlest_reg_id = 1,
 475                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 476                 },
 477         },
 478         .class          = &omap2_uart_class,
 479 };
 480
 481 /* UART3 */
 482 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 483         .name           = "uart3",
 484         .mpu_irqs       = omap2_uart3_mpu_irqs,
 485         .sdma_reqs      = omap2_uart3_sdma_reqs,
 486         .main_clk       = "uart3_fck",
 487         .prcm           = {
 488                 .omap2 = {
 489                         .module_offs = OMAP3430_PER_MOD,
 490                         .prcm_reg_id = 1,
 491                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 492                         .idlest_reg_id = 1,
 493                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 494                 },
 495         },
 496         .class          = &omap2_uart_class,
 497 };
 498
 499 /* UART4 */
 500 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 501         { .irq = INT_36XX_UART4_IRQ, },
 502         { .irq = -1 }
 503 };
 504
 505 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 506         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 507         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 508         { .dma_req = -1 }
 509 };
 510
 511 static struct omap_hwmod omap36xx_uart4_hwmod = {
 512         .name           = "uart4",
 513         .mpu_irqs       = uart4_mpu_irqs,
 514         .sdma_reqs      = uart4_sdma_reqs,
 515         .main_clk       = "uart4_fck",
 516         .prcm           = {
 517                 .omap2 = {
 518                         .module_offs = OMAP3430_PER_MOD,
 519                         .prcm_reg_id = 1,
 520                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 521                         .idlest_reg_id = 1,
 522                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 523                 },
 524         },
 525         .class          = &omap2_uart_class,
 526 };
 527
 528 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 529         { .irq = INT_35XX_UART4_IRQ, },
 530         { .irq = -1 }
 531 };
 532
 533 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 534         { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
 535         { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
 536         { .dma_req = -1 }
 537 };
 538
 539 /*
 540  * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
 541  * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
 542  * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
 543  * should not be needed.  The functional clock structure of the AM35xx
 544  * UART4 is extremely unclear and opaque; it is unclear what the role
 545  * of uart1/2_fck is for the UART4.  Any clarification from either
 546  * empirical testing or the AM3505/3517 hardware designers would be
 547  * most welcome.
 548  */
 549 static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
 550         { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 551 };
 552
 553 static struct omap_hwmod am35xx_uart4_hwmod = {
 554         .name           = "uart4",
 555         .mpu_irqs       = am35xx_uart4_mpu_irqs,
 556         .sdma_reqs      = am35xx_uart4_sdma_reqs,
 557         .main_clk       = "uart4_fck",
 558         .prcm           = {
 559                 .omap2 = {
 560                         .module_offs = CORE_MOD,
 561                         .prcm_reg_id = 1,
 562                         .module_bit = AM35XX_EN_UART4_SHIFT,
 563                         .idlest_reg_id = 1,
 564                         .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 565                 },
 566         },
 567         .opt_clks       = am35xx_uart4_opt_clks,
 568         .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
 569         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 570         .class          = &omap2_uart_class,
 571 };
 572
 573 static struct omap_hwmod_class i2c_class = {
 574         .name   = "i2c",
 575         .sysc   = &i2c_sysc,
 576         .rev    = OMAP_I2C_IP_VERSION_1,
 577         .reset  = &omap_i2c_reset,
 578 };
 579
 580 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 581         { .name = "dispc", .dma_req = 5 },
 582         { .name = "dsi1", .dma_req = 74 },
 583         { .dma_req = -1 }
 584 };
 585
 586 /* dss */
 587 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 588         /*
 589          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 590          * driver does not use these clocks.
 591          */
 592         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 593         { .role = "tv_clk", .clk = "dss_tv_fck" },
 594         /* required only on OMAP3430 */
 595         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 596 };
 597
 598 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 599         .name           = "dss_core",
 600         .class          = &omap2_dss_hwmod_class,
 601         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 602         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 603         .prcm           = {
 604                 .omap2 = {
 605                         .prcm_reg_id = 1,
 606                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 607                         .module_offs = OMAP3430_DSS_MOD,
 608                         .idlest_reg_id = 1,
 609                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 610                 },
 611         },
 612         .opt_clks       = dss_opt_clks,
 613         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 614         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 615 };
 616
 617 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 618         .name           = "dss_core",
 619         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 620         .class          = &omap2_dss_hwmod_class,
 621         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 622         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 623         .prcm           = {
 624                 .omap2 = {
 625                         .prcm_reg_id = 1,
 626                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 627                         .module_offs = OMAP3430_DSS_MOD,
 628                         .idlest_reg_id = 1,
 629                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 630                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 631                 },
 632         },
 633         .opt_clks       = dss_opt_clks,
 634         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 635 };
 636
 637 /*
 638  * 'dispc' class
 639  * display controller
 640  */
 641
 642 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 643         .rev_offs       = 0x0000,
 644         .sysc_offs      = 0x0010,
 645         .syss_offs      = 0x0014,
 646         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 647                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 648                            SYSC_HAS_ENAWAKEUP),
 649         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 650                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 651         .sysc_fields    = &omap_hwmod_sysc_type1,
 652 };
 653
 654 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 655         .name   = "dispc",
 656         .sysc   = &omap3_dispc_sysc,
 657 };
 658
 659 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 660         .name           = "dss_dispc",
 661         .class          = &omap3_dispc_hwmod_class,
 662         .mpu_irqs       = omap2_dispc_irqs,
 663         .main_clk       = "dss1_alwon_fck",
 664         .prcm           = {
 665                 .omap2 = {
 666                         .prcm_reg_id = 1,
 667                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 668                         .module_offs = OMAP3430_DSS_MOD,
 669                 },
 670         },
 671         .flags          = HWMOD_NO_IDLEST,
 672         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 673 };
 674
 675 /*
 676  * 'dsi' class
 677  * display serial interface controller
 678  */
 679
 680 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 681         .name = "dsi",
 682 };
 683
 684 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 685         { .irq = 25 },
 686         { .irq = -1 }
 687 };
 688
 689 /* dss_dsi1 */
 690 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 691         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 692 };
 693
 694 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 695         .name           = "dss_dsi1",
 696         .class          = &omap3xxx_dsi_hwmod_class,
 697         .mpu_irqs       = omap3xxx_dsi1_irqs,
 698         .main_clk       = "dss1_alwon_fck",
 699         .prcm           = {
 700                 .omap2 = {
 701                         .prcm_reg_id = 1,
 702                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 703                         .module_offs = OMAP3430_DSS_MOD,
 704                 },
 705         },
 706         .opt_clks       = dss_dsi1_opt_clks,
 707         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 708         .flags          = HWMOD_NO_IDLEST,
 709 };
 710
 711 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 712         { .role = "ick", .clk = "dss_ick" },
 713 };
 714
 715 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 716         .name           = "dss_rfbi",
 717         .class          = &omap2_rfbi_hwmod_class,
 718         .main_clk       = "dss1_alwon_fck",
 719         .prcm           = {
 720                 .omap2 = {
 721                         .prcm_reg_id = 1,
 722                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 723                         .module_offs = OMAP3430_DSS_MOD,
 724                 },
 725         },
 726         .opt_clks       = dss_rfbi_opt_clks,
 727         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 728         .flags          = HWMOD_NO_IDLEST,
 729 };
 730
 731 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 732         /* required only on OMAP3430 */
 733         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 734 };
 735
 736 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 737         .name           = "dss_venc",
 738         .class          = &omap2_venc_hwmod_class,
 739         .main_clk       = "dss_tv_fck",
 740         .prcm           = {
 741                 .omap2 = {
 742                         .prcm_reg_id = 1,
 743                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 744                         .module_offs = OMAP3430_DSS_MOD,
 745                 },
 746         },
 747         .opt_clks       = dss_venc_opt_clks,
 748         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 749         .flags          = HWMOD_NO_IDLEST,
 750 };
 751
 752 /* I2C1 */
 753 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 754         .fifo_depth     = 8, /* bytes */
 755         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 756                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 757                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 758 };
 759
 760 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 761         .name           = "i2c1",
 762         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 763         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 764         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 765         .main_clk       = "i2c1_fck",
 766         .prcm           = {
 767                 .omap2 = {
 768                         .module_offs = CORE_MOD,
 769                         .prcm_reg_id = 1,
 770                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 771                         .idlest_reg_id = 1,
 772                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 773                 },
 774         },
 775         .class          = &i2c_class,
 776         .dev_attr       = &i2c1_dev_attr,
 777 };
 778
 779 /* I2C2 */
 780 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 781         .fifo_depth     = 8, /* bytes */
 782         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 783                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 784                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 785 };
 786
 787 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 788         .name           = "i2c2",
 789         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 790         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 791         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 792         .main_clk       = "i2c2_fck",
 793         .prcm           = {
 794                 .omap2 = {
 795                         .module_offs = CORE_MOD,
 796                         .prcm_reg_id = 1,
 797                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 798                         .idlest_reg_id = 1,
 799                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 800                 },
 801         },
 802         .class          = &i2c_class,
 803         .dev_attr       = &i2c2_dev_attr,
 804 };
 805
 806 /* I2C3 */
 807 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 808         .fifo_depth     = 64, /* bytes */
 809         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 810                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 811                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 812 };
 813
 814 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 815         { .irq = INT_34XX_I2C3_IRQ, },
 816         { .irq = -1 }
 817 };
 818
 819 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 820         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
 821         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
 822         { .dma_req = -1 }
 823 };
 824
 825 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 826         .name           = "i2c3",
 827         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 828         .mpu_irqs       = i2c3_mpu_irqs,
 829         .sdma_reqs      = i2c3_sdma_reqs,
 830         .main_clk       = "i2c3_fck",
 831         .prcm           = {
 832                 .omap2 = {
 833                         .module_offs = CORE_MOD,
 834                         .prcm_reg_id = 1,
 835                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 836                         .idlest_reg_id = 1,
 837                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 838                 },
 839         },
 840         .class          = &i2c_class,
 841         .dev_attr       = &i2c3_dev_attr,
 842 };
 843
 844 /*
 845  * 'gpio' class
 846  * general purpose io module
 847  */
 848
 849 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 850         .rev_offs       = 0x0000,
 851         .sysc_offs      = 0x0010,
 852         .syss_offs      = 0x0014,
 853         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 854                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 855                            SYSS_HAS_RESET_STATUS),
 856         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 857         .sysc_fields    = &omap_hwmod_sysc_type1,
 858 };
 859
 860 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 861         .name = "gpio",
 862         .sysc = &omap3xxx_gpio_sysc,
 863         .rev = 1,
 864 };
 865
 866 /* gpio_dev_attr */
 867 static struct omap_gpio_dev_attr gpio_dev_attr = {
 868         .bank_width = 32,
 869         .dbck_flag = true,
 870 };
 871
 872 /* gpio1 */
 873 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 874         { .role = "dbclk", .clk = "gpio1_dbck", },
 875 };
 876
 877 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 878         .name           = "gpio1",
 879         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 880         .mpu_irqs       = omap2_gpio1_irqs,
 881         .main_clk       = "gpio1_ick",
 882         .opt_clks       = gpio1_opt_clks,
 883         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 884         .prcm           = {
 885                 .omap2 = {
 886                         .prcm_reg_id = 1,
 887                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 888                         .module_offs = WKUP_MOD,
 889                         .idlest_reg_id = 1,
 890                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 891                 },
 892         },
 893         .class          = &omap3xxx_gpio_hwmod_class,
 894         .dev_attr       = &gpio_dev_attr,
 895 };
 896
 897 /* gpio2 */
 898 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 899         { .role = "dbclk", .clk = "gpio2_dbck", },
 900 };
 901
 902 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 903         .name           = "gpio2",
 904         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 905         .mpu_irqs       = omap2_gpio2_irqs,
 906         .main_clk       = "gpio2_ick",
 907         .opt_clks       = gpio2_opt_clks,
 908         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 909         .prcm           = {
 910                 .omap2 = {
 911                         .prcm_reg_id = 1,
 912                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 913                         .module_offs = OMAP3430_PER_MOD,
 914                         .idlest_reg_id = 1,
 915                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 916                 },
 917         },
 918         .class          = &omap3xxx_gpio_hwmod_class,
 919         .dev_attr       = &gpio_dev_attr,
 920 };
 921
 922 /* gpio3 */
 923 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 924         { .role = "dbclk", .clk = "gpio3_dbck", },
 925 };
 926
 927 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 928         .name           = "gpio3",
 929         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 930         .mpu_irqs       = omap2_gpio3_irqs,
 931         .main_clk       = "gpio3_ick",
 932         .opt_clks       = gpio3_opt_clks,
 933         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 934         .prcm           = {
 935                 .omap2 = {
 936                         .prcm_reg_id = 1,
 937                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 938                         .module_offs = OMAP3430_PER_MOD,
 939                         .idlest_reg_id = 1,
 940                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 941                 },
 942         },
 943         .class          = &omap3xxx_gpio_hwmod_class,
 944         .dev_attr       = &gpio_dev_attr,
 945 };
 946
 947 /* gpio4 */
 948 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 949         { .role = "dbclk", .clk = "gpio4_dbck", },
 950 };
 951
 952 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 953         .name           = "gpio4",
 954         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 955         .mpu_irqs       = omap2_gpio4_irqs,
 956         .main_clk       = "gpio4_ick",
 957         .opt_clks       = gpio4_opt_clks,
 958         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 959         .prcm           = {
 960                 .omap2 = {
 961                         .prcm_reg_id = 1,
 962                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
 963                         .module_offs = OMAP3430_PER_MOD,
 964                         .idlest_reg_id = 1,
 965                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
 966                 },
 967         },
 968         .class          = &omap3xxx_gpio_hwmod_class,
 969         .dev_attr       = &gpio_dev_attr,
 970 };
 971
 972 /* gpio5 */
 973 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
 974         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
 975         { .irq = -1 }
 976 };
 977
 978 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 979         { .role = "dbclk", .clk = "gpio5_dbck", },
 980 };
 981
 982 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 983         .name           = "gpio5",
 984         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 985         .mpu_irqs       = omap3xxx_gpio5_irqs,
 986         .main_clk       = "gpio5_ick",
 987         .opt_clks       = gpio5_opt_clks,
 988         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 989         .prcm           = {
 990                 .omap2 = {
 991                         .prcm_reg_id = 1,
 992                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
 993                         .module_offs = OMAP3430_PER_MOD,
 994                         .idlest_reg_id = 1,
 995                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
 996                 },
 997         },
 998         .class          = &omap3xxx_gpio_hwmod_class,
 999         .dev_attr       = &gpio_dev_attr,
1000 };
1001
1002 /* gpio6 */
1003 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
1004         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
1005         { .irq = -1 }
1006 };
1007
1008 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1009         { .role = "dbclk", .clk = "gpio6_dbck", },
1010 };
1011
1012 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
1013         .name           = "gpio6",
1014         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1015         .mpu_irqs       = omap3xxx_gpio6_irqs,
1016         .main_clk       = "gpio6_ick",
1017         .opt_clks       = gpio6_opt_clks,
1018         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
1019         .prcm           = {
1020                 .omap2 = {
1021                         .prcm_reg_id = 1,
1022                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
1023                         .module_offs = OMAP3430_PER_MOD,
1024                         .idlest_reg_id = 1,
1025                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1026                 },
1027         },
1028         .class          = &omap3xxx_gpio_hwmod_class,
1029         .dev_attr       = &gpio_dev_attr,
1030 };
1031
1032 /* dma attributes */
1033 static struct omap_dma_dev_attr dma_dev_attr = {
1034         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1035                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1036         .lch_count = 32,
1037 };
1038
1039 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1040         .rev_offs       = 0x0000,
1041         .sysc_offs      = 0x002c,
1042         .syss_offs      = 0x0028,
1043         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1044                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1045                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1046                            SYSS_HAS_RESET_STATUS),
1047         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1048                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1049         .sysc_fields    = &omap_hwmod_sysc_type1,
1050 };
1051
1052 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1053         .name = "dma",
1054         .sysc = &omap3xxx_dma_sysc,
1055 };
1056
1057 /* dma_system */
1058 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1059         .name           = "dma",
1060         .class          = &omap3xxx_dma_hwmod_class,
1061         .mpu_irqs       = omap2_dma_system_irqs,
1062         .main_clk       = "core_l3_ick",
1063         .prcm = {
1064                 .omap2 = {
1065                         .module_offs            = CORE_MOD,
1066                         .prcm_reg_id            = 1,
1067                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1068                         .idlest_reg_id          = 1,
1069                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1070                 },
1071         },
1072         .dev_attr       = &dma_dev_attr,
1073         .flags          = HWMOD_NO_IDLEST,
1074 };
1075
1076 /*
1077  * 'mcbsp' class
1078  * multi channel buffered serial port controller
1079  */
1080
1081 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1082         .sysc_offs      = 0x008c,
1083         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1084                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1085         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1086         .sysc_fields    = &omap_hwmod_sysc_type1,
1087         .clockact       = 0x2,
1088 };
1089
1090 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1091         .name = "mcbsp",
1092         .sysc = &omap3xxx_mcbsp_sysc,
1093         .rev  = MCBSP_CONFIG_TYPE3,
1094 };
1095
1096 /* mcbsp1 */
1097 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1098         { .name = "common", .irq = 16 },
1099         { .name = "tx", .irq = 59 },
1100         { .name = "rx", .irq = 60 },
1101         { .irq = -1 }
1102 };
1103
1104 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1105         .name           = "mcbsp1",
1106         .class          = &omap3xxx_mcbsp_hwmod_class,
1107         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1108         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1109         .main_clk       = "mcbsp1_fck",
1110         .prcm           = {
1111                 .omap2 = {
1112                         .prcm_reg_id = 1,
1113                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1114                         .module_offs = CORE_MOD,
1115                         .idlest_reg_id = 1,
1116                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1117                 },
1118         },
1119 };
1120
1121 /* mcbsp2 */
1122 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1123         { .name = "common", .irq = 17 },
1124         { .name = "tx", .irq = 62 },
1125         { .name = "rx", .irq = 63 },
1126         { .irq = -1 }
1127 };
1128
1129 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1130         .sidetone       = "mcbsp2_sidetone",
1131 };
1132
1133 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1134         .name           = "mcbsp2",
1135         .class          = &omap3xxx_mcbsp_hwmod_class,
1136         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1137         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1138         .main_clk       = "mcbsp2_fck",
1139         .prcm           = {
1140                 .omap2 = {
1141                         .prcm_reg_id = 1,
1142                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1143                         .module_offs = OMAP3430_PER_MOD,
1144                         .idlest_reg_id = 1,
1145                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1146                 },
1147         },
1148         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1149 };
1150
1151 /* mcbsp3 */
1152 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1153         { .name = "common", .irq = 22 },
1154         { .name = "tx", .irq = 89 },
1155         { .name = "rx", .irq = 90 },
1156         { .irq = -1 }
1157 };
1158
1159 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1160         .sidetone       = "mcbsp3_sidetone",
1161 };
1162
1163 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1164         .name           = "mcbsp3",
1165         .class          = &omap3xxx_mcbsp_hwmod_class,
1166         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1167         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1168         .main_clk       = "mcbsp3_fck",
1169         .prcm           = {
1170                 .omap2 = {
1171                         .prcm_reg_id = 1,
1172                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1173                         .module_offs = OMAP3430_PER_MOD,
1174                         .idlest_reg_id = 1,
1175                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1176                 },
1177         },
1178         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1179 };
1180
1181 /* mcbsp4 */
1182 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1183         { .name = "common", .irq = 23 },
1184         { .name = "tx", .irq = 54 },
1185         { .name = "rx", .irq = 55 },
1186         { .irq = -1 }
1187 };
1188
1189 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1190         { .name = "rx", .dma_req = 20 },
1191         { .name = "tx", .dma_req = 19 },
1192         { .dma_req = -1 }
1193 };
1194
1195 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1196         .name           = "mcbsp4",
1197         .class          = &omap3xxx_mcbsp_hwmod_class,
1198         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1199         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1200         .main_clk       = "mcbsp4_fck",
1201         .prcm           = {
1202                 .omap2 = {
1203                         .prcm_reg_id = 1,
1204                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1205                         .module_offs = OMAP3430_PER_MOD,
1206                         .idlest_reg_id = 1,
1207                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1208                 },
1209         },
1210 };
1211
1212 /* mcbsp5 */
1213 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1214         { .name = "common", .irq = 27 },
1215         { .name = "tx", .irq = 81 },
1216         { .name = "rx", .irq = 82 },
1217         { .irq = -1 }
1218 };
1219
1220 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1221         { .name = "rx", .dma_req = 22 },
1222         { .name = "tx", .dma_req = 21 },
1223         { .dma_req = -1 }
1224 };
1225
1226 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1227         .name           = "mcbsp5",
1228         .class          = &omap3xxx_mcbsp_hwmod_class,
1229         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
1230         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
1231         .main_clk       = "mcbsp5_fck",
1232         .prcm           = {
1233                 .omap2 = {
1234                         .prcm_reg_id = 1,
1235                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1236                         .module_offs = CORE_MOD,
1237                         .idlest_reg_id = 1,
1238                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1239                 },
1240         },
1241 };
1242
1243 /* 'mcbsp sidetone' class */
1244 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1245         .sysc_offs      = 0x0010,
1246         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1247         .sysc_fields    = &omap_hwmod_sysc_type1,
1248 };
1249
1250 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1251         .name = "mcbsp_sidetone",
1252         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1253 };
1254
1255 /* mcbsp2_sidetone */
1256 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1257         { .name = "irq", .irq = 4 },
1258         { .irq = -1 }
1259 };
1260
1261 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1262         .name           = "mcbsp2_sidetone",
1263         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1264         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
1265         .main_clk       = "mcbsp2_fck",
1266         .prcm           = {
1267                 .omap2 = {
1268                         .prcm_reg_id = 1,
1269                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1270                         .module_offs = OMAP3430_PER_MOD,
1271                         .idlest_reg_id = 1,
1272                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1273                 },
1274         },
1275 };
1276
1277 /* mcbsp3_sidetone */
1278 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1279         { .name = "irq", .irq = 5 },
1280         { .irq = -1 }
1281 };
1282
1283 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1284         .name           = "mcbsp3_sidetone",
1285         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1286         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
1287         .main_clk       = "mcbsp3_fck",
1288         .prcm           = {
1289                 .omap2 = {
1290                         .prcm_reg_id = 1,
1291                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1292                         .module_offs = OMAP3430_PER_MOD,
1293                         .idlest_reg_id = 1,
1294                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1295                 },
1296         },
1297 };
1298
1299 /* SR common */
1300 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1301         .clkact_shift   = 20,
1302 };
1303
1304 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1305         .sysc_offs      = 0x24,
1306         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1307         .clockact       = CLOCKACT_TEST_ICLK,
1308         .sysc_fields    = &omap34xx_sr_sysc_fields,
1309 };
1310
1311 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1312         .name = "smartreflex",
1313         .sysc = &omap34xx_sr_sysc,
1314         .rev  = 1,
1315 };
1316
1317 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1318         .sidle_shift    = 24,
1319         .enwkup_shift   = 26,
1320 };
1321
1322 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1323         .sysc_offs      = 0x38,
1324         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1325         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1326                         SYSC_NO_CACHE),
1327         .sysc_fields    = &omap36xx_sr_sysc_fields,
1328 };
1329
1330 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1331         .name = "smartreflex",
1332         .sysc = &omap36xx_sr_sysc,
1333         .rev  = 2,
1334 };
1335
1336 /* SR1 */
1337 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1338         .sensor_voltdm_name   = "mpu_iva",
1339 };
1340
1341 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1342         { .irq = 18 },
1343         { .irq = -1 }
1344 };
1345
1346 static struct omap_hwmod omap34xx_sr1_hwmod = {
1347         .name           = "sr1",
1348         .class          = &omap34xx_smartreflex_hwmod_class,
1349         .main_clk       = "sr1_fck",
1350         .prcm           = {
1351                 .omap2 = {
1352                         .prcm_reg_id = 1,
1353                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1354                         .module_offs = WKUP_MOD,
1355                         .idlest_reg_id = 1,
1356                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1357                 },
1358         },
1359         .dev_attr       = &sr1_dev_attr,
1360         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1361         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1362 };
1363
1364 static struct omap_hwmod omap36xx_sr1_hwmod = {
1365         .name           = "sr1",
1366         .class          = &omap36xx_smartreflex_hwmod_class,
1367         .main_clk       = "sr1_fck",
1368         .prcm           = {
1369                 .omap2 = {
1370                         .prcm_reg_id = 1,
1371                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1372                         .module_offs = WKUP_MOD,
1373                         .idlest_reg_id = 1,
1374                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1375                 },
1376         },
1377         .dev_attr       = &sr1_dev_attr,
1378         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1379 };
1380
1381 /* SR2 */
1382 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1383         .sensor_voltdm_name     = "core",
1384 };
1385
1386 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1387         { .irq = 19 },
1388         { .irq = -1 }
1389 };
1390
1391 static struct omap_hwmod omap34xx_sr2_hwmod = {
1392         .name           = "sr2",
1393         .class          = &omap34xx_smartreflex_hwmod_class,
1394         .main_clk       = "sr2_fck",
1395         .prcm           = {
1396                 .omap2 = {
1397                         .prcm_reg_id = 1,
1398                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1399                         .module_offs = WKUP_MOD,
1400                         .idlest_reg_id = 1,
1401                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1402                 },
1403         },
1404         .dev_attr       = &sr2_dev_attr,
1405         .mpu_irqs       = omap3_smartreflex_core_irqs,
1406         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1407 };
1408
1409 static struct omap_hwmod omap36xx_sr2_hwmod = {
1410         .name           = "sr2",
1411         .class          = &omap36xx_smartreflex_hwmod_class,
1412         .main_clk       = "sr2_fck",
1413         .prcm           = {
1414                 .omap2 = {
1415                         .prcm_reg_id = 1,
1416                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1417                         .module_offs = WKUP_MOD,
1418                         .idlest_reg_id = 1,
1419                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1420                 },
1421         },
1422         .dev_attr       = &sr2_dev_attr,
1423         .mpu_irqs       = omap3_smartreflex_core_irqs,
1424 };
1425
1426 /*
1427  * 'mailbox' class
1428  * mailbox module allowing communication between the on-chip processors
1429  * using a queued mailbox-interrupt mechanism.
1430  */
1431
1432 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1433         .rev_offs       = 0x000,
1434         .sysc_offs      = 0x010,
1435         .syss_offs      = 0x014,
1436         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1437                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1438         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1439         .sysc_fields    = &omap_hwmod_sysc_type1,
1440 };
1441
1442 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1443         .name = "mailbox",
1444         .sysc = &omap3xxx_mailbox_sysc,
1445 };
1446
1447 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1448         { .irq = 26 },
1449         { .irq = -1 }
1450 };
1451
1452 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1453         .name           = "mailbox",
1454         .class          = &omap3xxx_mailbox_hwmod_class,
1455         .mpu_irqs       = omap3xxx_mailbox_irqs,
1456         .main_clk       = "mailboxes_ick",
1457         .prcm           = {
1458                 .omap2 = {
1459                         .prcm_reg_id = 1,
1460                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1461                         .module_offs = CORE_MOD,
1462                         .idlest_reg_id = 1,
1463                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1464                 },
1465         },
1466 };
1467
1468 /*
1469  * 'mcspi' class
1470  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1471  * bus
1472  */
1473
1474 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1475         .rev_offs       = 0x0000,
1476         .sysc_offs      = 0x0010,
1477         .syss_offs      = 0x0014,
1478         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1479                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1480                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1481         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1482         .sysc_fields    = &omap_hwmod_sysc_type1,
1483 };
1484
1485 static struct omap_hwmod_class omap34xx_mcspi_class = {
1486         .name = "mcspi",
1487         .sysc = &omap34xx_mcspi_sysc,
1488         .rev = OMAP3_MCSPI_REV,
1489 };
1490
1491 /* mcspi1 */
1492 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1493         .num_chipselect = 4,
1494 };
1495
1496 static struct omap_hwmod omap34xx_mcspi1 = {
1497         .name           = "mcspi1",
1498         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1499         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1500         .main_clk       = "mcspi1_fck",
1501         .prcm           = {
1502                 .omap2 = {
1503                         .module_offs = CORE_MOD,
1504                         .prcm_reg_id = 1,
1505                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1506                         .idlest_reg_id = 1,
1507                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1508                 },
1509         },
1510         .class          = &omap34xx_mcspi_class,
1511         .dev_attr       = &omap_mcspi1_dev_attr,
1512 };
1513
1514 /* mcspi2 */
1515 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1516         .num_chipselect = 2,
1517 };
1518
1519 static struct omap_hwmod omap34xx_mcspi2 = {
1520         .name           = "mcspi2",
1521         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1522         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1523         .main_clk       = "mcspi2_fck",
1524         .prcm           = {
1525                 .omap2 = {
1526                         .module_offs = CORE_MOD,
1527                         .prcm_reg_id = 1,
1528                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1529                         .idlest_reg_id = 1,
1530                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1531                 },
1532         },
1533         .class          = &omap34xx_mcspi_class,
1534         .dev_attr       = &omap_mcspi2_dev_attr,
1535 };
1536
1537 /* mcspi3 */
1538 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1539         { .name = "irq", .irq = 91 }, /* 91 */
1540         { .irq = -1 }
1541 };
1542
1543 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1544         { .name = "tx0", .dma_req = 15 },
1545         { .name = "rx0", .dma_req = 16 },
1546         { .name = "tx1", .dma_req = 23 },
1547         { .name = "rx1", .dma_req = 24 },
1548         { .dma_req = -1 }
1549 };
1550
1551 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1552         .num_chipselect = 2,
1553 };
1554
1555 static struct omap_hwmod omap34xx_mcspi3 = {
1556         .name           = "mcspi3",
1557         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
1558         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
1559         .main_clk       = "mcspi3_fck",
1560         .prcm           = {
1561                 .omap2 = {
1562                         .module_offs = CORE_MOD,
1563                         .prcm_reg_id = 1,
1564                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1565                         .idlest_reg_id = 1,
1566                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1567                 },
1568         },
1569         .class          = &omap34xx_mcspi_class,
1570         .dev_attr       = &omap_mcspi3_dev_attr,
1571 };
1572
1573 /* mcspi4 */
1574 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1575         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
1576         { .irq = -1 }
1577 };
1578
1579 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1580         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1581         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1582         { .dma_req = -1 }
1583 };
1584
1585 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1586         .num_chipselect = 1,
1587 };
1588
1589 static struct omap_hwmod omap34xx_mcspi4 = {
1590         .name           = "mcspi4",
1591         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
1592         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
1593         .main_clk       = "mcspi4_fck",
1594         .prcm           = {
1595                 .omap2 = {
1596                         .module_offs = CORE_MOD,
1597                         .prcm_reg_id = 1,
1598                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1599                         .idlest_reg_id = 1,
1600                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1601                 },
1602         },
1603         .class          = &omap34xx_mcspi_class,
1604         .dev_attr       = &omap_mcspi4_dev_attr,
1605 };
1606
1607 /* usbhsotg */
1608 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1609         .rev_offs       = 0x0400,
1610         .sysc_offs      = 0x0404,
1611         .syss_offs      = 0x0408,
1612         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1613                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1614                           SYSC_HAS_AUTOIDLE),
1615         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1616                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1617         .sysc_fields    = &omap_hwmod_sysc_type1,
1618 };
1619
1620 static struct omap_hwmod_class usbotg_class = {
1621         .name = "usbotg",
1622         .sysc = &omap3xxx_usbhsotg_sysc,
1623 };
1624
1625 /* usb_otg_hs */
1626 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1627
1628         { .name = "mc", .irq = 92 },
1629         { .name = "dma", .irq = 93 },
1630         { .irq = -1 }
1631 };
1632
1633 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1634         .name           = "usb_otg_hs",
1635         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
1636         .main_clk       = "hsotgusb_ick",
1637         .prcm           = {
1638                 .omap2 = {
1639                         .prcm_reg_id = 1,
1640                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1641                         .module_offs = CORE_MOD,
1642                         .idlest_reg_id = 1,
1643                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1644                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1645                 },
1646         },
1647         .class          = &usbotg_class,
1648
1649         /*
1650          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1651          * broken when autoidle is enabled
1652          * workaround is to disable the autoidle bit at module level.
1653          */
1654         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1655                                 | HWMOD_SWSUP_MSTANDBY,
1656 };
1657
1658 /* usb_otg_hs */
1659 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1660         { .name = "mc", .irq = 71 },
1661         { .irq = -1 }
1662 };
1663
1664 static struct omap_hwmod_class am35xx_usbotg_class = {
1665         .name = "am35xx_usbotg",
1666 };
1667
1668 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1669         .name           = "am35x_otg_hs",
1670         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
1671         .main_clk       = "hsotgusb_fck",
1672         .class          = &am35xx_usbotg_class,
1673         .flags          = HWMOD_NO_IDLEST,
1674 };
1675
1676 /* MMC/SD/SDIO common */
1677 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1678         .rev_offs       = 0x1fc,
1679         .sysc_offs      = 0x10,
1680         .syss_offs      = 0x14,
1681         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1682                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1683                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1684         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1685         .sysc_fields    = &omap_hwmod_sysc_type1,
1686 };
1687
1688 static struct omap_hwmod_class omap34xx_mmc_class = {
1689         .name = "mmc",
1690         .sysc = &omap34xx_mmc_sysc,
1691 };
1692
1693 /* MMC/SD/SDIO1 */
1694
1695 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1696         { .irq = 83, },
1697         { .irq = -1 }
1698 };
1699
1700 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1701         { .name = "tx", .dma_req = 61, },
1702         { .name = "rx", .dma_req = 62, },
1703         { .dma_req = -1 }
1704 };
1705
1706 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1707         { .role = "dbck", .clk = "omap_32k_fck", },
1708 };
1709
1710 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1711         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1712 };
1713
1714 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1715 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1716         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1717                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1718 };
1719
1720 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1721         .name           = "mmc1",
1722         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1723         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1724         .opt_clks       = omap34xx_mmc1_opt_clks,
1725         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1726         .main_clk       = "mmchs1_fck",
1727         .prcm           = {
1728                 .omap2 = {
1729                         .module_offs = CORE_MOD,
1730                         .prcm_reg_id = 1,
1731                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1732                         .idlest_reg_id = 1,
1733                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1734                 },
1735         },
1736         .dev_attr       = &mmc1_pre_es3_dev_attr,
1737         .class          = &omap34xx_mmc_class,
1738 };
1739
1740 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1741         .name           = "mmc1",
1742         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1743         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1744         .opt_clks       = omap34xx_mmc1_opt_clks,
1745         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1746         .main_clk       = "mmchs1_fck",
1747         .prcm           = {
1748                 .omap2 = {
1749                         .module_offs = CORE_MOD,
1750                         .prcm_reg_id = 1,
1751                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1752                         .idlest_reg_id = 1,
1753                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1754                 },
1755         },
1756         .dev_attr       = &mmc1_dev_attr,
1757         .class          = &omap34xx_mmc_class,
1758 };
1759
1760 /* MMC/SD/SDIO2 */
1761
1762 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1763         { .irq = INT_24XX_MMC2_IRQ, },
1764         { .irq = -1 }
1765 };
1766
1767 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1768         { .name = "tx", .dma_req = 47, },
1769         { .name = "rx", .dma_req = 48, },
1770         { .dma_req = -1 }
1771 };
1772
1773 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1774         { .role = "dbck", .clk = "omap_32k_fck", },
1775 };
1776
1777 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1778 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1779         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1780 };
1781
1782 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1783         .name           = "mmc2",
1784         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1785         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1786         .opt_clks       = omap34xx_mmc2_opt_clks,
1787         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1788         .main_clk       = "mmchs2_fck",
1789         .prcm           = {
1790                 .omap2 = {
1791                         .module_offs = CORE_MOD,
1792                         .prcm_reg_id = 1,
1793                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1794                         .idlest_reg_id = 1,
1795                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1796                 },
1797         },
1798         .dev_attr       = &mmc2_pre_es3_dev_attr,
1799         .class          = &omap34xx_mmc_class,
1800 };
1801
1802 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1803         .name           = "mmc2",
1804         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1805         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1806         .opt_clks       = omap34xx_mmc2_opt_clks,
1807         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1808         .main_clk       = "mmchs2_fck",
1809         .prcm           = {
1810                 .omap2 = {
1811                         .module_offs = CORE_MOD,
1812                         .prcm_reg_id = 1,
1813                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1814                         .idlest_reg_id = 1,
1815                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1816                 },
1817         },
1818         .class          = &omap34xx_mmc_class,
1819 };
1820
1821 /* MMC/SD/SDIO3 */
1822
1823 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1824         { .irq = 94, },
1825         { .irq = -1 }
1826 };
1827
1828 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1829         { .name = "tx", .dma_req = 77, },
1830         { .name = "rx", .dma_req = 78, },
1831         { .dma_req = -1 }
1832 };
1833
1834 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1835         { .role = "dbck", .clk = "omap_32k_fck", },
1836 };
1837
1838 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1839         .name           = "mmc3",
1840         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
1841         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
1842         .opt_clks       = omap34xx_mmc3_opt_clks,
1843         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1844         .main_clk       = "mmchs3_fck",
1845         .prcm           = {
1846                 .omap2 = {
1847                         .prcm_reg_id = 1,
1848                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1849                         .idlest_reg_id = 1,
1850                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1851                 },
1852         },
1853         .class          = &omap34xx_mmc_class,
1854 };
1855
1856 /*
1857  * 'usb_host_hs' class
1858  * high-speed multi-port usb host controller
1859  */
1860
1861 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1862         .rev_offs       = 0x0000,
1863         .sysc_offs      = 0x0010,
1864         .syss_offs      = 0x0014,
1865         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1866                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1867                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1868         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1869                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1870         .sysc_fields    = &omap_hwmod_sysc_type1,
1871 };
1872
1873 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1874         .name = "usb_host_hs",
1875         .sysc = &omap3xxx_usb_host_hs_sysc,
1876 };
1877
1878 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1879           { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1880 };
1881
1882 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1883         { .name = "ohci-irq", .irq = 76 },
1884         { .name = "ehci-irq", .irq = 77 },
1885         { .irq = -1 }
1886 };
1887
1888 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1889         .name           = "usb_host_hs",
1890         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1891         .clkdm_name     = "l3_init_clkdm",
1892         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
1893         .main_clk       = "usbhost_48m_fck",
1894         .prcm = {
1895                 .omap2 = {
1896                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1897                         .prcm_reg_id = 1,
1898                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1899                         .idlest_reg_id = 1,
1900                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1901                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1902                 },
1903         },
1904         .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
1905         .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1906
1907         /*
1908          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1909          * id: i660
1910          *
1911          * Description:
1912          * In the following configuration :
1913          * - USBHOST module is set to smart-idle mode
1914          * - PRCM asserts idle_req to the USBHOST module ( This typically
1915          *   happens when the system is going to a low power mode : all ports
1916          *   have been suspended, the master part of the USBHOST module has
1917          *   entered the standby state, and SW has cut the functional clocks)
1918          * - an USBHOST interrupt occurs before the module is able to answer
1919          *   idle_ack, typically a remote wakeup IRQ.
1920          * Then the USB HOST module will enter a deadlock situation where it
1921          * is no more accessible nor functional.
1922          *
1923          * Workaround:
1924          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1925          */
1926
1927         /*
1928          * Errata: USB host EHCI may stall when entering smart-standby mode
1929          * Id: i571
1930          *
1931          * Description:
1932          * When the USBHOST module is set to smart-standby mode, and when it is
1933          * ready to enter the standby state (i.e. all ports are suspended and
1934          * all attached devices are in suspend mode), then it can wrongly assert
1935          * the Mstandby signal too early while there are still some residual OCP
1936          * transactions ongoing. If this condition occurs, the internal state
1937          * machine may go to an undefined state and the USB link may be stuck
1938          * upon the next resume.
1939          *
1940          * Workaround:
1941          * Don't use smart standby; use only force standby,
1942          * hence HWMOD_SWSUP_MSTANDBY
1943          */
1944
1945         /*
1946          * During system boot; If the hwmod framework resets the module
1947          * the module will have smart idle settings; which can lead to deadlock
1948          * (above Errata Id:i660); so, dont reset the module during boot;
1949          * Use HWMOD_INIT_NO_RESET.
1950          */
1951
1952         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1953                           HWMOD_INIT_NO_RESET,
1954 };
1955
1956 /*
1957  * 'usb_tll_hs' class
1958  * usb_tll_hs module is the adapter on the usb_host_hs ports
1959  */
1960 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1961         .rev_offs       = 0x0000,
1962         .sysc_offs      = 0x0010,
1963         .syss_offs      = 0x0014,
1964         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1965                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1966                            SYSC_HAS_AUTOIDLE),
1967         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1968         .sysc_fields    = &omap_hwmod_sysc_type1,
1969 };
1970
1971 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1972         .name = "usb_tll_hs",
1973         .sysc = &omap3xxx_usb_tll_hs_sysc,
1974 };
1975
1976 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
1977         { .name = "tll-irq", .irq = 78 },
1978         { .irq = -1 }
1979 };
1980
1981 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1982         .name           = "usb_tll_hs",
1983         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
1984         .clkdm_name     = "l3_init_clkdm",
1985         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
1986         .main_clk       = "usbtll_fck",
1987         .prcm = {
1988                 .omap2 = {
1989                         .module_offs = CORE_MOD,
1990                         .prcm_reg_id = 3,
1991                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1992                         .idlest_reg_id = 3,
1993                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1994                 },
1995         },
1996 };
1997
1998 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1999         .name           = "hdq1w",
2000         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
2001         .main_clk       = "hdq_fck",
2002         .prcm           = {
2003                 .omap2 = {
2004                         .module_offs = CORE_MOD,
2005                         .prcm_reg_id = 1,
2006                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
2007                         .idlest_reg_id = 1,
2008                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
2009                 },
2010         },
2011         .class          = &omap2_hdq1w_class,
2012 };
2013
2014 /*
2015  * '32K sync counter' class
2016  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
2017  */
2018 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
2019         .rev_offs       = 0x0000,
2020         .sysc_offs      = 0x0004,
2021         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2022         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
2023         .sysc_fields    = &omap_hwmod_sysc_type1,
2024 };
2025
2026 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2027         .name   = "counter",
2028         .sysc   = &omap3xxx_counter_sysc,
2029 };
2030
2031 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2032         .name           = "counter_32k",
2033         .class          = &omap3xxx_counter_hwmod_class,
2034         .clkdm_name     = "wkup_clkdm",
2035         .flags          = HWMOD_SWSUP_SIDLE,
2036         .main_clk       = "wkup_32k_fck",
2037         .prcm           = {
2038                 .omap2  = {
2039                         .module_offs = WKUP_MOD,
2040                         .prcm_reg_id = 1,
2041                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2042                         .idlest_reg_id = 1,
2043                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2044                 },
2045         },
2046 };
2047
2048 /*
2049  * interfaces
2050  */
2051
2052 /* L3 -> L4_CORE interface */
2053 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2054         .master = &omap3xxx_l3_main_hwmod,
2055         .slave  = &omap3xxx_l4_core_hwmod,
2056         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2057 };
2058
2059 /* L3 -> L4_PER interface */
2060 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2061         .master = &omap3xxx_l3_main_hwmod,
2062         .slave  = &omap3xxx_l4_per_hwmod,
2063         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2064 };
2065
2066 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2067         {
2068                 .pa_start       = 0x68000000,
2069                 .pa_end         = 0x6800ffff,
2070                 .flags          = ADDR_TYPE_RT,
2071         },
2072         { }
2073 };
2074
2075 /* MPU -> L3 interface */
2076 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2077         .master   = &omap3xxx_mpu_hwmod,
2078         .slave    = &omap3xxx_l3_main_hwmod,
2079         .addr     = omap3xxx_l3_main_addrs,
2080         .user   = OCP_USER_MPU,
2081 };
2082
2083 /* DSS -> l3 */
2084 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2085         .master         = &omap3430es1_dss_core_hwmod,
2086         .slave          = &omap3xxx_l3_main_hwmod,
2087         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2088 };
2089
2090 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2091         .master         = &omap3xxx_dss_core_hwmod,
2092         .slave          = &omap3xxx_l3_main_hwmod,
2093         .fw = {
2094                 .omap2 = {
2095                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2096                         .flags  = OMAP_FIREWALL_L3,
2097                 }
2098         },
2099         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2100 };
2101
2102 /* l3_core -> usbhsotg interface */
2103 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2104         .master         = &omap3xxx_usbhsotg_hwmod,
2105         .slave          = &omap3xxx_l3_main_hwmod,
2106         .clk            = "core_l3_ick",
2107         .user           = OCP_USER_MPU,
2108 };
2109
2110 /* l3_core -> am35xx_usbhsotg interface */
2111 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2112         .master         = &am35xx_usbhsotg_hwmod,
2113         .slave          = &omap3xxx_l3_main_hwmod,
2114         .clk            = "hsotgusb_ick",
2115         .user           = OCP_USER_MPU,
2116 };
2117
2118 /* L4_CORE -> L4_WKUP interface */
2119 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2120         .master = &omap3xxx_l4_core_hwmod,
2121         .slave  = &omap3xxx_l4_wkup_hwmod,
2122         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2123 };
2124
2125 /* L4 CORE -> MMC1 interface */
2126 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2127         .master         = &omap3xxx_l4_core_hwmod,
2128         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
2129         .clk            = "mmchs1_ick",
2130         .addr           = omap2430_mmc1_addr_space,
2131         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2132         .flags          = OMAP_FIREWALL_L4
2133 };
2134
2135 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2136         .master         = &omap3xxx_l4_core_hwmod,
2137         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
2138         .clk            = "mmchs1_ick",
2139         .addr           = omap2430_mmc1_addr_space,
2140         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2141         .flags          = OMAP_FIREWALL_L4
2142 };
2143
2144 /* L4 CORE -> MMC2 interface */
2145 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2146         .master         = &omap3xxx_l4_core_hwmod,
2147         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
2148         .clk            = "mmchs2_ick",
2149         .addr           = omap2430_mmc2_addr_space,
2150         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2151         .flags          = OMAP_FIREWALL_L4
2152 };
2153
2154 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2155         .master         = &omap3xxx_l4_core_hwmod,
2156         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2157         .clk            = "mmchs2_ick",
2158         .addr           = omap2430_mmc2_addr_space,
2159         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2160         .flags          = OMAP_FIREWALL_L4
2161 };
2162
2163 /* L4 CORE -> MMC3 interface */
2164 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2165         {
2166                 .pa_start       = 0x480ad000,
2167                 .pa_end         = 0x480ad1ff,
2168                 .flags          = ADDR_TYPE_RT,
2169         },
2170         { }
2171 };
2172
2173 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2174         .master         = &omap3xxx_l4_core_hwmod,
2175         .slave          = &omap3xxx_mmc3_hwmod,
2176         .clk            = "mmchs3_ick",
2177         .addr           = omap3xxx_mmc3_addr_space,
2178         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2179         .flags          = OMAP_FIREWALL_L4
2180 };
2181
2182 /* L4 CORE -> UART1 interface */
2183 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2184         {
2185                 .pa_start       = OMAP3_UART1_BASE,
2186                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
2187                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2188         },
2189         { }
2190 };
2191
2192 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2193         .master         = &omap3xxx_l4_core_hwmod,
2194         .slave          = &omap3xxx_uart1_hwmod,
2195         .clk            = "uart1_ick",
2196         .addr           = omap3xxx_uart1_addr_space,
2197         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2198 };
2199
2200 /* L4 CORE -> UART2 interface */
2201 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2202         {
2203                 .pa_start       = OMAP3_UART2_BASE,
2204                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
2205                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2206         },
2207         { }
2208 };
2209
2210 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2211         .master         = &omap3xxx_l4_core_hwmod,
2212         .slave          = &omap3xxx_uart2_hwmod,
2213         .clk            = "uart2_ick",
2214         .addr           = omap3xxx_uart2_addr_space,
2215         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2216 };
2217
2218 /* L4 PER -> UART3 interface */
2219 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2220         {
2221                 .pa_start       = OMAP3_UART3_BASE,
2222                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
2223                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2224         },
2225         { }
2226 };
2227
2228 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2229         .master         = &omap3xxx_l4_per_hwmod,
2230         .slave          = &omap3xxx_uart3_hwmod,
2231         .clk            = "uart3_ick",
2232         .addr           = omap3xxx_uart3_addr_space,
2233         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2234 };
2235
2236 /* L4 PER -> UART4 interface */
2237 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2238         {
2239                 .pa_start       = OMAP3_UART4_BASE,
2240                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
2241                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2242         },
2243         { }
2244 };
2245
2246 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2247         .master         = &omap3xxx_l4_per_hwmod,
2248         .slave          = &omap36xx_uart4_hwmod,
2249         .clk            = "uart4_ick",
2250         .addr           = omap36xx_uart4_addr_space,
2251         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2252 };
2253
2254 /* AM35xx: L4 CORE -> UART4 interface */
2255 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2256         {
2257                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
2258                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2259                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2260         },
2261         { }
2262 };
2263
2264 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2265         .master         = &omap3xxx_l4_core_hwmod,
2266         .slave          = &am35xx_uart4_hwmod,
2267         .clk            = "uart4_ick",
2268         .addr           = am35xx_uart4_addr_space,
2269         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2270 };
2271
2272 /* L4 CORE -> I2C1 interface */
2273 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2274         .master         = &omap3xxx_l4_core_hwmod,
2275         .slave          = &omap3xxx_i2c1_hwmod,
2276         .clk            = "i2c1_ick",
2277         .addr           = omap2_i2c1_addr_space,
2278         .fw = {
2279                 .omap2 = {
2280                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2281                         .l4_prot_group = 7,
2282                         .flags  = OMAP_FIREWALL_L4,
2283                 }
2284         },
2285         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2286 };
2287
2288 /* L4 CORE -> I2C2 interface */
2289 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2290         .master         = &omap3xxx_l4_core_hwmod,
2291         .slave          = &omap3xxx_i2c2_hwmod,
2292         .clk            = "i2c2_ick",
2293         .addr           = omap2_i2c2_addr_space,
2294         .fw = {
2295                 .omap2 = {
2296                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2297                         .l4_prot_group = 7,
2298                         .flags = OMAP_FIREWALL_L4,
2299                 }
2300         },
2301         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2302 };
2303
2304 /* L4 CORE -> I2C3 interface */
2305 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2306         {
2307                 .pa_start       = 0x48060000,
2308                 .pa_end         = 0x48060000 + SZ_128 - 1,
2309                 .flags          = ADDR_TYPE_RT,
2310         },
2311         { }
2312 };
2313
2314 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2315         .master         = &omap3xxx_l4_core_hwmod,
2316         .slave          = &omap3xxx_i2c3_hwmod,
2317         .clk            = "i2c3_ick",
2318         .addr           = omap3xxx_i2c3_addr_space,
2319         .fw = {
2320                 .omap2 = {
2321                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2322                         .l4_prot_group = 7,
2323                         .flags = OMAP_FIREWALL_L4,
2324                 }
2325         },
2326         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2327 };
2328
2329 /* L4 CORE -> SR1 interface */
2330 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2331         {
2332                 .pa_start       = OMAP34XX_SR1_BASE,
2333                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2334                 .flags          = ADDR_TYPE_RT,
2335         },
2336         { }
2337 };
2338
2339 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2340         .master         = &omap3xxx_l4_core_hwmod,
2341         .slave          = &omap34xx_sr1_hwmod,
2342         .clk            = "sr_l4_ick",
2343         .addr           = omap3_sr1_addr_space,
2344         .user           = OCP_USER_MPU,
2345 };
2346
2347 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2348         .master         = &omap3xxx_l4_core_hwmod,
2349         .slave          = &omap36xx_sr1_hwmod,
2350         .clk            = "sr_l4_ick",
2351         .addr           = omap3_sr1_addr_space,
2352         .user           = OCP_USER_MPU,
2353 };
2354
2355 /* L4 CORE -> SR1 interface */
2356 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2357         {
2358                 .pa_start       = OMAP34XX_SR2_BASE,
2359                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2360                 .flags          = ADDR_TYPE_RT,
2361         },
2362         { }
2363 };
2364
2365 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2366         .master         = &omap3xxx_l4_core_hwmod,
2367         .slave          = &omap34xx_sr2_hwmod,
2368         .clk            = "sr_l4_ick",
2369         .addr           = omap3_sr2_addr_space,
2370         .user           = OCP_USER_MPU,
2371 };
2372
2373 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2374         .master         = &omap3xxx_l4_core_hwmod,
2375         .slave          = &omap36xx_sr2_hwmod,
2376         .clk            = "sr_l4_ick",
2377         .addr           = omap3_sr2_addr_space,
2378         .user           = OCP_USER_MPU,
2379 };
2380
2381 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2382         {
2383                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
2384                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2385                 .flags          = ADDR_TYPE_RT
2386         },
2387         { }
2388 };
2389
2390 /* l4_core -> usbhsotg  */
2391 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2392         .master         = &omap3xxx_l4_core_hwmod,
2393         .slave          = &omap3xxx_usbhsotg_hwmod,
2394         .clk            = "l4_ick",
2395         .addr           = omap3xxx_usbhsotg_addrs,
2396         .user           = OCP_USER_MPU,
2397 };
2398
2399 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2400         {
2401                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
2402                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2403                 .flags          = ADDR_TYPE_RT
2404         },
2405         { }
2406 };
2407
2408 /* l4_core -> usbhsotg  */
2409 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2410         .master         = &omap3xxx_l4_core_hwmod,
2411         .slave          = &am35xx_usbhsotg_hwmod,
2412         .clk            = "hsotgusb_ick",
2413         .addr           = am35xx_usbhsotg_addrs,
2414         .user           = OCP_USER_MPU,
2415 };
2416
2417 /* L4_WKUP -> L4_SEC interface */
2418 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2419         .master = &omap3xxx_l4_wkup_hwmod,
2420         .slave  = &omap3xxx_l4_sec_hwmod,
2421         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2422 };
2423
2424 /* IVA2 <- L3 interface */
2425 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2426         .master         = &omap3xxx_l3_main_hwmod,
2427         .slave          = &omap3xxx_iva_hwmod,
2428         .clk            = "core_l3_ick",
2429         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2430 };
2431
2432 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2433         {
2434                 .pa_start       = 0x48318000,
2435                 .pa_end         = 0x48318000 + SZ_1K - 1,
2436                 .flags          = ADDR_TYPE_RT
2437         },
2438         { }
2439 };
2440
2441 /* l4_wkup -> timer1 */
2442 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2443         .master         = &omap3xxx_l4_wkup_hwmod,
2444         .slave          = &omap3xxx_timer1_hwmod,
2445         .clk            = "gpt1_ick",
2446         .addr           = omap3xxx_timer1_addrs,
2447         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2448 };
2449
2450 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2451         {
2452                 .pa_start       = 0x49032000,
2453                 .pa_end         = 0x49032000 + SZ_1K - 1,
2454                 .flags          = ADDR_TYPE_RT
2455         },
2456         { }
2457 };
2458
2459 /* l4_per -> timer2 */
2460 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2461         .master         = &omap3xxx_l4_per_hwmod,
2462         .slave          = &omap3xxx_timer2_hwmod,
2463         .clk            = "gpt2_ick",
2464         .addr           = omap3xxx_timer2_addrs,
2465         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2466 };
2467
2468 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2469         {
2470                 .pa_start       = 0x49034000,
2471                 .pa_end         = 0x49034000 + SZ_1K - 1,
2472                 .flags          = ADDR_TYPE_RT
2473         },
2474         { }
2475 };
2476
2477 /* l4_per -> timer3 */
2478 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2479         .master         = &omap3xxx_l4_per_hwmod,
2480         .slave          = &omap3xxx_timer3_hwmod,
2481         .clk            = "gpt3_ick",
2482         .addr           = omap3xxx_timer3_addrs,
2483         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2484 };
2485
2486 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2487         {
2488                 .pa_start       = 0x49036000,
2489                 .pa_end         = 0x49036000 + SZ_1K - 1,
2490                 .flags          = ADDR_TYPE_RT
2491         },
2492         { }
2493 };
2494
2495 /* l4_per -> timer4 */
2496 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2497         .master         = &omap3xxx_l4_per_hwmod,
2498         .slave          = &omap3xxx_timer4_hwmod,
2499         .clk            = "gpt4_ick",
2500         .addr           = omap3xxx_timer4_addrs,
2501         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2502 };
2503
2504 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2505         {
2506                 .pa_start       = 0x49038000,
2507                 .pa_end         = 0x49038000 + SZ_1K - 1,
2508                 .flags          = ADDR_TYPE_RT
2509         },
2510         { }
2511 };
2512
2513 /* l4_per -> timer5 */
2514 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2515         .master         = &omap3xxx_l4_per_hwmod,
2516         .slave          = &omap3xxx_timer5_hwmod,
2517         .clk            = "gpt5_ick",
2518         .addr           = omap3xxx_timer5_addrs,
2519         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2520 };
2521
2522 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2523         {
2524                 .pa_start       = 0x4903A000,
2525                 .pa_end         = 0x4903A000 + SZ_1K - 1,
2526                 .flags          = ADDR_TYPE_RT
2527         },
2528         { }
2529 };
2530
2531 /* l4_per -> timer6 */
2532 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2533         .master         = &omap3xxx_l4_per_hwmod,
2534         .slave          = &omap3xxx_timer6_hwmod,
2535         .clk            = "gpt6_ick",
2536         .addr           = omap3xxx_timer6_addrs,
2537         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2538 };
2539
2540 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2541         {
2542                 .pa_start       = 0x4903C000,
2543                 .pa_end         = 0x4903C000 + SZ_1K - 1,
2544                 .flags          = ADDR_TYPE_RT
2545         },
2546         { }
2547 };
2548
2549 /* l4_per -> timer7 */
2550 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2551         .master         = &omap3xxx_l4_per_hwmod,
2552         .slave          = &omap3xxx_timer7_hwmod,
2553         .clk            = "gpt7_ick",
2554         .addr           = omap3xxx_timer7_addrs,
2555         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2556 };
2557
2558 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2559         {
2560                 .pa_start       = 0x4903E000,
2561                 .pa_end         = 0x4903E000 + SZ_1K - 1,
2562                 .flags          = ADDR_TYPE_RT
2563         },
2564         { }
2565 };
2566
2567 /* l4_per -> timer8 */
2568 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2569         .master         = &omap3xxx_l4_per_hwmod,
2570         .slave          = &omap3xxx_timer8_hwmod,
2571         .clk            = "gpt8_ick",
2572         .addr           = omap3xxx_timer8_addrs,
2573         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2574 };
2575
2576 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2577         {
2578                 .pa_start       = 0x49040000,
2579                 .pa_end         = 0x49040000 + SZ_1K - 1,
2580                 .flags          = ADDR_TYPE_RT
2581         },
2582         { }
2583 };
2584
2585 /* l4_per -> timer9 */
2586 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2587         .master         = &omap3xxx_l4_per_hwmod,
2588         .slave          = &omap3xxx_timer9_hwmod,
2589         .clk            = "gpt9_ick",
2590         .addr           = omap3xxx_timer9_addrs,
2591         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2592 };
2593
2594 /* l4_core -> timer10 */
2595 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2596         .master         = &omap3xxx_l4_core_hwmod,
2597         .slave          = &omap3xxx_timer10_hwmod,
2598         .clk            = "gpt10_ick",
2599         .addr           = omap2_timer10_addrs,
2600         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2601 };
2602
2603 /* l4_core -> timer11 */
2604 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2605         .master         = &omap3xxx_l4_core_hwmod,
2606         .slave          = &omap3xxx_timer11_hwmod,
2607         .clk            = "gpt11_ick",
2608         .addr           = omap2_timer11_addrs,
2609         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2610 };
2611
2612 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2613         {
2614                 .pa_start       = 0x48304000,
2615                 .pa_end         = 0x48304000 + SZ_1K - 1,
2616                 .flags          = ADDR_TYPE_RT
2617         },
2618         { }
2619 };
2620
2621 /* l4_core -> timer12 */
2622 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2623         .master         = &omap3xxx_l4_sec_hwmod,
2624         .slave          = &omap3xxx_timer12_hwmod,
2625         .clk            = "gpt12_ick",
2626         .addr           = omap3xxx_timer12_addrs,
2627         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2628 };
2629
2630 /* l4_wkup -> wd_timer2 */
2631 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2632         {
2633                 .pa_start       = 0x48314000,
2634                 .pa_end         = 0x4831407f,
2635                 .flags          = ADDR_TYPE_RT
2636         },
2637         { }
2638 };
2639
2640 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2641         .master         = &omap3xxx_l4_wkup_hwmod,
2642         .slave          = &omap3xxx_wd_timer2_hwmod,
2643         .clk            = "wdt2_ick",
2644         .addr           = omap3xxx_wd_timer2_addrs,
2645         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2646 };
2647
2648 /* l4_core -> dss */
2649 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2650         .master         = &omap3xxx_l4_core_hwmod,
2651         .slave          = &omap3430es1_dss_core_hwmod,
2652         .clk            = "dss_ick",
2653         .addr           = omap2_dss_addrs,
2654         .fw = {
2655                 .omap2 = {
2656                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2657                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2658                         .flags  = OMAP_FIREWALL_L4,
2659                 }
2660         },
2661         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2662 };
2663
2664 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2665         .master         = &omap3xxx_l4_core_hwmod,
2666         .slave          = &omap3xxx_dss_core_hwmod,
2667         .clk            = "dss_ick",
2668         .addr           = omap2_dss_addrs,
2669         .fw = {
2670                 .omap2 = {
2671                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2672                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2673                         .flags  = OMAP_FIREWALL_L4,
2674                 }
2675         },
2676         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2677 };
2678
2679 /* l4_core -> dss_dispc */
2680 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2681         .master         = &omap3xxx_l4_core_hwmod,
2682         .slave          = &omap3xxx_dss_dispc_hwmod,
2683         .clk            = "dss_ick",
2684         .addr           = omap2_dss_dispc_addrs,
2685         .fw = {
2686                 .omap2 = {
2687                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2688                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2689                         .flags  = OMAP_FIREWALL_L4,
2690                 }
2691         },
2692         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2693 };
2694
2695 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2696         {
2697                 .pa_start       = 0x4804FC00,
2698                 .pa_end         = 0x4804FFFF,
2699                 .flags          = ADDR_TYPE_RT
2700         },
2701         { }
2702 };
2703
2704 /* l4_core -> dss_dsi1 */
2705 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2706         .master         = &omap3xxx_l4_core_hwmod,
2707         .slave          = &omap3xxx_dss_dsi1_hwmod,
2708         .clk            = "dss_ick",
2709         .addr           = omap3xxx_dss_dsi1_addrs,
2710         .fw = {
2711                 .omap2 = {
2712                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2713                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2714                         .flags  = OMAP_FIREWALL_L4,
2715                 }
2716         },
2717         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2718 };
2719
2720 /* l4_core -> dss_rfbi */
2721 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2722         .master         = &omap3xxx_l4_core_hwmod,
2723         .slave          = &omap3xxx_dss_rfbi_hwmod,
2724         .clk            = "dss_ick",
2725         .addr           = omap2_dss_rfbi_addrs,
2726         .fw = {
2727                 .omap2 = {
2728                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2729                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2730                         .flags  = OMAP_FIREWALL_L4,
2731                 }
2732         },
2733         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2734 };
2735
2736 /* l4_core -> dss_venc */
2737 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2738         .master         = &omap3xxx_l4_core_hwmod,
2739         .slave          = &omap3xxx_dss_venc_hwmod,
2740         .clk            = "dss_ick",
2741         .addr           = omap2_dss_venc_addrs,
2742         .fw = {
2743                 .omap2 = {
2744                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2745                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2746                         .flags  = OMAP_FIREWALL_L4,
2747                 }
2748         },
2749         .flags          = OCPIF_SWSUP_IDLE,
2750         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2751 };
2752
2753 /* l4_wkup -> gpio1 */
2754 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2755         {
2756                 .pa_start       = 0x48310000,
2757                 .pa_end         = 0x483101ff,
2758                 .flags          = ADDR_TYPE_RT
2759         },
2760         { }
2761 };
2762
2763 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2764         .master         = &omap3xxx_l4_wkup_hwmod,
2765         .slave          = &omap3xxx_gpio1_hwmod,
2766         .addr           = omap3xxx_gpio1_addrs,
2767         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2768 };
2769
2770 /* l4_per -> gpio2 */
2771 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2772         {
2773                 .pa_start       = 0x49050000,
2774                 .pa_end         = 0x490501ff,
2775                 .flags          = ADDR_TYPE_RT
2776         },
2777         { }
2778 };
2779
2780 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2781         .master         = &omap3xxx_l4_per_hwmod,
2782         .slave          = &omap3xxx_gpio2_hwmod,
2783         .addr           = omap3xxx_gpio2_addrs,
2784         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2785 };
2786
2787 /* l4_per -> gpio3 */
2788 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2789         {
2790                 .pa_start       = 0x49052000,
2791                 .pa_end         = 0x490521ff,
2792                 .flags          = ADDR_TYPE_RT
2793         },
2794         { }
2795 };
2796
2797 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2798         .master         = &omap3xxx_l4_per_hwmod,
2799         .slave          = &omap3xxx_gpio3_hwmod,
2800         .addr           = omap3xxx_gpio3_addrs,
2801         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2802 };
2803
2804 /* l4_per -> gpio4 */
2805 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2806         {
2807                 .pa_start       = 0x49054000,
2808                 .pa_end         = 0x490541ff,
2809                 .flags          = ADDR_TYPE_RT
2810         },
2811         { }
2812 };
2813
2814 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2815         .master         = &omap3xxx_l4_per_hwmod,
2816         .slave          = &omap3xxx_gpio4_hwmod,
2817         .addr           = omap3xxx_gpio4_addrs,
2818         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2819 };
2820
2821 /* l4_per -> gpio5 */
2822 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2823         {
2824                 .pa_start       = 0x49056000,
2825                 .pa_end         = 0x490561ff,
2826                 .flags          = ADDR_TYPE_RT
2827         },
2828         { }
2829 };
2830
2831 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2832         .master         = &omap3xxx_l4_per_hwmod,
2833         .slave          = &omap3xxx_gpio5_hwmod,
2834         .addr           = omap3xxx_gpio5_addrs,
2835         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2836 };
2837
2838 /* l4_per -> gpio6 */
2839 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2840         {
2841                 .pa_start       = 0x49058000,
2842                 .pa_end         = 0x490581ff,
2843                 .flags          = ADDR_TYPE_RT
2844         },
2845         { }
2846 };
2847
2848 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2849         .master         = &omap3xxx_l4_per_hwmod,
2850         .slave          = &omap3xxx_gpio6_hwmod,
2851         .addr           = omap3xxx_gpio6_addrs,
2852         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2853 };
2854
2855 /* dma_system -> L3 */
2856 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2857         .master         = &omap3xxx_dma_system_hwmod,
2858         .slave          = &omap3xxx_l3_main_hwmod,
2859         .clk            = "core_l3_ick",
2860         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2861 };
2862
2863 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2864         {
2865                 .pa_start       = 0x48056000,
2866                 .pa_end         = 0x48056fff,
2867                 .flags          = ADDR_TYPE_RT
2868         },
2869         { }
2870 };
2871
2872 /* l4_cfg -> dma_system */
2873 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2874         .master         = &omap3xxx_l4_core_hwmod,
2875         .slave          = &omap3xxx_dma_system_hwmod,
2876         .clk            = "core_l4_ick",
2877         .addr           = omap3xxx_dma_system_addrs,
2878         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2879 };
2880
2881 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2882         {
2883                 .name           = "mpu",
2884                 .pa_start       = 0x48074000,
2885                 .pa_end         = 0x480740ff,
2886                 .flags          = ADDR_TYPE_RT
2887         },
2888         { }
2889 };
2890
2891 /* l4_core -> mcbsp1 */
2892 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2893         .master         = &omap3xxx_l4_core_hwmod,
2894         .slave          = &omap3xxx_mcbsp1_hwmod,
2895         .clk            = "mcbsp1_ick",
2896         .addr           = omap3xxx_mcbsp1_addrs,
2897         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2898 };
2899
2900 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2901         {
2902                 .name           = "mpu",
2903                 .pa_start       = 0x49022000,
2904                 .pa_end         = 0x490220ff,
2905                 .flags          = ADDR_TYPE_RT
2906         },
2907         { }
2908 };
2909
2910 /* l4_per -> mcbsp2 */
2911 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2912         .master         = &omap3xxx_l4_per_hwmod,
2913         .slave          = &omap3xxx_mcbsp2_hwmod,
2914         .clk            = "mcbsp2_ick",
2915         .addr           = omap3xxx_mcbsp2_addrs,
2916         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2917 };
2918
2919 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2920         {
2921                 .name           = "mpu",
2922                 .pa_start       = 0x49024000,
2923                 .pa_end         = 0x490240ff,
2924                 .flags          = ADDR_TYPE_RT
2925         },
2926         { }
2927 };
2928
2929 /* l4_per -> mcbsp3 */
2930 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2931         .master         = &omap3xxx_l4_per_hwmod,
2932         .slave          = &omap3xxx_mcbsp3_hwmod,
2933         .clk            = "mcbsp3_ick",
2934         .addr           = omap3xxx_mcbsp3_addrs,
2935         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2936 };
2937
2938 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2939         {
2940                 .name           = "mpu",
2941                 .pa_start       = 0x49026000,
2942                 .pa_end         = 0x490260ff,
2943                 .flags          = ADDR_TYPE_RT
2944         },
2945         { }
2946 };
2947
2948 /* l4_per -> mcbsp4 */
2949 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2950         .master         = &omap3xxx_l4_per_hwmod,
2951         .slave          = &omap3xxx_mcbsp4_hwmod,
2952         .clk            = "mcbsp4_ick",
2953         .addr           = omap3xxx_mcbsp4_addrs,
2954         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2955 };
2956
2957 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2958         {
2959                 .name           = "mpu",
2960                 .pa_start       = 0x48096000,
2961                 .pa_end         = 0x480960ff,
2962                 .flags          = ADDR_TYPE_RT
2963         },
2964         { }
2965 };
2966
2967 /* l4_core -> mcbsp5 */
2968 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2969         .master         = &omap3xxx_l4_core_hwmod,
2970         .slave          = &omap3xxx_mcbsp5_hwmod,
2971         .clk            = "mcbsp5_ick",
2972         .addr           = omap3xxx_mcbsp5_addrs,
2973         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2974 };
2975
2976 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2977         {
2978                 .name           = "sidetone",
2979                 .pa_start       = 0x49028000,
2980                 .pa_end         = 0x490280ff,
2981                 .flags          = ADDR_TYPE_RT
2982         },
2983         { }
2984 };
2985
2986 /* l4_per -> mcbsp2_sidetone */
2987 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2988         .master         = &omap3xxx_l4_per_hwmod,
2989         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2990         .clk            = "mcbsp2_ick",
2991         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2992         .user           = OCP_USER_MPU,
2993 };
2994
2995 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2996         {
2997                 .name           = "sidetone",
2998                 .pa_start       = 0x4902A000,
2999                 .pa_end         = 0x4902A0ff,
3000                 .flags          = ADDR_TYPE_RT
3001         },
3002         { }
3003 };
3004
3005 /* l4_per -> mcbsp3_sidetone */
3006 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
3007         .master         = &omap3xxx_l4_per_hwmod,
3008         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
3009         .clk            = "mcbsp3_ick",
3010         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
3011         .user           = OCP_USER_MPU,
3012 };
3013
3014 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
3015         {
3016                 .pa_start       = 0x48094000,
3017                 .pa_end         = 0x480941ff,
3018                 .flags          = ADDR_TYPE_RT,
3019         },
3020         { }
3021 };
3022
3023 /* l4_core -> mailbox */
3024 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3025         .master         = &omap3xxx_l4_core_hwmod,
3026         .slave          = &omap3xxx_mailbox_hwmod,
3027         .addr           = omap3xxx_mailbox_addrs,
3028         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3029 };
3030
3031 /* l4 core -> mcspi1 interface */
3032 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3033         .master         = &omap3xxx_l4_core_hwmod,
3034         .slave          = &omap34xx_mcspi1,
3035         .clk            = "mcspi1_ick",
3036         .addr           = omap2_mcspi1_addr_space,
3037         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3038 };
3039
3040 /* l4 core -> mcspi2 interface */
3041 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3042         .master         = &omap3xxx_l4_core_hwmod,
3043         .slave          = &omap34xx_mcspi2,
3044         .clk            = "mcspi2_ick",
3045         .addr           = omap2_mcspi2_addr_space,
3046         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3047 };
3048
3049 /* l4 core -> mcspi3 interface */
3050 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3051         .master         = &omap3xxx_l4_core_hwmod,
3052         .slave          = &omap34xx_mcspi3,
3053         .clk            = "mcspi3_ick",
3054         .addr           = omap2430_mcspi3_addr_space,
3055         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3056 };
3057
3058 /* l4 core -> mcspi4 interface */
3059 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3060         {
3061                 .pa_start       = 0x480ba000,
3062                 .pa_end         = 0x480ba0ff,
3063                 .flags          = ADDR_TYPE_RT,
3064         },
3065         { }
3066 };
3067
3068 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3069         .master         = &omap3xxx_l4_core_hwmod,
3070         .slave          = &omap34xx_mcspi4,
3071         .clk            = "mcspi4_ick",
3072         .addr           = omap34xx_mcspi4_addr_space,
3073         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3074 };
3075
3076 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3077         .master         = &omap3xxx_usb_host_hs_hwmod,
3078         .slave          = &omap3xxx_l3_main_hwmod,
3079         .clk            = "core_l3_ick",
3080         .user           = OCP_USER_MPU,
3081 };
3082
3083 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3084         {
3085                 .name           = "uhh",
3086                 .pa_start       = 0x48064000,
3087                 .pa_end         = 0x480643ff,
3088                 .flags          = ADDR_TYPE_RT
3089         },
3090         {
3091                 .name           = "ohci",
3092                 .pa_start       = 0x48064400,
3093                 .pa_end         = 0x480647ff,
3094         },
3095         {
3096                 .name           = "ehci",
3097                 .pa_start       = 0x48064800,
3098                 .pa_end         = 0x48064cff,
3099         },
3100         {}
3101 };
3102
3103 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3104         .master         = &omap3xxx_l4_core_hwmod,
3105         .slave          = &omap3xxx_usb_host_hs_hwmod,
3106         .clk            = "usbhost_ick",
3107         .addr           = omap3xxx_usb_host_hs_addrs,
3108         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3109 };
3110
3111 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3112         {
3113                 .name           = "tll",
3114                 .pa_start       = 0x48062000,
3115                 .pa_end         = 0x48062fff,
3116                 .flags          = ADDR_TYPE_RT
3117         },
3118         {}
3119 };
3120
3121 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3122         .master         = &omap3xxx_l4_core_hwmod,
3123         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3124         .clk            = "usbtll_ick",
3125         .addr           = omap3xxx_usb_tll_hs_addrs,
3126         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3127 };
3128
3129 /* l4_core -> hdq1w interface */
3130 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3131         .master         = &omap3xxx_l4_core_hwmod,
3132         .slave          = &omap3xxx_hdq1w_hwmod,
3133         .clk            = "hdq_ick",
3134         .addr           = omap2_hdq1w_addr_space,
3135         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3136         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3137 };
3138
3139 /* l4_wkup -> 32ksync_counter */
3140 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3141         {
3142                 .pa_start       = 0x48320000,
3143                 .pa_end         = 0x4832001f,
3144                 .flags          = ADDR_TYPE_RT
3145         },
3146         { }
3147 };
3148
3149 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3150         .master         = &omap3xxx_l4_wkup_hwmod,
3151         .slave          = &omap3xxx_counter_32k_hwmod,
3152         .clk            = "omap_32ksync_ick",
3153         .addr           = omap3xxx_counter_32k_addrs,
3154         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3155 };
3156
3157 /* am35xx has Davinci MDIO & EMAC */
3158 static struct omap_hwmod_class am35xx_mdio_class = {
3159         .name = "davinci_mdio",
3160 };
3161
3162 static struct omap_hwmod am35xx_mdio_hwmod = {
3163         .name           = "davinci_mdio",
3164         .class          = &am35xx_mdio_class,
3165         .flags          = HWMOD_NO_IDLEST,
3166 };
3167
3168 /*
3169  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3170  * but this will probably require some additional hwmod core support,
3171  * so is left as a future to-do item.
3172  */
3173 static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
3174         .master         = &am35xx_mdio_hwmod,
3175         .slave          = &omap3xxx_l3_main_hwmod,
3176         .clk            = "emac_fck",
3177         .user           = OCP_USER_MPU,
3178 };
3179
3180 static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
3181         {
3182                 .pa_start       = AM35XX_IPSS_MDIO_BASE,
3183                 .pa_end         = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
3184                 .flags          = ADDR_TYPE_RT,
3185         },
3186         { }
3187 };
3188
3189 /* l4_core -> davinci mdio  */
3190 /*
3191  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3192  * but this will probably require some additional hwmod core support,
3193  * so is left as a future to-do item.
3194  */
3195 static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
3196         .master         = &omap3xxx_l4_core_hwmod,
3197         .slave          = &am35xx_mdio_hwmod,
3198         .clk            = "emac_fck",
3199         .addr           = am35xx_mdio_addrs,
3200         .user           = OCP_USER_MPU,
3201 };
3202
3203 static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
3204         { .name = "rxthresh",   .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
3205         { .name = "rx_pulse",   .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
3206         { .name = "tx_pulse",   .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
3207         { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
3208         { .irq = -1 }
3209 };
3210
3211 static struct omap_hwmod_class am35xx_emac_class = {
3212         .name = "davinci_emac",
3213 };
3214
3215 static struct omap_hwmod am35xx_emac_hwmod = {
3216         .name           = "davinci_emac",
3217         .mpu_irqs       = am35xx_emac_mpu_irqs,
3218         .class          = &am35xx_emac_class,
3219         .flags          = HWMOD_NO_IDLEST,
3220 };
3221
3222 /* l3_core -> davinci emac interface */
3223 /*
3224  * XXX Should be connected to an IPSS hwmod, not the L3 directly;
3225  * but this will probably require some additional hwmod core support,
3226  * so is left as a future to-do item.
3227  */
3228 static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
3229         .master         = &am35xx_emac_hwmod,
3230         .slave          = &omap3xxx_l3_main_hwmod,
3231         .clk            = "emac_ick",
3232         .user           = OCP_USER_MPU,
3233 };
3234
3235 static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
3236         {
3237                 .pa_start       = AM35XX_IPSS_EMAC_BASE,
3238                 .pa_end         = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
3239                 .flags          = ADDR_TYPE_RT,
3240         },
3241         { }
3242 };
3243
3244 /* l4_core -> davinci emac  */
3245 /*
3246  * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
3247  * but this will probably require some additional hwmod core support,
3248  * so is left as a future to-do item.
3249  */
3250 static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
3251         .master         = &omap3xxx_l4_core_hwmod,
3252         .slave          = &am35xx_emac_hwmod,
3253         .clk            = "emac_ick",
3254         .addr           = am35xx_emac_addrs,
3255         .user           = OCP_USER_MPU,
3256 };
3257
3258 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3259         &omap3xxx_l3_main__l4_core,
3260         &omap3xxx_l3_main__l4_per,
3261         &omap3xxx_mpu__l3_main,
3262         &omap3xxx_l4_core__l4_wkup,
3263         &omap3xxx_l4_core__mmc3,
3264         &omap3_l4_core__uart1,
3265         &omap3_l4_core__uart2,
3266         &omap3_l4_per__uart3,
3267         &omap3_l4_core__i2c1,
3268         &omap3_l4_core__i2c2,
3269         &omap3_l4_core__i2c3,
3270         &omap3xxx_l4_wkup__l4_sec,
3271         &omap3xxx_l4_wkup__timer1,
3272         &omap3xxx_l4_per__timer2,
3273         &omap3xxx_l4_per__timer3,
3274         &omap3xxx_l4_per__timer4,
3275         &omap3xxx_l4_per__timer5,
3276         &omap3xxx_l4_per__timer6,
3277         &omap3xxx_l4_per__timer7,
3278         &omap3xxx_l4_per__timer8,
3279         &omap3xxx_l4_per__timer9,
3280         &omap3xxx_l4_core__timer10,
3281         &omap3xxx_l4_core__timer11,
3282         &omap3xxx_l4_wkup__wd_timer2,
3283         &omap3xxx_l4_wkup__gpio1,
3284         &omap3xxx_l4_per__gpio2,
3285         &omap3xxx_l4_per__gpio3,
3286         &omap3xxx_l4_per__gpio4,
3287         &omap3xxx_l4_per__gpio5,
3288         &omap3xxx_l4_per__gpio6,
3289         &omap3xxx_dma_system__l3,
3290         &omap3xxx_l4_core__dma_system,
3291         &omap3xxx_l4_core__mcbsp1,
3292         &omap3xxx_l4_per__mcbsp2,
3293         &omap3xxx_l4_per__mcbsp3,
3294         &omap3xxx_l4_per__mcbsp4,
3295         &omap3xxx_l4_core__mcbsp5,
3296         &omap3xxx_l4_per__mcbsp2_sidetone,
3297         &omap3xxx_l4_per__mcbsp3_sidetone,
3298         &omap34xx_l4_core__mcspi1,
3299         &omap34xx_l4_core__mcspi2,
3300         &omap34xx_l4_core__mcspi3,
3301         &omap34xx_l4_core__mcspi4,
3302         &omap3xxx_l4_wkup__counter_32k,
3303         NULL,
3304 };
3305
3306 /* GP-only hwmod links */
3307 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3308         &omap3xxx_l4_sec__timer12,
3309         NULL
3310 };
3311
3312 /* 3430ES1-only hwmod links */
3313 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3314         &omap3430es1_dss__l3,
3315         &omap3430es1_l4_core__dss,
3316         NULL
3317 };
3318
3319 /* 3430ES2+-only hwmod links */
3320 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3321         &omap3xxx_dss__l3,
3322         &omap3xxx_l4_core__dss,
3323         &omap3xxx_usbhsotg__l3,
3324         &omap3xxx_l4_core__usbhsotg,
3325         &omap3xxx_usb_host_hs__l3_main_2,
3326         &omap3xxx_l4_core__usb_host_hs,
3327         &omap3xxx_l4_core__usb_tll_hs,
3328         NULL
3329 };
3330
3331 /* <= 3430ES3-only hwmod links */
3332 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3333         &omap3xxx_l4_core__pre_es3_mmc1,
3334         &omap3xxx_l4_core__pre_es3_mmc2,
3335         NULL
3336 };
3337
3338 /* 3430ES3+-only hwmod links */
3339 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3340         &omap3xxx_l4_core__es3plus_mmc1,
3341         &omap3xxx_l4_core__es3plus_mmc2,
3342         NULL
3343 };
3344
3345 /* 34xx-only hwmod links (all ES revisions) */
3346 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3347         &omap3xxx_l3__iva,
3348         &omap34xx_l4_core__sr1,
3349         &omap34xx_l4_core__sr2,
3350         &omap3xxx_l4_core__mailbox,
3351         &omap3xxx_l4_core__hdq1w,
3352         NULL
3353 };
3354
3355 /* 36xx-only hwmod links (all ES revisions) */
3356 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3357         &omap3xxx_l3__iva,
3358         &omap36xx_l4_per__uart4,
3359         &omap3xxx_dss__l3,
3360         &omap3xxx_l4_core__dss,
3361         &omap36xx_l4_core__sr1,
3362         &omap36xx_l4_core__sr2,
3363         &omap3xxx_usbhsotg__l3,
3364         &omap3xxx_l4_core__usbhsotg,
3365         &omap3xxx_l4_core__mailbox,
3366         &omap3xxx_usb_host_hs__l3_main_2,
3367         &omap3xxx_l4_core__usb_host_hs,
3368         &omap3xxx_l4_core__usb_tll_hs,
3369         &omap3xxx_l4_core__es3plus_mmc1,
3370         &omap3xxx_l4_core__es3plus_mmc2,
3371         &omap3xxx_l4_core__hdq1w,
3372         NULL
3373 };
3374
3375 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3376         &omap3xxx_dss__l3,
3377         &omap3xxx_l4_core__dss,
3378         &am35xx_usbhsotg__l3,
3379         &am35xx_l4_core__usbhsotg,
3380         &am35xx_l4_core__uart4,
3381         &omap3xxx_usb_host_hs__l3_main_2,
3382         &omap3xxx_l4_core__usb_host_hs,
3383         &omap3xxx_l4_core__usb_tll_hs,
3384         &omap3xxx_l4_core__es3plus_mmc1,
3385         &omap3xxx_l4_core__es3plus_mmc2,
3386         &am35xx_mdio__l3,
3387         &am35xx_l4_core__mdio,
3388         &am35xx_emac__l3,
3389         &am35xx_l4_core__emac,
3390         NULL
3391 };
3392
3393 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3394         &omap3xxx_l4_core__dss_dispc,
3395         &omap3xxx_l4_core__dss_dsi1,
3396         &omap3xxx_l4_core__dss_rfbi,
3397         &omap3xxx_l4_core__dss_venc,
3398         NULL
3399 };
3400
3401 int __init omap3xxx_hwmod_init(void)
3402 {
3403         int r;
3404         struct omap_hwmod_ocp_if **h = NULL;
3405         unsigned int rev;
3406
3407         /* Register hwmod links common to all OMAP3 */
3408         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3409         if (r < 0)
3410                 return r;
3411
3412         /* Register GP-only hwmod links. */
3413         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3414                 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3415                 if (r < 0)
3416                         return r;
3417         }
3418
3419         rev = omap_rev();
3420
3421         /*
3422          * Register hwmod links common to individual OMAP3 families, all
3423          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3424          * All possible revisions should be included in this conditional.
3425          */
3426         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3427             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3428             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3429                 h = omap34xx_hwmod_ocp_ifs;
3430         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3431                 h = am35xx_hwmod_ocp_ifs;
3432         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3433                    rev == OMAP3630_REV_ES1_2) {
3434                 h = omap36xx_hwmod_ocp_ifs;
3435         } else {
3436                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3437                 return -EINVAL;
3438         };
3439
3440         r = omap_hwmod_register_links(h);
3441         if (r < 0)
3442                 return r;
3443
3444         /*
3445          * Register hwmod links specific to certain ES levels of a
3446          * particular family of silicon (e.g., 34xx ES1.0)
3447          */
3448         h = NULL;
3449         if (rev == OMAP3430_REV_ES1_0) {
3450                 h = omap3430es1_hwmod_ocp_ifs;
3451         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3452                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3453                    rev == OMAP3430_REV_ES3_1_2) {
3454                 h = omap3430es2plus_hwmod_ocp_ifs;
3455         };
3456
3457         if (h) {
3458                 r = omap_hwmod_register_links(h);
3459                 if (r < 0)
3460                         return r;
3461         }
3462
3463         h = NULL;
3464         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3465             rev == OMAP3430_REV_ES2_1) {
3466                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3467         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3468                    rev == OMAP3430_REV_ES3_1_2) {
3469                 h = omap3430_es3plus_hwmod_ocp_ifs;
3470         };
3471
3472         if (h)
3473                 r = omap_hwmod_register_links(h);
3474         if (r < 0)
3475                 return r;
3476
3477         /*
3478          * DSS code presumes that dss_core hwmod is handled first,
3479          * _before_ any other DSS related hwmods so register common
3480          * DSS hwmod links last to ensure that dss_core is already
3481          * registered.  Otherwise some change things may happen, for
3482          * ex. if dispc is handled before dss_core and DSS is enabled
3483          * in bootloader DISPC will be reset with outputs enabled
3484          * which sometimes leads to unrecoverable L3 error.  XXX The
3485          * long-term fix to this is to ensure hwmods are set up in
3486          * dependency order in the hwmod core code.
3487          */
3488         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3489
3490         return r;
3491 }