arch/arm/mach-omap2/omap_hwmod_3xxx_data.c

   1 /*
   2  * omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
   3  *
   4  * Copyright (C) 2009-2011 Nokia Corporation
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  * Paul Walmsley
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * The data in this file should be completely autogeneratable from
  13  * the TI hardware database or other technical documentation.
  14  *
  15  * XXX these should be marked initdata for multi-OMAP kernels
  16  */
  17 #include <plat/omap_hwmod.h>
  18 #include <mach/irqs.h>
  19 #include <plat/cpu.h>
  20 #include <plat/dma.h>
  21 #include <plat/serial.h>
  22 #include <plat/l3_3xxx.h>
  23 #include <plat/l4_3xxx.h>
  24 #include <plat/i2c.h>
  25 #include <plat/gpio.h>
  26 #include <plat/mmc.h>
  27 #include <plat/mcbsp.h>
  28 #include <plat/mcspi.h>
  29 #include <plat/dmtimer.h>
  30
  31 #include "omap_hwmod_common_data.h"
  32
  33 #include "smartreflex.h"
  34 #include "prm-regbits-34xx.h"
  35 #include "cm-regbits-34xx.h"
  36 #include "wd_timer.h"
  37 #include <mach/am35xx.h>
  38
  39 /*
  40  * OMAP3xxx hardware module integration data
  41  *
  42  * All of the data in this section should be autogeneratable from the
  43  * TI hardware database or other technical documentation.  Data that
  44  * is driver-specific or driver-kernel integration-specific belongs
  45  * elsewhere.
  46  */
  47
  48 /*
  49  * IP blocks
  50  */
  51
  52 /* L3 */
  53 static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
  54         { .irq = INT_34XX_L3_DBG_IRQ },
  55         { .irq = INT_34XX_L3_APP_IRQ },
  56         { .irq = -1 }
  57 };
  58
  59 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
  60         .name           = "l3_main",
  61         .class          = &l3_hwmod_class,
  62         .mpu_irqs       = omap3xxx_l3_main_irqs,
  63         .flags          = HWMOD_NO_IDLEST,
  64 };
  65
  66 /* L4 CORE */
  67 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
  68         .name           = "l4_core",
  69         .class          = &l4_hwmod_class,
  70         .flags          = HWMOD_NO_IDLEST,
  71 };
  72
  73 /* L4 PER */
  74 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
  75         .name           = "l4_per",
  76         .class          = &l4_hwmod_class,
  77         .flags          = HWMOD_NO_IDLEST,
  78 };
  79
  80 /* L4 WKUP */
  81 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
  82         .name           = "l4_wkup",
  83         .class          = &l4_hwmod_class,
  84         .flags          = HWMOD_NO_IDLEST,
  85 };
  86
  87 /* L4 SEC */
  88 static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
  89         .name           = "l4_sec",
  90         .class          = &l4_hwmod_class,
  91         .flags          = HWMOD_NO_IDLEST,
  92 };
  93
  94 /* MPU */
  95 static struct omap_hwmod omap3xxx_mpu_hwmod = {
  96         .name           = "mpu",
  97         .class          = &mpu_hwmod_class,
  98         .main_clk       = "arm_fck",
  99 };
 100
 101 /* IVA2 (IVA2) */
 102 static struct omap_hwmod_rst_info omap3xxx_iva_resets[] = {
 103         { .name = "logic", .rst_shift = 0 },
 104         { .name = "seq0", .rst_shift = 1 },
 105         { .name = "seq1", .rst_shift = 2 },
 106 };
 107
 108 static struct omap_hwmod omap3xxx_iva_hwmod = {
 109         .name           = "iva",
 110         .class          = &iva_hwmod_class,
 111         .clkdm_name     = "iva2_clkdm",
 112         .rst_lines      = omap3xxx_iva_resets,
 113         .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_iva_resets),
 114         .main_clk       = "iva2_ck",
 115 };
 116
 117 /* timer class */
 118 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
 119         .rev_offs       = 0x0000,
 120         .sysc_offs      = 0x0010,
 121         .syss_offs      = 0x0014,
 122         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
 123                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 124                                 SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
 125         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 126         .sysc_fields    = &omap_hwmod_sysc_type1,
 127 };
 128
 129 static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
 130         .name = "timer",
 131         .sysc = &omap3xxx_timer_1ms_sysc,
 132         .rev = OMAP_TIMER_IP_VERSION_1,
 133 };
 134
 135 static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
 136         .rev_offs       = 0x0000,
 137         .sysc_offs      = 0x0010,
 138         .syss_offs      = 0x0014,
 139         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
 140                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 141         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 142         .sysc_fields    = &omap_hwmod_sysc_type1,
 143 };
 144
 145 static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
 146         .name = "timer",
 147         .sysc = &omap3xxx_timer_sysc,
 148         .rev =  OMAP_TIMER_IP_VERSION_1,
 149 };
 150
 151 /* secure timers dev attribute */
 152 static struct omap_timer_capability_dev_attr capability_secure_dev_attr = {
 153         .timer_capability       = OMAP_TIMER_ALWON | OMAP_TIMER_SECURE,
 154 };
 155
 156 /* always-on timers dev attribute */
 157 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 158         .timer_capability       = OMAP_TIMER_ALWON,
 159 };
 160
 161 /* pwm timers dev attribute */
 162 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 163         .timer_capability       = OMAP_TIMER_HAS_PWM,
 164 };
 165
 166 /* timer1 */
 167 static struct omap_hwmod omap3xxx_timer1_hwmod = {
 168         .name           = "timer1",
 169         .mpu_irqs       = omap2_timer1_mpu_irqs,
 170         .main_clk       = "gpt1_fck",
 171         .prcm           = {
 172                 .omap2 = {
 173                         .prcm_reg_id = 1,
 174                         .module_bit = OMAP3430_EN_GPT1_SHIFT,
 175                         .module_offs = WKUP_MOD,
 176                         .idlest_reg_id = 1,
 177                         .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
 178                 },
 179         },
 180         .dev_attr       = &capability_alwon_dev_attr,
 181         .class          = &omap3xxx_timer_1ms_hwmod_class,
 182 };
 183
 184 /* timer2 */
 185 static struct omap_hwmod omap3xxx_timer2_hwmod = {
 186         .name           = "timer2",
 187         .mpu_irqs       = omap2_timer2_mpu_irqs,
 188         .main_clk       = "gpt2_fck",
 189         .prcm           = {
 190                 .omap2 = {
 191                         .prcm_reg_id = 1,
 192                         .module_bit = OMAP3430_EN_GPT2_SHIFT,
 193                         .module_offs = OMAP3430_PER_MOD,
 194                         .idlest_reg_id = 1,
 195                         .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
 196                 },
 197         },
 198         .class          = &omap3xxx_timer_1ms_hwmod_class,
 199 };
 200
 201 /* timer3 */
 202 static struct omap_hwmod omap3xxx_timer3_hwmod = {
 203         .name           = "timer3",
 204         .mpu_irqs       = omap2_timer3_mpu_irqs,
 205         .main_clk       = "gpt3_fck",
 206         .prcm           = {
 207                 .omap2 = {
 208                         .prcm_reg_id = 1,
 209                         .module_bit = OMAP3430_EN_GPT3_SHIFT,
 210                         .module_offs = OMAP3430_PER_MOD,
 211                         .idlest_reg_id = 1,
 212                         .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
 213                 },
 214         },
 215         .class          = &omap3xxx_timer_hwmod_class,
 216 };
 217
 218 /* timer4 */
 219 static struct omap_hwmod omap3xxx_timer4_hwmod = {
 220         .name           = "timer4",
 221         .mpu_irqs       = omap2_timer4_mpu_irqs,
 222         .main_clk       = "gpt4_fck",
 223         .prcm           = {
 224                 .omap2 = {
 225                         .prcm_reg_id = 1,
 226                         .module_bit = OMAP3430_EN_GPT4_SHIFT,
 227                         .module_offs = OMAP3430_PER_MOD,
 228                         .idlest_reg_id = 1,
 229                         .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
 230                 },
 231         },
 232         .class          = &omap3xxx_timer_hwmod_class,
 233 };
 234
 235 /* timer5 */
 236 static struct omap_hwmod omap3xxx_timer5_hwmod = {
 237         .name           = "timer5",
 238         .mpu_irqs       = omap2_timer5_mpu_irqs,
 239         .main_clk       = "gpt5_fck",
 240         .prcm           = {
 241                 .omap2 = {
 242                         .prcm_reg_id = 1,
 243                         .module_bit = OMAP3430_EN_GPT5_SHIFT,
 244                         .module_offs = OMAP3430_PER_MOD,
 245                         .idlest_reg_id = 1,
 246                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
 247                 },
 248         },
 249         .class          = &omap3xxx_timer_hwmod_class,
 250 };
 251
 252 /* timer6 */
 253 static struct omap_hwmod omap3xxx_timer6_hwmod = {
 254         .name           = "timer6",
 255         .mpu_irqs       = omap2_timer6_mpu_irqs,
 256         .main_clk       = "gpt6_fck",
 257         .prcm           = {
 258                 .omap2 = {
 259                         .prcm_reg_id = 1,
 260                         .module_bit = OMAP3430_EN_GPT6_SHIFT,
 261                         .module_offs = OMAP3430_PER_MOD,
 262                         .idlest_reg_id = 1,
 263                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
 264                 },
 265         },
 266         .class          = &omap3xxx_timer_hwmod_class,
 267 };
 268
 269 /* timer7 */
 270 static struct omap_hwmod omap3xxx_timer7_hwmod = {
 271         .name           = "timer7",
 272         .mpu_irqs       = omap2_timer7_mpu_irqs,
 273         .main_clk       = "gpt7_fck",
 274         .prcm           = {
 275                 .omap2 = {
 276                         .prcm_reg_id = 1,
 277                         .module_bit = OMAP3430_EN_GPT7_SHIFT,
 278                         .module_offs = OMAP3430_PER_MOD,
 279                         .idlest_reg_id = 1,
 280                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
 281                 },
 282         },
 283         .class          = &omap3xxx_timer_hwmod_class,
 284 };
 285
 286 /* timer8 */
 287 static struct omap_hwmod omap3xxx_timer8_hwmod = {
 288         .name           = "timer8",
 289         .mpu_irqs       = omap2_timer8_mpu_irqs,
 290         .main_clk       = "gpt8_fck",
 291         .prcm           = {
 292                 .omap2 = {
 293                         .prcm_reg_id = 1,
 294                         .module_bit = OMAP3430_EN_GPT8_SHIFT,
 295                         .module_offs = OMAP3430_PER_MOD,
 296                         .idlest_reg_id = 1,
 297                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
 298                 },
 299         },
 300         .dev_attr       = &capability_pwm_dev_attr,
 301         .class          = &omap3xxx_timer_hwmod_class,
 302 };
 303
 304 /* timer9 */
 305 static struct omap_hwmod omap3xxx_timer9_hwmod = {
 306         .name           = "timer9",
 307         .mpu_irqs       = omap2_timer9_mpu_irqs,
 308         .main_clk       = "gpt9_fck",
 309         .prcm           = {
 310                 .omap2 = {
 311                         .prcm_reg_id = 1,
 312                         .module_bit = OMAP3430_EN_GPT9_SHIFT,
 313                         .module_offs = OMAP3430_PER_MOD,
 314                         .idlest_reg_id = 1,
 315                         .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
 316                 },
 317         },
 318         .dev_attr       = &capability_pwm_dev_attr,
 319         .class          = &omap3xxx_timer_hwmod_class,
 320 };
 321
 322 /* timer10 */
 323 static struct omap_hwmod omap3xxx_timer10_hwmod = {
 324         .name           = "timer10",
 325         .mpu_irqs       = omap2_timer10_mpu_irqs,
 326         .main_clk       = "gpt10_fck",
 327         .prcm           = {
 328                 .omap2 = {
 329                         .prcm_reg_id = 1,
 330                         .module_bit = OMAP3430_EN_GPT10_SHIFT,
 331                         .module_offs = CORE_MOD,
 332                         .idlest_reg_id = 1,
 333                         .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
 334                 },
 335         },
 336         .dev_attr       = &capability_pwm_dev_attr,
 337         .class          = &omap3xxx_timer_1ms_hwmod_class,
 338 };
 339
 340 /* timer11 */
 341 static struct omap_hwmod omap3xxx_timer11_hwmod = {
 342         .name           = "timer11",
 343         .mpu_irqs       = omap2_timer11_mpu_irqs,
 344         .main_clk       = "gpt11_fck",
 345         .prcm           = {
 346                 .omap2 = {
 347                         .prcm_reg_id = 1,
 348                         .module_bit = OMAP3430_EN_GPT11_SHIFT,
 349                         .module_offs = CORE_MOD,
 350                         .idlest_reg_id = 1,
 351                         .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
 352                 },
 353         },
 354         .dev_attr       = &capability_pwm_dev_attr,
 355         .class          = &omap3xxx_timer_hwmod_class,
 356 };
 357
 358 /* timer12 */
 359 static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
 360         { .irq = 95, },
 361         { .irq = -1 }
 362 };
 363
 364 static struct omap_hwmod omap3xxx_timer12_hwmod = {
 365         .name           = "timer12",
 366         .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
 367         .main_clk       = "gpt12_fck",
 368         .prcm           = {
 369                 .omap2 = {
 370                         .prcm_reg_id = 1,
 371                         .module_bit = OMAP3430_EN_GPT12_SHIFT,
 372                         .module_offs = WKUP_MOD,
 373                         .idlest_reg_id = 1,
 374                         .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
 375                 },
 376         },
 377         .dev_attr       = &capability_secure_dev_attr,
 378         .class          = &omap3xxx_timer_hwmod_class,
 379 };
 380
 381 /*
 382  * 'wd_timer' class
 383  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
 384  * overflow condition
 385  */
 386
 387 static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = {
 388         .rev_offs       = 0x0000,
 389         .sysc_offs      = 0x0010,
 390         .syss_offs      = 0x0014,
 391         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
 392                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 393                            SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 394                            SYSS_HAS_RESET_STATUS),
 395         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 396         .sysc_fields    = &omap_hwmod_sysc_type1,
 397 };
 398
 399 /* I2C common */
 400 static struct omap_hwmod_class_sysconfig i2c_sysc = {
 401         .rev_offs       = 0x00,
 402         .sysc_offs      = 0x20,
 403         .syss_offs      = 0x10,
 404         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 405                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 406                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 407         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 408         .clockact       = CLOCKACT_TEST_ICLK,
 409         .sysc_fields    = &omap_hwmod_sysc_type1,
 410 };
 411
 412 static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = {
 413         .name           = "wd_timer",
 414         .sysc           = &omap3xxx_wd_timer_sysc,
 415         .pre_shutdown   = &omap2_wd_timer_disable,
 416         .reset          = &omap2_wd_timer_reset,
 417 };
 418
 419 static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
 420         .name           = "wd_timer2",
 421         .class          = &omap3xxx_wd_timer_hwmod_class,
 422         .main_clk       = "wdt2_fck",
 423         .prcm           = {
 424                 .omap2 = {
 425                         .prcm_reg_id = 1,
 426                         .module_bit = OMAP3430_EN_WDT2_SHIFT,
 427                         .module_offs = WKUP_MOD,
 428                         .idlest_reg_id = 1,
 429                         .idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
 430                 },
 431         },
 432         /*
 433          * XXX: Use software supervised mode, HW supervised smartidle seems to
 434          * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
 435          */
 436         .flags          = HWMOD_SWSUP_SIDLE,
 437 };
 438
 439 /* UART1 */
 440 static struct omap_hwmod omap3xxx_uart1_hwmod = {
 441         .name           = "uart1",
 442         .mpu_irqs       = omap2_uart1_mpu_irqs,
 443         .sdma_reqs      = omap2_uart1_sdma_reqs,
 444         .main_clk       = "uart1_fck",
 445         .prcm           = {
 446                 .omap2 = {
 447                         .module_offs = CORE_MOD,
 448                         .prcm_reg_id = 1,
 449                         .module_bit = OMAP3430_EN_UART1_SHIFT,
 450                         .idlest_reg_id = 1,
 451                         .idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
 452                 },
 453         },
 454         .class          = &omap2_uart_class,
 455 };
 456
 457 /* UART2 */
 458 static struct omap_hwmod omap3xxx_uart2_hwmod = {
 459         .name           = "uart2",
 460         .mpu_irqs       = omap2_uart2_mpu_irqs,
 461         .sdma_reqs      = omap2_uart2_sdma_reqs,
 462         .main_clk       = "uart2_fck",
 463         .prcm           = {
 464                 .omap2 = {
 465                         .module_offs = CORE_MOD,
 466                         .prcm_reg_id = 1,
 467                         .module_bit = OMAP3430_EN_UART2_SHIFT,
 468                         .idlest_reg_id = 1,
 469                         .idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
 470                 },
 471         },
 472         .class          = &omap2_uart_class,
 473 };
 474
 475 /* UART3 */
 476 static struct omap_hwmod omap3xxx_uart3_hwmod = {
 477         .name           = "uart3",
 478         .mpu_irqs       = omap2_uart3_mpu_irqs,
 479         .sdma_reqs      = omap2_uart3_sdma_reqs,
 480         .main_clk       = "uart3_fck",
 481         .prcm           = {
 482                 .omap2 = {
 483                         .module_offs = OMAP3430_PER_MOD,
 484                         .prcm_reg_id = 1,
 485                         .module_bit = OMAP3430_EN_UART3_SHIFT,
 486                         .idlest_reg_id = 1,
 487                         .idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
 488                 },
 489         },
 490         .class          = &omap2_uart_class,
 491 };
 492
 493 /* UART4 */
 494 static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
 495         { .irq = INT_36XX_UART4_IRQ, },
 496         { .irq = -1 }
 497 };
 498
 499 static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
 500         { .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
 501         { .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
 502         { .dma_req = -1 }
 503 };
 504
 505 static struct omap_hwmod omap36xx_uart4_hwmod = {
 506         .name           = "uart4",
 507         .mpu_irqs       = uart4_mpu_irqs,
 508         .sdma_reqs      = uart4_sdma_reqs,
 509         .main_clk       = "uart4_fck",
 510         .prcm           = {
 511                 .omap2 = {
 512                         .module_offs = OMAP3430_PER_MOD,
 513                         .prcm_reg_id = 1,
 514                         .module_bit = OMAP3630_EN_UART4_SHIFT,
 515                         .idlest_reg_id = 1,
 516                         .idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
 517                 },
 518         },
 519         .class          = &omap2_uart_class,
 520 };
 521
 522 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
 523         { .irq = INT_35XX_UART4_IRQ, },
 524 };
 525
 526 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 527         { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
 528         { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
 529 };
 530
 531 static struct omap_hwmod am35xx_uart4_hwmod = {
 532         .name           = "uart4",
 533         .mpu_irqs       = am35xx_uart4_mpu_irqs,
 534         .sdma_reqs      = am35xx_uart4_sdma_reqs,
 535         .main_clk       = "uart4_fck",
 536         .prcm           = {
 537                 .omap2 = {
 538                         .module_offs = CORE_MOD,
 539                         .prcm_reg_id = 1,
 540                         .module_bit = OMAP3430_EN_UART4_SHIFT,
 541                         .idlest_reg_id = 1,
 542                         .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
 543                 },
 544         },
 545         .class          = &omap2_uart_class,
 546 };
 547
 548 static struct omap_hwmod_class i2c_class = {
 549         .name   = "i2c",
 550         .sysc   = &i2c_sysc,
 551         .rev    = OMAP_I2C_IP_VERSION_1,
 552         .reset  = &omap_i2c_reset,
 553 };
 554
 555 static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
 556         { .name = "dispc", .dma_req = 5 },
 557         { .name = "dsi1", .dma_req = 74 },
 558         { .dma_req = -1 }
 559 };
 560
 561 /* dss */
 562 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 563         /*
 564          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 565          * driver does not use these clocks.
 566          */
 567         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 568         { .role = "tv_clk", .clk = "dss_tv_fck" },
 569         /* required only on OMAP3430 */
 570         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 571 };
 572
 573 static struct omap_hwmod omap3430es1_dss_core_hwmod = {
 574         .name           = "dss_core",
 575         .class          = &omap2_dss_hwmod_class,
 576         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 577         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 578         .prcm           = {
 579                 .omap2 = {
 580                         .prcm_reg_id = 1,
 581                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 582                         .module_offs = OMAP3430_DSS_MOD,
 583                         .idlest_reg_id = 1,
 584                         .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
 585                 },
 586         },
 587         .opt_clks       = dss_opt_clks,
 588         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 589         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 590 };
 591
 592 static struct omap_hwmod omap3xxx_dss_core_hwmod = {
 593         .name           = "dss_core",
 594         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 595         .class          = &omap2_dss_hwmod_class,
 596         .main_clk       = "dss1_alwon_fck", /* instead of dss_fck */
 597         .sdma_reqs      = omap3xxx_dss_sdma_chs,
 598         .prcm           = {
 599                 .omap2 = {
 600                         .prcm_reg_id = 1,
 601                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 602                         .module_offs = OMAP3430_DSS_MOD,
 603                         .idlest_reg_id = 1,
 604                         .idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
 605                         .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
 606                 },
 607         },
 608         .opt_clks       = dss_opt_clks,
 609         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 610 };
 611
 612 /*
 613  * 'dispc' class
 614  * display controller
 615  */
 616
 617 static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
 618         .rev_offs       = 0x0000,
 619         .sysc_offs      = 0x0010,
 620         .syss_offs      = 0x0014,
 621         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
 622                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 623                            SYSC_HAS_ENAWAKEUP),
 624         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 625                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 626         .sysc_fields    = &omap_hwmod_sysc_type1,
 627 };
 628
 629 static struct omap_hwmod_class omap3_dispc_hwmod_class = {
 630         .name   = "dispc",
 631         .sysc   = &omap3_dispc_sysc,
 632 };
 633
 634 static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
 635         .name           = "dss_dispc",
 636         .class          = &omap3_dispc_hwmod_class,
 637         .mpu_irqs       = omap2_dispc_irqs,
 638         .main_clk       = "dss1_alwon_fck",
 639         .prcm           = {
 640                 .omap2 = {
 641                         .prcm_reg_id = 1,
 642                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 643                         .module_offs = OMAP3430_DSS_MOD,
 644                 },
 645         },
 646         .flags          = HWMOD_NO_IDLEST,
 647         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 648 };
 649
 650 /*
 651  * 'dsi' class
 652  * display serial interface controller
 653  */
 654
 655 static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
 656         .name = "dsi",
 657 };
 658
 659 static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
 660         { .irq = 25 },
 661         { .irq = -1 }
 662 };
 663
 664 /* dss_dsi1 */
 665 static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 666         { .role = "sys_clk", .clk = "dss2_alwon_fck" },
 667 };
 668
 669 static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
 670         .name           = "dss_dsi1",
 671         .class          = &omap3xxx_dsi_hwmod_class,
 672         .mpu_irqs       = omap3xxx_dsi1_irqs,
 673         .main_clk       = "dss1_alwon_fck",
 674         .prcm           = {
 675                 .omap2 = {
 676                         .prcm_reg_id = 1,
 677                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 678                         .module_offs = OMAP3430_DSS_MOD,
 679                 },
 680         },
 681         .opt_clks       = dss_dsi1_opt_clks,
 682         .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_opt_clks),
 683         .flags          = HWMOD_NO_IDLEST,
 684 };
 685
 686 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 687         { .role = "ick", .clk = "dss_ick" },
 688 };
 689
 690 static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
 691         .name           = "dss_rfbi",
 692         .class          = &omap2_rfbi_hwmod_class,
 693         .main_clk       = "dss1_alwon_fck",
 694         .prcm           = {
 695                 .omap2 = {
 696                         .prcm_reg_id = 1,
 697                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 698                         .module_offs = OMAP3430_DSS_MOD,
 699                 },
 700         },
 701         .opt_clks       = dss_rfbi_opt_clks,
 702         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 703         .flags          = HWMOD_NO_IDLEST,
 704 };
 705
 706 static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 707         /* required only on OMAP3430 */
 708         { .role = "tv_dac_clk", .clk = "dss_96m_fck" },
 709 };
 710
 711 static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
 712         .name           = "dss_venc",
 713         .class          = &omap2_venc_hwmod_class,
 714         .main_clk       = "dss_tv_fck",
 715         .prcm           = {
 716                 .omap2 = {
 717                         .prcm_reg_id = 1,
 718                         .module_bit = OMAP3430_EN_DSS1_SHIFT,
 719                         .module_offs = OMAP3430_DSS_MOD,
 720                 },
 721         },
 722         .opt_clks       = dss_venc_opt_clks,
 723         .opt_clks_cnt   = ARRAY_SIZE(dss_venc_opt_clks),
 724         .flags          = HWMOD_NO_IDLEST,
 725 };
 726
 727 /* I2C1 */
 728 static struct omap_i2c_dev_attr i2c1_dev_attr = {
 729         .fifo_depth     = 8, /* bytes */
 730         .flags          = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 731                           OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 732                           OMAP_I2C_FLAG_BUS_SHIFT_2,
 733 };
 734
 735 static struct omap_hwmod omap3xxx_i2c1_hwmod = {
 736         .name           = "i2c1",
 737         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 738         .mpu_irqs       = omap2_i2c1_mpu_irqs,
 739         .sdma_reqs      = omap2_i2c1_sdma_reqs,
 740         .main_clk       = "i2c1_fck",
 741         .prcm           = {
 742                 .omap2 = {
 743                         .module_offs = CORE_MOD,
 744                         .prcm_reg_id = 1,
 745                         .module_bit = OMAP3430_EN_I2C1_SHIFT,
 746                         .idlest_reg_id = 1,
 747                         .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
 748                 },
 749         },
 750         .class          = &i2c_class,
 751         .dev_attr       = &i2c1_dev_attr,
 752 };
 753
 754 /* I2C2 */
 755 static struct omap_i2c_dev_attr i2c2_dev_attr = {
 756         .fifo_depth     = 8, /* bytes */
 757         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 758                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 759                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 760 };
 761
 762 static struct omap_hwmod omap3xxx_i2c2_hwmod = {
 763         .name           = "i2c2",
 764         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 765         .mpu_irqs       = omap2_i2c2_mpu_irqs,
 766         .sdma_reqs      = omap2_i2c2_sdma_reqs,
 767         .main_clk       = "i2c2_fck",
 768         .prcm           = {
 769                 .omap2 = {
 770                         .module_offs = CORE_MOD,
 771                         .prcm_reg_id = 1,
 772                         .module_bit = OMAP3430_EN_I2C2_SHIFT,
 773                         .idlest_reg_id = 1,
 774                         .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
 775                 },
 776         },
 777         .class          = &i2c_class,
 778         .dev_attr       = &i2c2_dev_attr,
 779 };
 780
 781 /* I2C3 */
 782 static struct omap_i2c_dev_attr i2c3_dev_attr = {
 783         .fifo_depth     = 64, /* bytes */
 784         .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
 785                  OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
 786                  OMAP_I2C_FLAG_BUS_SHIFT_2,
 787 };
 788
 789 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
 790         { .irq = INT_34XX_I2C3_IRQ, },
 791         { .irq = -1 }
 792 };
 793
 794 static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
 795         { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
 796         { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
 797         { .dma_req = -1 }
 798 };
 799
 800 static struct omap_hwmod omap3xxx_i2c3_hwmod = {
 801         .name           = "i2c3",
 802         .flags          = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
 803         .mpu_irqs       = i2c3_mpu_irqs,
 804         .sdma_reqs      = i2c3_sdma_reqs,
 805         .main_clk       = "i2c3_fck",
 806         .prcm           = {
 807                 .omap2 = {
 808                         .module_offs = CORE_MOD,
 809                         .prcm_reg_id = 1,
 810                         .module_bit = OMAP3430_EN_I2C3_SHIFT,
 811                         .idlest_reg_id = 1,
 812                         .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
 813                 },
 814         },
 815         .class          = &i2c_class,
 816         .dev_attr       = &i2c3_dev_attr,
 817 };
 818
 819 /*
 820  * 'gpio' class
 821  * general purpose io module
 822  */
 823
 824 static struct omap_hwmod_class_sysconfig omap3xxx_gpio_sysc = {
 825         .rev_offs       = 0x0000,
 826         .sysc_offs      = 0x0010,
 827         .syss_offs      = 0x0014,
 828         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 829                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 830                            SYSS_HAS_RESET_STATUS),
 831         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 832         .sysc_fields    = &omap_hwmod_sysc_type1,
 833 };
 834
 835 static struct omap_hwmod_class omap3xxx_gpio_hwmod_class = {
 836         .name = "gpio",
 837         .sysc = &omap3xxx_gpio_sysc,
 838         .rev = 1,
 839 };
 840
 841 /* gpio_dev_attr */
 842 static struct omap_gpio_dev_attr gpio_dev_attr = {
 843         .bank_width = 32,
 844         .dbck_flag = true,
 845 };
 846
 847 /* gpio1 */
 848 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
 849         { .role = "dbclk", .clk = "gpio1_dbck", },
 850 };
 851
 852 static struct omap_hwmod omap3xxx_gpio1_hwmod = {
 853         .name           = "gpio1",
 854         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 855         .mpu_irqs       = omap2_gpio1_irqs,
 856         .main_clk       = "gpio1_ick",
 857         .opt_clks       = gpio1_opt_clks,
 858         .opt_clks_cnt   = ARRAY_SIZE(gpio1_opt_clks),
 859         .prcm           = {
 860                 .omap2 = {
 861                         .prcm_reg_id = 1,
 862                         .module_bit = OMAP3430_EN_GPIO1_SHIFT,
 863                         .module_offs = WKUP_MOD,
 864                         .idlest_reg_id = 1,
 865                         .idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
 866                 },
 867         },
 868         .class          = &omap3xxx_gpio_hwmod_class,
 869         .dev_attr       = &gpio_dev_attr,
 870 };
 871
 872 /* gpio2 */
 873 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
 874         { .role = "dbclk", .clk = "gpio2_dbck", },
 875 };
 876
 877 static struct omap_hwmod omap3xxx_gpio2_hwmod = {
 878         .name           = "gpio2",
 879         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 880         .mpu_irqs       = omap2_gpio2_irqs,
 881         .main_clk       = "gpio2_ick",
 882         .opt_clks       = gpio2_opt_clks,
 883         .opt_clks_cnt   = ARRAY_SIZE(gpio2_opt_clks),
 884         .prcm           = {
 885                 .omap2 = {
 886                         .prcm_reg_id = 1,
 887                         .module_bit = OMAP3430_EN_GPIO2_SHIFT,
 888                         .module_offs = OMAP3430_PER_MOD,
 889                         .idlest_reg_id = 1,
 890                         .idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
 891                 },
 892         },
 893         .class          = &omap3xxx_gpio_hwmod_class,
 894         .dev_attr       = &gpio_dev_attr,
 895 };
 896
 897 /* gpio3 */
 898 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
 899         { .role = "dbclk", .clk = "gpio3_dbck", },
 900 };
 901
 902 static struct omap_hwmod omap3xxx_gpio3_hwmod = {
 903         .name           = "gpio3",
 904         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 905         .mpu_irqs       = omap2_gpio3_irqs,
 906         .main_clk       = "gpio3_ick",
 907         .opt_clks       = gpio3_opt_clks,
 908         .opt_clks_cnt   = ARRAY_SIZE(gpio3_opt_clks),
 909         .prcm           = {
 910                 .omap2 = {
 911                         .prcm_reg_id = 1,
 912                         .module_bit = OMAP3430_EN_GPIO3_SHIFT,
 913                         .module_offs = OMAP3430_PER_MOD,
 914                         .idlest_reg_id = 1,
 915                         .idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
 916                 },
 917         },
 918         .class          = &omap3xxx_gpio_hwmod_class,
 919         .dev_attr       = &gpio_dev_attr,
 920 };
 921
 922 /* gpio4 */
 923 static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
 924         { .role = "dbclk", .clk = "gpio4_dbck", },
 925 };
 926
 927 static struct omap_hwmod omap3xxx_gpio4_hwmod = {
 928         .name           = "gpio4",
 929         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 930         .mpu_irqs       = omap2_gpio4_irqs,
 931         .main_clk       = "gpio4_ick",
 932         .opt_clks       = gpio4_opt_clks,
 933         .opt_clks_cnt   = ARRAY_SIZE(gpio4_opt_clks),
 934         .prcm           = {
 935                 .omap2 = {
 936                         .prcm_reg_id = 1,
 937                         .module_bit = OMAP3430_EN_GPIO4_SHIFT,
 938                         .module_offs = OMAP3430_PER_MOD,
 939                         .idlest_reg_id = 1,
 940                         .idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
 941                 },
 942         },
 943         .class          = &omap3xxx_gpio_hwmod_class,
 944         .dev_attr       = &gpio_dev_attr,
 945 };
 946
 947 /* gpio5 */
 948 static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
 949         { .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
 950         { .irq = -1 }
 951 };
 952
 953 static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
 954         { .role = "dbclk", .clk = "gpio5_dbck", },
 955 };
 956
 957 static struct omap_hwmod omap3xxx_gpio5_hwmod = {
 958         .name           = "gpio5",
 959         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 960         .mpu_irqs       = omap3xxx_gpio5_irqs,
 961         .main_clk       = "gpio5_ick",
 962         .opt_clks       = gpio5_opt_clks,
 963         .opt_clks_cnt   = ARRAY_SIZE(gpio5_opt_clks),
 964         .prcm           = {
 965                 .omap2 = {
 966                         .prcm_reg_id = 1,
 967                         .module_bit = OMAP3430_EN_GPIO5_SHIFT,
 968                         .module_offs = OMAP3430_PER_MOD,
 969                         .idlest_reg_id = 1,
 970                         .idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
 971                 },
 972         },
 973         .class          = &omap3xxx_gpio_hwmod_class,
 974         .dev_attr       = &gpio_dev_attr,
 975 };
 976
 977 /* gpio6 */
 978 static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
 979         { .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
 980         { .irq = -1 }
 981 };
 982
 983 static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
 984         { .role = "dbclk", .clk = "gpio6_dbck", },
 985 };
 986
 987 static struct omap_hwmod omap3xxx_gpio6_hwmod = {
 988         .name           = "gpio6",
 989         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 990         .mpu_irqs       = omap3xxx_gpio6_irqs,
 991         .main_clk       = "gpio6_ick",
 992         .opt_clks       = gpio6_opt_clks,
 993         .opt_clks_cnt   = ARRAY_SIZE(gpio6_opt_clks),
 994         .prcm           = {
 995                 .omap2 = {
 996                         .prcm_reg_id = 1,
 997                         .module_bit = OMAP3430_EN_GPIO6_SHIFT,
 998                         .module_offs = OMAP3430_PER_MOD,
 999                         .idlest_reg_id = 1,
1000                         .idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
1001                 },
1002         },
1003         .class          = &omap3xxx_gpio_hwmod_class,
1004         .dev_attr       = &gpio_dev_attr,
1005 };
1006
1007 /* dma attributes */
1008 static struct omap_dma_dev_attr dma_dev_attr = {
1009         .dev_caps  = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
1010                                 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
1011         .lch_count = 32,
1012 };
1013
1014 static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
1015         .rev_offs       = 0x0000,
1016         .sysc_offs      = 0x002c,
1017         .syss_offs      = 0x0028,
1018         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1019                            SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1020                            SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE |
1021                            SYSS_HAS_RESET_STATUS),
1022         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1023                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1024         .sysc_fields    = &omap_hwmod_sysc_type1,
1025 };
1026
1027 static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
1028         .name = "dma",
1029         .sysc = &omap3xxx_dma_sysc,
1030 };
1031
1032 /* dma_system */
1033 static struct omap_hwmod omap3xxx_dma_system_hwmod = {
1034         .name           = "dma",
1035         .class          = &omap3xxx_dma_hwmod_class,
1036         .mpu_irqs       = omap2_dma_system_irqs,
1037         .main_clk       = "core_l3_ick",
1038         .prcm = {
1039                 .omap2 = {
1040                         .module_offs            = CORE_MOD,
1041                         .prcm_reg_id            = 1,
1042                         .module_bit             = OMAP3430_ST_SDMA_SHIFT,
1043                         .idlest_reg_id          = 1,
1044                         .idlest_idle_bit        = OMAP3430_ST_SDMA_SHIFT,
1045                 },
1046         },
1047         .dev_attr       = &dma_dev_attr,
1048         .flags          = HWMOD_NO_IDLEST,
1049 };
1050
1051 /*
1052  * 'mcbsp' class
1053  * multi channel buffered serial port controller
1054  */
1055
1056 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
1057         .sysc_offs      = 0x008c,
1058         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1059                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1060         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1061         .sysc_fields    = &omap_hwmod_sysc_type1,
1062         .clockact       = 0x2,
1063 };
1064
1065 static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
1066         .name = "mcbsp",
1067         .sysc = &omap3xxx_mcbsp_sysc,
1068         .rev  = MCBSP_CONFIG_TYPE3,
1069 };
1070
1071 /* mcbsp1 */
1072 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
1073         { .name = "common", .irq = 16 },
1074         { .name = "tx", .irq = 59 },
1075         { .name = "rx", .irq = 60 },
1076         { .irq = -1 }
1077 };
1078
1079 static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
1080         .name           = "mcbsp1",
1081         .class          = &omap3xxx_mcbsp_hwmod_class,
1082         .mpu_irqs       = omap3xxx_mcbsp1_irqs,
1083         .sdma_reqs      = omap2_mcbsp1_sdma_reqs,
1084         .main_clk       = "mcbsp1_fck",
1085         .prcm           = {
1086                 .omap2 = {
1087                         .prcm_reg_id = 1,
1088                         .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
1089                         .module_offs = CORE_MOD,
1090                         .idlest_reg_id = 1,
1091                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
1092                 },
1093         },
1094 };
1095
1096 /* mcbsp2 */
1097 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
1098         { .name = "common", .irq = 17 },
1099         { .name = "tx", .irq = 62 },
1100         { .name = "rx", .irq = 63 },
1101         { .irq = -1 }
1102 };
1103
1104 static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
1105         .sidetone       = "mcbsp2_sidetone",
1106 };
1107
1108 static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
1109         .name           = "mcbsp2",
1110         .class          = &omap3xxx_mcbsp_hwmod_class,
1111         .mpu_irqs       = omap3xxx_mcbsp2_irqs,
1112         .sdma_reqs      = omap2_mcbsp2_sdma_reqs,
1113         .main_clk       = "mcbsp2_fck",
1114         .prcm           = {
1115                 .omap2 = {
1116                         .prcm_reg_id = 1,
1117                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1118                         .module_offs = OMAP3430_PER_MOD,
1119                         .idlest_reg_id = 1,
1120                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1121                 },
1122         },
1123         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
1124 };
1125
1126 /* mcbsp3 */
1127 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
1128         { .name = "common", .irq = 22 },
1129         { .name = "tx", .irq = 89 },
1130         { .name = "rx", .irq = 90 },
1131         { .irq = -1 }
1132 };
1133
1134 static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
1135         .sidetone       = "mcbsp3_sidetone",
1136 };
1137
1138 static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
1139         .name           = "mcbsp3",
1140         .class          = &omap3xxx_mcbsp_hwmod_class,
1141         .mpu_irqs       = omap3xxx_mcbsp3_irqs,
1142         .sdma_reqs      = omap2_mcbsp3_sdma_reqs,
1143         .main_clk       = "mcbsp3_fck",
1144         .prcm           = {
1145                 .omap2 = {
1146                         .prcm_reg_id = 1,
1147                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1148                         .module_offs = OMAP3430_PER_MOD,
1149                         .idlest_reg_id = 1,
1150                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1151                 },
1152         },
1153         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
1154 };
1155
1156 /* mcbsp4 */
1157 static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
1158         { .name = "common", .irq = 23 },
1159         { .name = "tx", .irq = 54 },
1160         { .name = "rx", .irq = 55 },
1161         { .irq = -1 }
1162 };
1163
1164 static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
1165         { .name = "rx", .dma_req = 20 },
1166         { .name = "tx", .dma_req = 19 },
1167         { .dma_req = -1 }
1168 };
1169
1170 static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
1171         .name           = "mcbsp4",
1172         .class          = &omap3xxx_mcbsp_hwmod_class,
1173         .mpu_irqs       = omap3xxx_mcbsp4_irqs,
1174         .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
1175         .main_clk       = "mcbsp4_fck",
1176         .prcm           = {
1177                 .omap2 = {
1178                         .prcm_reg_id = 1,
1179                         .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
1180                         .module_offs = OMAP3430_PER_MOD,
1181                         .idlest_reg_id = 1,
1182                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
1183                 },
1184         },
1185 };
1186
1187 /* mcbsp5 */
1188 static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
1189         { .name = "common", .irq = 27 },
1190         { .name = "tx", .irq = 81 },
1191         { .name = "rx", .irq = 82 },
1192         { .irq = -1 }
1193 };
1194
1195 static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
1196         { .name = "rx", .dma_req = 22 },
1197         { .name = "tx", .dma_req = 21 },
1198         { .dma_req = -1 }
1199 };
1200
1201 static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
1202         .name           = "mcbsp5",
1203         .class          = &omap3xxx_mcbsp_hwmod_class,
1204         .mpu_irqs       = omap3xxx_mcbsp5_irqs,
1205         .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
1206         .main_clk       = "mcbsp5_fck",
1207         .prcm           = {
1208                 .omap2 = {
1209                         .prcm_reg_id = 1,
1210                         .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
1211                         .module_offs = CORE_MOD,
1212                         .idlest_reg_id = 1,
1213                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
1214                 },
1215         },
1216 };
1217
1218 /* 'mcbsp sidetone' class */
1219 static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
1220         .sysc_offs      = 0x0010,
1221         .sysc_flags     = SYSC_HAS_AUTOIDLE,
1222         .sysc_fields    = &omap_hwmod_sysc_type1,
1223 };
1224
1225 static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
1226         .name = "mcbsp_sidetone",
1227         .sysc = &omap3xxx_mcbsp_sidetone_sysc,
1228 };
1229
1230 /* mcbsp2_sidetone */
1231 static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
1232         { .name = "irq", .irq = 4 },
1233         { .irq = -1 }
1234 };
1235
1236 static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
1237         .name           = "mcbsp2_sidetone",
1238         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1239         .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
1240         .main_clk       = "mcbsp2_fck",
1241         .prcm           = {
1242                 .omap2 = {
1243                         .prcm_reg_id = 1,
1244                          .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
1245                         .module_offs = OMAP3430_PER_MOD,
1246                         .idlest_reg_id = 1,
1247                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
1248                 },
1249         },
1250 };
1251
1252 /* mcbsp3_sidetone */
1253 static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
1254         { .name = "irq", .irq = 5 },
1255         { .irq = -1 }
1256 };
1257
1258 static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
1259         .name           = "mcbsp3_sidetone",
1260         .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
1261         .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
1262         .main_clk       = "mcbsp3_fck",
1263         .prcm           = {
1264                 .omap2 = {
1265                         .prcm_reg_id = 1,
1266                         .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
1267                         .module_offs = OMAP3430_PER_MOD,
1268                         .idlest_reg_id = 1,
1269                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
1270                 },
1271         },
1272 };
1273
1274 /* SR common */
1275 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
1276         .clkact_shift   = 20,
1277 };
1278
1279 static struct omap_hwmod_class_sysconfig omap34xx_sr_sysc = {
1280         .sysc_offs      = 0x24,
1281         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_NO_CACHE),
1282         .clockact       = CLOCKACT_TEST_ICLK,
1283         .sysc_fields    = &omap34xx_sr_sysc_fields,
1284 };
1285
1286 static struct omap_hwmod_class omap34xx_smartreflex_hwmod_class = {
1287         .name = "smartreflex",
1288         .sysc = &omap34xx_sr_sysc,
1289         .rev  = 1,
1290 };
1291
1292 static struct omap_hwmod_sysc_fields omap36xx_sr_sysc_fields = {
1293         .sidle_shift    = 24,
1294         .enwkup_shift   = 26,
1295 };
1296
1297 static struct omap_hwmod_class_sysconfig omap36xx_sr_sysc = {
1298         .sysc_offs      = 0x38,
1299         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1300         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1301                         SYSC_NO_CACHE),
1302         .sysc_fields    = &omap36xx_sr_sysc_fields,
1303 };
1304
1305 static struct omap_hwmod_class omap36xx_smartreflex_hwmod_class = {
1306         .name = "smartreflex",
1307         .sysc = &omap36xx_sr_sysc,
1308         .rev  = 2,
1309 };
1310
1311 /* SR1 */
1312 static struct omap_smartreflex_dev_attr sr1_dev_attr = {
1313         .sensor_voltdm_name   = "mpu_iva",
1314 };
1315
1316 static struct omap_hwmod_irq_info omap3_smartreflex_mpu_irqs[] = {
1317         { .irq = 18 },
1318         { .irq = -1 }
1319 };
1320
1321 static struct omap_hwmod omap34xx_sr1_hwmod = {
1322         .name           = "sr1",
1323         .class          = &omap34xx_smartreflex_hwmod_class,
1324         .main_clk       = "sr1_fck",
1325         .prcm           = {
1326                 .omap2 = {
1327                         .prcm_reg_id = 1,
1328                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1329                         .module_offs = WKUP_MOD,
1330                         .idlest_reg_id = 1,
1331                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1332                 },
1333         },
1334         .dev_attr       = &sr1_dev_attr,
1335         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1336         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1337 };
1338
1339 static struct omap_hwmod omap36xx_sr1_hwmod = {
1340         .name           = "sr1",
1341         .class          = &omap36xx_smartreflex_hwmod_class,
1342         .main_clk       = "sr1_fck",
1343         .prcm           = {
1344                 .omap2 = {
1345                         .prcm_reg_id = 1,
1346                         .module_bit = OMAP3430_EN_SR1_SHIFT,
1347                         .module_offs = WKUP_MOD,
1348                         .idlest_reg_id = 1,
1349                         .idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
1350                 },
1351         },
1352         .dev_attr       = &sr1_dev_attr,
1353         .mpu_irqs       = omap3_smartreflex_mpu_irqs,
1354 };
1355
1356 /* SR2 */
1357 static struct omap_smartreflex_dev_attr sr2_dev_attr = {
1358         .sensor_voltdm_name     = "core",
1359 };
1360
1361 static struct omap_hwmod_irq_info omap3_smartreflex_core_irqs[] = {
1362         { .irq = 19 },
1363         { .irq = -1 }
1364 };
1365
1366 static struct omap_hwmod omap34xx_sr2_hwmod = {
1367         .name           = "sr2",
1368         .class          = &omap34xx_smartreflex_hwmod_class,
1369         .main_clk       = "sr2_fck",
1370         .prcm           = {
1371                 .omap2 = {
1372                         .prcm_reg_id = 1,
1373                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1374                         .module_offs = WKUP_MOD,
1375                         .idlest_reg_id = 1,
1376                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1377                 },
1378         },
1379         .dev_attr       = &sr2_dev_attr,
1380         .mpu_irqs       = omap3_smartreflex_core_irqs,
1381         .flags          = HWMOD_SET_DEFAULT_CLOCKACT,
1382 };
1383
1384 static struct omap_hwmod omap36xx_sr2_hwmod = {
1385         .name           = "sr2",
1386         .class          = &omap36xx_smartreflex_hwmod_class,
1387         .main_clk       = "sr2_fck",
1388         .prcm           = {
1389                 .omap2 = {
1390                         .prcm_reg_id = 1,
1391                         .module_bit = OMAP3430_EN_SR2_SHIFT,
1392                         .module_offs = WKUP_MOD,
1393                         .idlest_reg_id = 1,
1394                         .idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
1395                 },
1396         },
1397         .dev_attr       = &sr2_dev_attr,
1398         .mpu_irqs       = omap3_smartreflex_core_irqs,
1399 };
1400
1401 /*
1402  * 'mailbox' class
1403  * mailbox module allowing communication between the on-chip processors
1404  * using a queued mailbox-interrupt mechanism.
1405  */
1406
1407 static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
1408         .rev_offs       = 0x000,
1409         .sysc_offs      = 0x010,
1410         .syss_offs      = 0x014,
1411         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1412                                 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1413         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1414         .sysc_fields    = &omap_hwmod_sysc_type1,
1415 };
1416
1417 static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
1418         .name = "mailbox",
1419         .sysc = &omap3xxx_mailbox_sysc,
1420 };
1421
1422 static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
1423         { .irq = 26 },
1424         { .irq = -1 }
1425 };
1426
1427 static struct omap_hwmod omap3xxx_mailbox_hwmod = {
1428         .name           = "mailbox",
1429         .class          = &omap3xxx_mailbox_hwmod_class,
1430         .mpu_irqs       = omap3xxx_mailbox_irqs,
1431         .main_clk       = "mailboxes_ick",
1432         .prcm           = {
1433                 .omap2 = {
1434                         .prcm_reg_id = 1,
1435                         .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
1436                         .module_offs = CORE_MOD,
1437                         .idlest_reg_id = 1,
1438                         .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
1439                 },
1440         },
1441 };
1442
1443 /*
1444  * 'mcspi' class
1445  * multichannel serial port interface (mcspi) / master/slave synchronous serial
1446  * bus
1447  */
1448
1449 static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
1450         .rev_offs       = 0x0000,
1451         .sysc_offs      = 0x0010,
1452         .syss_offs      = 0x0014,
1453         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1454                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1455                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1456         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1457         .sysc_fields    = &omap_hwmod_sysc_type1,
1458 };
1459
1460 static struct omap_hwmod_class omap34xx_mcspi_class = {
1461         .name = "mcspi",
1462         .sysc = &omap34xx_mcspi_sysc,
1463         .rev = OMAP3_MCSPI_REV,
1464 };
1465
1466 /* mcspi1 */
1467 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
1468         .num_chipselect = 4,
1469 };
1470
1471 static struct omap_hwmod omap34xx_mcspi1 = {
1472         .name           = "mcspi1",
1473         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
1474         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
1475         .main_clk       = "mcspi1_fck",
1476         .prcm           = {
1477                 .omap2 = {
1478                         .module_offs = CORE_MOD,
1479                         .prcm_reg_id = 1,
1480                         .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
1481                         .idlest_reg_id = 1,
1482                         .idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
1483                 },
1484         },
1485         .class          = &omap34xx_mcspi_class,
1486         .dev_attr       = &omap_mcspi1_dev_attr,
1487 };
1488
1489 /* mcspi2 */
1490 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
1491         .num_chipselect = 2,
1492 };
1493
1494 static struct omap_hwmod omap34xx_mcspi2 = {
1495         .name           = "mcspi2",
1496         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
1497         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
1498         .main_clk       = "mcspi2_fck",
1499         .prcm           = {
1500                 .omap2 = {
1501                         .module_offs = CORE_MOD,
1502                         .prcm_reg_id = 1,
1503                         .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
1504                         .idlest_reg_id = 1,
1505                         .idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
1506                 },
1507         },
1508         .class          = &omap34xx_mcspi_class,
1509         .dev_attr       = &omap_mcspi2_dev_attr,
1510 };
1511
1512 /* mcspi3 */
1513 static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
1514         { .name = "irq", .irq = 91 }, /* 91 */
1515         { .irq = -1 }
1516 };
1517
1518 static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
1519         { .name = "tx0", .dma_req = 15 },
1520         { .name = "rx0", .dma_req = 16 },
1521         { .name = "tx1", .dma_req = 23 },
1522         { .name = "rx1", .dma_req = 24 },
1523         { .dma_req = -1 }
1524 };
1525
1526 static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
1527         .num_chipselect = 2,
1528 };
1529
1530 static struct omap_hwmod omap34xx_mcspi3 = {
1531         .name           = "mcspi3",
1532         .mpu_irqs       = omap34xx_mcspi3_mpu_irqs,
1533         .sdma_reqs      = omap34xx_mcspi3_sdma_reqs,
1534         .main_clk       = "mcspi3_fck",
1535         .prcm           = {
1536                 .omap2 = {
1537                         .module_offs = CORE_MOD,
1538                         .prcm_reg_id = 1,
1539                         .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
1540                         .idlest_reg_id = 1,
1541                         .idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
1542                 },
1543         },
1544         .class          = &omap34xx_mcspi_class,
1545         .dev_attr       = &omap_mcspi3_dev_attr,
1546 };
1547
1548 /* mcspi4 */
1549 static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
1550         { .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
1551         { .irq = -1 }
1552 };
1553
1554 static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
1555         { .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
1556         { .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
1557         { .dma_req = -1 }
1558 };
1559
1560 static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
1561         .num_chipselect = 1,
1562 };
1563
1564 static struct omap_hwmod omap34xx_mcspi4 = {
1565         .name           = "mcspi4",
1566         .mpu_irqs       = omap34xx_mcspi4_mpu_irqs,
1567         .sdma_reqs      = omap34xx_mcspi4_sdma_reqs,
1568         .main_clk       = "mcspi4_fck",
1569         .prcm           = {
1570                 .omap2 = {
1571                         .module_offs = CORE_MOD,
1572                         .prcm_reg_id = 1,
1573                         .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
1574                         .idlest_reg_id = 1,
1575                         .idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
1576                 },
1577         },
1578         .class          = &omap34xx_mcspi_class,
1579         .dev_attr       = &omap_mcspi4_dev_attr,
1580 };
1581
1582 /* usbhsotg */
1583 static struct omap_hwmod_class_sysconfig omap3xxx_usbhsotg_sysc = {
1584         .rev_offs       = 0x0400,
1585         .sysc_offs      = 0x0404,
1586         .syss_offs      = 0x0408,
1587         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
1588                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1589                           SYSC_HAS_AUTOIDLE),
1590         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1591                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1592         .sysc_fields    = &omap_hwmod_sysc_type1,
1593 };
1594
1595 static struct omap_hwmod_class usbotg_class = {
1596         .name = "usbotg",
1597         .sysc = &omap3xxx_usbhsotg_sysc,
1598 };
1599
1600 /* usb_otg_hs */
1601 static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
1602
1603         { .name = "mc", .irq = 92 },
1604         { .name = "dma", .irq = 93 },
1605         { .irq = -1 }
1606 };
1607
1608 static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
1609         .name           = "usb_otg_hs",
1610         .mpu_irqs       = omap3xxx_usbhsotg_mpu_irqs,
1611         .main_clk       = "hsotgusb_ick",
1612         .prcm           = {
1613                 .omap2 = {
1614                         .prcm_reg_id = 1,
1615                         .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
1616                         .module_offs = CORE_MOD,
1617                         .idlest_reg_id = 1,
1618                         .idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
1619                         .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT
1620                 },
1621         },
1622         .class          = &usbotg_class,
1623
1624         /*
1625          * Erratum ID: i479  idle_req / idle_ack mechanism potentially
1626          * broken when autoidle is enabled
1627          * workaround is to disable the autoidle bit at module level.
1628          */
1629         .flags          = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
1630                                 | HWMOD_SWSUP_MSTANDBY,
1631 };
1632
1633 /* usb_otg_hs */
1634 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
1635
1636         { .name = "mc", .irq = 71 },
1637         { .irq = -1 }
1638 };
1639
1640 static struct omap_hwmod_class am35xx_usbotg_class = {
1641         .name = "am35xx_usbotg",
1642         .sysc = NULL,
1643 };
1644
1645 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
1646         .name           = "am35x_otg_hs",
1647         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
1648         .main_clk       = NULL,
1649         .prcm = {
1650                 .omap2 = {
1651                 },
1652         },
1653         .class          = &am35xx_usbotg_class,
1654 };
1655
1656 /* MMC/SD/SDIO common */
1657 static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
1658         .rev_offs       = 0x1fc,
1659         .sysc_offs      = 0x10,
1660         .syss_offs      = 0x14,
1661         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1662                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1663                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1664         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1665         .sysc_fields    = &omap_hwmod_sysc_type1,
1666 };
1667
1668 static struct omap_hwmod_class omap34xx_mmc_class = {
1669         .name = "mmc",
1670         .sysc = &omap34xx_mmc_sysc,
1671 };
1672
1673 /* MMC/SD/SDIO1 */
1674
1675 static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
1676         { .irq = 83, },
1677         { .irq = -1 }
1678 };
1679
1680 static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
1681         { .name = "tx", .dma_req = 61, },
1682         { .name = "rx", .dma_req = 62, },
1683         { .dma_req = -1 }
1684 };
1685
1686 static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
1687         { .role = "dbck", .clk = "omap_32k_fck", },
1688 };
1689
1690 static struct omap_mmc_dev_attr mmc1_dev_attr = {
1691         .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1692 };
1693
1694 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1695 static struct omap_mmc_dev_attr mmc1_pre_es3_dev_attr = {
1696         .flags = (OMAP_HSMMC_SUPPORTS_DUAL_VOLT |
1697                   OMAP_HSMMC_BROKEN_MULTIBLOCK_READ),
1698 };
1699
1700 static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
1701         .name           = "mmc1",
1702         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1703         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1704         .opt_clks       = omap34xx_mmc1_opt_clks,
1705         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1706         .main_clk       = "mmchs1_fck",
1707         .prcm           = {
1708                 .omap2 = {
1709                         .module_offs = CORE_MOD,
1710                         .prcm_reg_id = 1,
1711                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1712                         .idlest_reg_id = 1,
1713                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1714                 },
1715         },
1716         .dev_attr       = &mmc1_pre_es3_dev_attr,
1717         .class          = &omap34xx_mmc_class,
1718 };
1719
1720 static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
1721         .name           = "mmc1",
1722         .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
1723         .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
1724         .opt_clks       = omap34xx_mmc1_opt_clks,
1725         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
1726         .main_clk       = "mmchs1_fck",
1727         .prcm           = {
1728                 .omap2 = {
1729                         .module_offs = CORE_MOD,
1730                         .prcm_reg_id = 1,
1731                         .module_bit = OMAP3430_EN_MMC1_SHIFT,
1732                         .idlest_reg_id = 1,
1733                         .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
1734                 },
1735         },
1736         .dev_attr       = &mmc1_dev_attr,
1737         .class          = &omap34xx_mmc_class,
1738 };
1739
1740 /* MMC/SD/SDIO2 */
1741
1742 static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
1743         { .irq = INT_24XX_MMC2_IRQ, },
1744         { .irq = -1 }
1745 };
1746
1747 static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
1748         { .name = "tx", .dma_req = 47, },
1749         { .name = "rx", .dma_req = 48, },
1750         { .dma_req = -1 }
1751 };
1752
1753 static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
1754         { .role = "dbck", .clk = "omap_32k_fck", },
1755 };
1756
1757 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1758 static struct omap_mmc_dev_attr mmc2_pre_es3_dev_attr = {
1759         .flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1760 };
1761
1762 static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
1763         .name           = "mmc2",
1764         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1765         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1766         .opt_clks       = omap34xx_mmc2_opt_clks,
1767         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1768         .main_clk       = "mmchs2_fck",
1769         .prcm           = {
1770                 .omap2 = {
1771                         .module_offs = CORE_MOD,
1772                         .prcm_reg_id = 1,
1773                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1774                         .idlest_reg_id = 1,
1775                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1776                 },
1777         },
1778         .dev_attr       = &mmc2_pre_es3_dev_attr,
1779         .class          = &omap34xx_mmc_class,
1780 };
1781
1782 static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
1783         .name           = "mmc2",
1784         .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
1785         .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
1786         .opt_clks       = omap34xx_mmc2_opt_clks,
1787         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
1788         .main_clk       = "mmchs2_fck",
1789         .prcm           = {
1790                 .omap2 = {
1791                         .module_offs = CORE_MOD,
1792                         .prcm_reg_id = 1,
1793                         .module_bit = OMAP3430_EN_MMC2_SHIFT,
1794                         .idlest_reg_id = 1,
1795                         .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
1796                 },
1797         },
1798         .class          = &omap34xx_mmc_class,
1799 };
1800
1801 /* MMC/SD/SDIO3 */
1802
1803 static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
1804         { .irq = 94, },
1805         { .irq = -1 }
1806 };
1807
1808 static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
1809         { .name = "tx", .dma_req = 77, },
1810         { .name = "rx", .dma_req = 78, },
1811         { .dma_req = -1 }
1812 };
1813
1814 static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
1815         { .role = "dbck", .clk = "omap_32k_fck", },
1816 };
1817
1818 static struct omap_hwmod omap3xxx_mmc3_hwmod = {
1819         .name           = "mmc3",
1820         .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
1821         .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
1822         .opt_clks       = omap34xx_mmc3_opt_clks,
1823         .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
1824         .main_clk       = "mmchs3_fck",
1825         .prcm           = {
1826                 .omap2 = {
1827                         .prcm_reg_id = 1,
1828                         .module_bit = OMAP3430_EN_MMC3_SHIFT,
1829                         .idlest_reg_id = 1,
1830                         .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
1831                 },
1832         },
1833         .class          = &omap34xx_mmc_class,
1834 };
1835
1836 /*
1837  * 'usb_host_hs' class
1838  * high-speed multi-port usb host controller
1839  */
1840
1841 static struct omap_hwmod_class_sysconfig omap3xxx_usb_host_hs_sysc = {
1842         .rev_offs       = 0x0000,
1843         .sysc_offs      = 0x0010,
1844         .syss_offs      = 0x0014,
1845         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
1846                            SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1847                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1848         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1849                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1850         .sysc_fields    = &omap_hwmod_sysc_type1,
1851 };
1852
1853 static struct omap_hwmod_class omap3xxx_usb_host_hs_hwmod_class = {
1854         .name = "usb_host_hs",
1855         .sysc = &omap3xxx_usb_host_hs_sysc,
1856 };
1857
1858 static struct omap_hwmod_opt_clk omap3xxx_usb_host_hs_opt_clks[] = {
1859           { .role = "ehci_logic_fck", .clk = "usbhost_120m_fck", },
1860 };
1861
1862 static struct omap_hwmod_irq_info omap3xxx_usb_host_hs_irqs[] = {
1863         { .name = "ohci-irq", .irq = 76 },
1864         { .name = "ehci-irq", .irq = 77 },
1865         { .irq = -1 }
1866 };
1867
1868 static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
1869         .name           = "usb_host_hs",
1870         .class          = &omap3xxx_usb_host_hs_hwmod_class,
1871         .clkdm_name     = "l3_init_clkdm",
1872         .mpu_irqs       = omap3xxx_usb_host_hs_irqs,
1873         .main_clk       = "usbhost_48m_fck",
1874         .prcm = {
1875                 .omap2 = {
1876                         .module_offs = OMAP3430ES2_USBHOST_MOD,
1877                         .prcm_reg_id = 1,
1878                         .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
1879                         .idlest_reg_id = 1,
1880                         .idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
1881                         .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
1882                 },
1883         },
1884         .opt_clks       = omap3xxx_usb_host_hs_opt_clks,
1885         .opt_clks_cnt   = ARRAY_SIZE(omap3xxx_usb_host_hs_opt_clks),
1886
1887         /*
1888          * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1889          * id: i660
1890          *
1891          * Description:
1892          * In the following configuration :
1893          * - USBHOST module is set to smart-idle mode
1894          * - PRCM asserts idle_req to the USBHOST module ( This typically
1895          *   happens when the system is going to a low power mode : all ports
1896          *   have been suspended, the master part of the USBHOST module has
1897          *   entered the standby state, and SW has cut the functional clocks)
1898          * - an USBHOST interrupt occurs before the module is able to answer
1899          *   idle_ack, typically a remote wakeup IRQ.
1900          * Then the USB HOST module will enter a deadlock situation where it
1901          * is no more accessible nor functional.
1902          *
1903          * Workaround:
1904          * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1905          */
1906
1907         /*
1908          * Errata: USB host EHCI may stall when entering smart-standby mode
1909          * Id: i571
1910          *
1911          * Description:
1912          * When the USBHOST module is set to smart-standby mode, and when it is
1913          * ready to enter the standby state (i.e. all ports are suspended and
1914          * all attached devices are in suspend mode), then it can wrongly assert
1915          * the Mstandby signal too early while there are still some residual OCP
1916          * transactions ongoing. If this condition occurs, the internal state
1917          * machine may go to an undefined state and the USB link may be stuck
1918          * upon the next resume.
1919          *
1920          * Workaround:
1921          * Don't use smart standby; use only force standby,
1922          * hence HWMOD_SWSUP_MSTANDBY
1923          */
1924
1925         /*
1926          * During system boot; If the hwmod framework resets the module
1927          * the module will have smart idle settings; which can lead to deadlock
1928          * (above Errata Id:i660); so, dont reset the module during boot;
1929          * Use HWMOD_INIT_NO_RESET.
1930          */
1931
1932         .flags          = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1933                           HWMOD_INIT_NO_RESET,
1934 };
1935
1936 /*
1937  * 'usb_tll_hs' class
1938  * usb_tll_hs module is the adapter on the usb_host_hs ports
1939  */
1940 static struct omap_hwmod_class_sysconfig omap3xxx_usb_tll_hs_sysc = {
1941         .rev_offs       = 0x0000,
1942         .sysc_offs      = 0x0010,
1943         .syss_offs      = 0x0014,
1944         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1945                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1946                            SYSC_HAS_AUTOIDLE),
1947         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1948         .sysc_fields    = &omap_hwmod_sysc_type1,
1949 };
1950
1951 static struct omap_hwmod_class omap3xxx_usb_tll_hs_hwmod_class = {
1952         .name = "usb_tll_hs",
1953         .sysc = &omap3xxx_usb_tll_hs_sysc,
1954 };
1955
1956 static struct omap_hwmod_irq_info omap3xxx_usb_tll_hs_irqs[] = {
1957         { .name = "tll-irq", .irq = 78 },
1958         { .irq = -1 }
1959 };
1960
1961 static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
1962         .name           = "usb_tll_hs",
1963         .class          = &omap3xxx_usb_tll_hs_hwmod_class,
1964         .clkdm_name     = "l3_init_clkdm",
1965         .mpu_irqs       = omap3xxx_usb_tll_hs_irqs,
1966         .main_clk       = "usbtll_fck",
1967         .prcm = {
1968                 .omap2 = {
1969                         .module_offs = CORE_MOD,
1970                         .prcm_reg_id = 3,
1971                         .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
1972                         .idlest_reg_id = 3,
1973                         .idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
1974                 },
1975         },
1976 };
1977
1978 static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
1979         .name           = "hdq1w",
1980         .mpu_irqs       = omap2_hdq1w_mpu_irqs,
1981         .main_clk       = "hdq_fck",
1982         .prcm           = {
1983                 .omap2 = {
1984                         .module_offs = CORE_MOD,
1985                         .prcm_reg_id = 1,
1986                         .module_bit = OMAP3430_EN_HDQ_SHIFT,
1987                         .idlest_reg_id = 1,
1988                         .idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
1989                 },
1990         },
1991         .class          = &omap2_hdq1w_class,
1992 };
1993
1994 /*
1995  * '32K sync counter' class
1996  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
1997  */
1998 static struct omap_hwmod_class_sysconfig omap3xxx_counter_sysc = {
1999         .rev_offs       = 0x0000,
2000         .sysc_offs      = 0x0004,
2001         .sysc_flags     = SYSC_HAS_SIDLEMODE,
2002         .idlemodes      = (SIDLE_FORCE | SIDLE_NO),
2003         .sysc_fields    = &omap_hwmod_sysc_type1,
2004 };
2005
2006 static struct omap_hwmod_class omap3xxx_counter_hwmod_class = {
2007         .name   = "counter",
2008         .sysc   = &omap3xxx_counter_sysc,
2009 };
2010
2011 static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
2012         .name           = "counter_32k",
2013         .class          = &omap3xxx_counter_hwmod_class,
2014         .clkdm_name     = "wkup_clkdm",
2015         .flags          = HWMOD_SWSUP_SIDLE,
2016         .main_clk       = "wkup_32k_fck",
2017         .prcm           = {
2018                 .omap2  = {
2019                         .module_offs = WKUP_MOD,
2020                         .prcm_reg_id = 1,
2021                         .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
2022                         .idlest_reg_id = 1,
2023                         .idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
2024                 },
2025         },
2026 };
2027
2028 /*
2029  * interfaces
2030  */
2031
2032 /* L3 -> L4_CORE interface */
2033 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
2034         .master = &omap3xxx_l3_main_hwmod,
2035         .slave  = &omap3xxx_l4_core_hwmod,
2036         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2037 };
2038
2039 /* L3 -> L4_PER interface */
2040 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
2041         .master = &omap3xxx_l3_main_hwmod,
2042         .slave  = &omap3xxx_l4_per_hwmod,
2043         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2044 };
2045
2046 static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
2047         {
2048                 .pa_start       = 0x68000000,
2049                 .pa_end         = 0x6800ffff,
2050                 .flags          = ADDR_TYPE_RT,
2051         },
2052         { }
2053 };
2054
2055 /* MPU -> L3 interface */
2056 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
2057         .master   = &omap3xxx_mpu_hwmod,
2058         .slave    = &omap3xxx_l3_main_hwmod,
2059         .addr     = omap3xxx_l3_main_addrs,
2060         .user   = OCP_USER_MPU,
2061 };
2062
2063 /* DSS -> l3 */
2064 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
2065         .master         = &omap3430es1_dss_core_hwmod,
2066         .slave          = &omap3xxx_l3_main_hwmod,
2067         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2068 };
2069
2070 static struct omap_hwmod_ocp_if omap3xxx_dss__l3 = {
2071         .master         = &omap3xxx_dss_core_hwmod,
2072         .slave          = &omap3xxx_l3_main_hwmod,
2073         .fw = {
2074                 .omap2 = {
2075                         .l3_perm_bit  = OMAP3_L3_CORE_FW_INIT_ID_DSS,
2076                         .flags  = OMAP_FIREWALL_L3,
2077                 }
2078         },
2079         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2080 };
2081
2082 /* l3_core -> usbhsotg interface */
2083 static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
2084         .master         = &omap3xxx_usbhsotg_hwmod,
2085         .slave          = &omap3xxx_l3_main_hwmod,
2086         .clk            = "core_l3_ick",
2087         .user           = OCP_USER_MPU,
2088 };
2089
2090 /* l3_core -> am35xx_usbhsotg interface */
2091 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
2092         .master         = &am35xx_usbhsotg_hwmod,
2093         .slave          = &omap3xxx_l3_main_hwmod,
2094         .clk            = "core_l3_ick",
2095         .user           = OCP_USER_MPU,
2096 };
2097 /* L4_CORE -> L4_WKUP interface */
2098 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
2099         .master = &omap3xxx_l4_core_hwmod,
2100         .slave  = &omap3xxx_l4_wkup_hwmod,
2101         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2102 };
2103
2104 /* L4 CORE -> MMC1 interface */
2105 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc1 = {
2106         .master         = &omap3xxx_l4_core_hwmod,
2107         .slave          = &omap3xxx_pre_es3_mmc1_hwmod,
2108         .clk            = "mmchs1_ick",
2109         .addr           = omap2430_mmc1_addr_space,
2110         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2111         .flags          = OMAP_FIREWALL_L4
2112 };
2113
2114 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc1 = {
2115         .master         = &omap3xxx_l4_core_hwmod,
2116         .slave          = &omap3xxx_es3plus_mmc1_hwmod,
2117         .clk            = "mmchs1_ick",
2118         .addr           = omap2430_mmc1_addr_space,
2119         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2120         .flags          = OMAP_FIREWALL_L4
2121 };
2122
2123 /* L4 CORE -> MMC2 interface */
2124 static struct omap_hwmod_ocp_if omap3xxx_l4_core__pre_es3_mmc2 = {
2125         .master         = &omap3xxx_l4_core_hwmod,
2126         .slave          = &omap3xxx_pre_es3_mmc2_hwmod,
2127         .clk            = "mmchs2_ick",
2128         .addr           = omap2430_mmc2_addr_space,
2129         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2130         .flags          = OMAP_FIREWALL_L4
2131 };
2132
2133 static struct omap_hwmod_ocp_if omap3xxx_l4_core__es3plus_mmc2 = {
2134         .master         = &omap3xxx_l4_core_hwmod,
2135         .slave          = &omap3xxx_es3plus_mmc2_hwmod,
2136         .clk            = "mmchs2_ick",
2137         .addr           = omap2430_mmc2_addr_space,
2138         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2139         .flags          = OMAP_FIREWALL_L4
2140 };
2141
2142 /* L4 CORE -> MMC3 interface */
2143 static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
2144         {
2145                 .pa_start       = 0x480ad000,
2146                 .pa_end         = 0x480ad1ff,
2147                 .flags          = ADDR_TYPE_RT,
2148         },
2149         { }
2150 };
2151
2152 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
2153         .master         = &omap3xxx_l4_core_hwmod,
2154         .slave          = &omap3xxx_mmc3_hwmod,
2155         .clk            = "mmchs3_ick",
2156         .addr           = omap3xxx_mmc3_addr_space,
2157         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2158         .flags          = OMAP_FIREWALL_L4
2159 };
2160
2161 /* L4 CORE -> UART1 interface */
2162 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
2163         {
2164                 .pa_start       = OMAP3_UART1_BASE,
2165                 .pa_end         = OMAP3_UART1_BASE + SZ_8K - 1,
2166                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2167         },
2168         { }
2169 };
2170
2171 static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
2172         .master         = &omap3xxx_l4_core_hwmod,
2173         .slave          = &omap3xxx_uart1_hwmod,
2174         .clk            = "uart1_ick",
2175         .addr           = omap3xxx_uart1_addr_space,
2176         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2177 };
2178
2179 /* L4 CORE -> UART2 interface */
2180 static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
2181         {
2182                 .pa_start       = OMAP3_UART2_BASE,
2183                 .pa_end         = OMAP3_UART2_BASE + SZ_1K - 1,
2184                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2185         },
2186         { }
2187 };
2188
2189 static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
2190         .master         = &omap3xxx_l4_core_hwmod,
2191         .slave          = &omap3xxx_uart2_hwmod,
2192         .clk            = "uart2_ick",
2193         .addr           = omap3xxx_uart2_addr_space,
2194         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2195 };
2196
2197 /* L4 PER -> UART3 interface */
2198 static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
2199         {
2200                 .pa_start       = OMAP3_UART3_BASE,
2201                 .pa_end         = OMAP3_UART3_BASE + SZ_1K - 1,
2202                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2203         },
2204         { }
2205 };
2206
2207 static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
2208         .master         = &omap3xxx_l4_per_hwmod,
2209         .slave          = &omap3xxx_uart3_hwmod,
2210         .clk            = "uart3_ick",
2211         .addr           = omap3xxx_uart3_addr_space,
2212         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2213 };
2214
2215 /* L4 PER -> UART4 interface */
2216 static struct omap_hwmod_addr_space omap36xx_uart4_addr_space[] = {
2217         {
2218                 .pa_start       = OMAP3_UART4_BASE,
2219                 .pa_end         = OMAP3_UART4_BASE + SZ_1K - 1,
2220                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2221         },
2222         { }
2223 };
2224
2225 static struct omap_hwmod_ocp_if omap36xx_l4_per__uart4 = {
2226         .master         = &omap3xxx_l4_per_hwmod,
2227         .slave          = &omap36xx_uart4_hwmod,
2228         .clk            = "uart4_ick",
2229         .addr           = omap36xx_uart4_addr_space,
2230         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2231 };
2232
2233 /* AM35xx: L4 CORE -> UART4 interface */
2234 static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
2235         {
2236                 .pa_start       = OMAP3_UART4_AM35XX_BASE,
2237                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
2238                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
2239         },
2240 };
2241
2242 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
2243         .master         = &omap3xxx_l4_core_hwmod,
2244         .slave          = &am35xx_uart4_hwmod,
2245         .clk            = "uart4_ick",
2246         .addr           = am35xx_uart4_addr_space,
2247         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2248 };
2249
2250 /* L4 CORE -> I2C1 interface */
2251 static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
2252         .master         = &omap3xxx_l4_core_hwmod,
2253         .slave          = &omap3xxx_i2c1_hwmod,
2254         .clk            = "i2c1_ick",
2255         .addr           = omap2_i2c1_addr_space,
2256         .fw = {
2257                 .omap2 = {
2258                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C1_REGION,
2259                         .l4_prot_group = 7,
2260                         .flags  = OMAP_FIREWALL_L4,
2261                 }
2262         },
2263         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2264 };
2265
2266 /* L4 CORE -> I2C2 interface */
2267 static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
2268         .master         = &omap3xxx_l4_core_hwmod,
2269         .slave          = &omap3xxx_i2c2_hwmod,
2270         .clk            = "i2c2_ick",
2271         .addr           = omap2_i2c2_addr_space,
2272         .fw = {
2273                 .omap2 = {
2274                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C2_REGION,
2275                         .l4_prot_group = 7,
2276                         .flags = OMAP_FIREWALL_L4,
2277                 }
2278         },
2279         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2280 };
2281
2282 /* L4 CORE -> I2C3 interface */
2283 static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
2284         {
2285                 .pa_start       = 0x48060000,
2286                 .pa_end         = 0x48060000 + SZ_128 - 1,
2287                 .flags          = ADDR_TYPE_RT,
2288         },
2289         { }
2290 };
2291
2292 static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
2293         .master         = &omap3xxx_l4_core_hwmod,
2294         .slave          = &omap3xxx_i2c3_hwmod,
2295         .clk            = "i2c3_ick",
2296         .addr           = omap3xxx_i2c3_addr_space,
2297         .fw = {
2298                 .omap2 = {
2299                         .l4_fw_region  = OMAP3_L4_CORE_FW_I2C3_REGION,
2300                         .l4_prot_group = 7,
2301                         .flags = OMAP_FIREWALL_L4,
2302                 }
2303         },
2304         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2305 };
2306
2307 /* L4 CORE -> SR1 interface */
2308 static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
2309         {
2310                 .pa_start       = OMAP34XX_SR1_BASE,
2311                 .pa_end         = OMAP34XX_SR1_BASE + SZ_1K - 1,
2312                 .flags          = ADDR_TYPE_RT,
2313         },
2314         { }
2315 };
2316
2317 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr1 = {
2318         .master         = &omap3xxx_l4_core_hwmod,
2319         .slave          = &omap34xx_sr1_hwmod,
2320         .clk            = "sr_l4_ick",
2321         .addr           = omap3_sr1_addr_space,
2322         .user           = OCP_USER_MPU,
2323 };
2324
2325 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr1 = {
2326         .master         = &omap3xxx_l4_core_hwmod,
2327         .slave          = &omap36xx_sr1_hwmod,
2328         .clk            = "sr_l4_ick",
2329         .addr           = omap3_sr1_addr_space,
2330         .user           = OCP_USER_MPU,
2331 };
2332
2333 /* L4 CORE -> SR1 interface */
2334 static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
2335         {
2336                 .pa_start       = OMAP34XX_SR2_BASE,
2337                 .pa_end         = OMAP34XX_SR2_BASE + SZ_1K - 1,
2338                 .flags          = ADDR_TYPE_RT,
2339         },
2340         { }
2341 };
2342
2343 static struct omap_hwmod_ocp_if omap34xx_l4_core__sr2 = {
2344         .master         = &omap3xxx_l4_core_hwmod,
2345         .slave          = &omap34xx_sr2_hwmod,
2346         .clk            = "sr_l4_ick",
2347         .addr           = omap3_sr2_addr_space,
2348         .user           = OCP_USER_MPU,
2349 };
2350
2351 static struct omap_hwmod_ocp_if omap36xx_l4_core__sr2 = {
2352         .master         = &omap3xxx_l4_core_hwmod,
2353         .slave          = &omap36xx_sr2_hwmod,
2354         .clk            = "sr_l4_ick",
2355         .addr           = omap3_sr2_addr_space,
2356         .user           = OCP_USER_MPU,
2357 };
2358
2359 static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
2360         {
2361                 .pa_start       = OMAP34XX_HSUSB_OTG_BASE,
2362                 .pa_end         = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
2363                 .flags          = ADDR_TYPE_RT
2364         },
2365         { }
2366 };
2367
2368 /* l4_core -> usbhsotg  */
2369 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
2370         .master         = &omap3xxx_l4_core_hwmod,
2371         .slave          = &omap3xxx_usbhsotg_hwmod,
2372         .clk            = "l4_ick",
2373         .addr           = omap3xxx_usbhsotg_addrs,
2374         .user           = OCP_USER_MPU,
2375 };
2376
2377 static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
2378         {
2379                 .pa_start       = AM35XX_IPSS_USBOTGSS_BASE,
2380                 .pa_end         = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
2381                 .flags          = ADDR_TYPE_RT
2382         },
2383         { }
2384 };
2385
2386 /* l4_core -> usbhsotg  */
2387 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
2388         .master         = &omap3xxx_l4_core_hwmod,
2389         .slave          = &am35xx_usbhsotg_hwmod,
2390         .clk            = "l4_ick",
2391         .addr           = am35xx_usbhsotg_addrs,
2392         .user           = OCP_USER_MPU,
2393 };
2394
2395 /* L4_WKUP -> L4_SEC interface */
2396 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__l4_sec = {
2397         .master = &omap3xxx_l4_wkup_hwmod,
2398         .slave  = &omap3xxx_l4_sec_hwmod,
2399         .user   = OCP_USER_MPU | OCP_USER_SDMA,
2400 };
2401
2402 /* IVA2 <- L3 interface */
2403 static struct omap_hwmod_ocp_if omap3xxx_l3__iva = {
2404         .master         = &omap3xxx_l3_main_hwmod,
2405         .slave          = &omap3xxx_iva_hwmod,
2406         .clk            = "core_l3_ick",
2407         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2408 };
2409
2410 static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
2411         {
2412                 .pa_start       = 0x48318000,
2413                 .pa_end         = 0x48318000 + SZ_1K - 1,
2414                 .flags          = ADDR_TYPE_RT
2415         },
2416         { }
2417 };
2418
2419 /* l4_wkup -> timer1 */
2420 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
2421         .master         = &omap3xxx_l4_wkup_hwmod,
2422         .slave          = &omap3xxx_timer1_hwmod,
2423         .clk            = "gpt1_ick",
2424         .addr           = omap3xxx_timer1_addrs,
2425         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2426 };
2427
2428 static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
2429         {
2430                 .pa_start       = 0x49032000,
2431                 .pa_end         = 0x49032000 + SZ_1K - 1,
2432                 .flags          = ADDR_TYPE_RT
2433         },
2434         { }
2435 };
2436
2437 /* l4_per -> timer2 */
2438 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
2439         .master         = &omap3xxx_l4_per_hwmod,
2440         .slave          = &omap3xxx_timer2_hwmod,
2441         .clk            = "gpt2_ick",
2442         .addr           = omap3xxx_timer2_addrs,
2443         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2444 };
2445
2446 static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
2447         {
2448                 .pa_start       = 0x49034000,
2449                 .pa_end         = 0x49034000 + SZ_1K - 1,
2450                 .flags          = ADDR_TYPE_RT
2451         },
2452         { }
2453 };
2454
2455 /* l4_per -> timer3 */
2456 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
2457         .master         = &omap3xxx_l4_per_hwmod,
2458         .slave          = &omap3xxx_timer3_hwmod,
2459         .clk            = "gpt3_ick",
2460         .addr           = omap3xxx_timer3_addrs,
2461         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2462 };
2463
2464 static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
2465         {
2466                 .pa_start       = 0x49036000,
2467                 .pa_end         = 0x49036000 + SZ_1K - 1,
2468                 .flags          = ADDR_TYPE_RT
2469         },
2470         { }
2471 };
2472
2473 /* l4_per -> timer4 */
2474 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
2475         .master         = &omap3xxx_l4_per_hwmod,
2476         .slave          = &omap3xxx_timer4_hwmod,
2477         .clk            = "gpt4_ick",
2478         .addr           = omap3xxx_timer4_addrs,
2479         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2480 };
2481
2482 static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
2483         {
2484                 .pa_start       = 0x49038000,
2485                 .pa_end         = 0x49038000 + SZ_1K - 1,
2486                 .flags          = ADDR_TYPE_RT
2487         },
2488         { }
2489 };
2490
2491 /* l4_per -> timer5 */
2492 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
2493         .master         = &omap3xxx_l4_per_hwmod,
2494         .slave          = &omap3xxx_timer5_hwmod,
2495         .clk            = "gpt5_ick",
2496         .addr           = omap3xxx_timer5_addrs,
2497         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2498 };
2499
2500 static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
2501         {
2502                 .pa_start       = 0x4903A000,
2503                 .pa_end         = 0x4903A000 + SZ_1K - 1,
2504                 .flags          = ADDR_TYPE_RT
2505         },
2506         { }
2507 };
2508
2509 /* l4_per -> timer6 */
2510 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
2511         .master         = &omap3xxx_l4_per_hwmod,
2512         .slave          = &omap3xxx_timer6_hwmod,
2513         .clk            = "gpt6_ick",
2514         .addr           = omap3xxx_timer6_addrs,
2515         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2516 };
2517
2518 static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
2519         {
2520                 .pa_start       = 0x4903C000,
2521                 .pa_end         = 0x4903C000 + SZ_1K - 1,
2522                 .flags          = ADDR_TYPE_RT
2523         },
2524         { }
2525 };
2526
2527 /* l4_per -> timer7 */
2528 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
2529         .master         = &omap3xxx_l4_per_hwmod,
2530         .slave          = &omap3xxx_timer7_hwmod,
2531         .clk            = "gpt7_ick",
2532         .addr           = omap3xxx_timer7_addrs,
2533         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2534 };
2535
2536 static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
2537         {
2538                 .pa_start       = 0x4903E000,
2539                 .pa_end         = 0x4903E000 + SZ_1K - 1,
2540                 .flags          = ADDR_TYPE_RT
2541         },
2542         { }
2543 };
2544
2545 /* l4_per -> timer8 */
2546 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
2547         .master         = &omap3xxx_l4_per_hwmod,
2548         .slave          = &omap3xxx_timer8_hwmod,
2549         .clk            = "gpt8_ick",
2550         .addr           = omap3xxx_timer8_addrs,
2551         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2552 };
2553
2554 static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
2555         {
2556                 .pa_start       = 0x49040000,
2557                 .pa_end         = 0x49040000 + SZ_1K - 1,
2558                 .flags          = ADDR_TYPE_RT
2559         },
2560         { }
2561 };
2562
2563 /* l4_per -> timer9 */
2564 static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
2565         .master         = &omap3xxx_l4_per_hwmod,
2566         .slave          = &omap3xxx_timer9_hwmod,
2567         .clk            = "gpt9_ick",
2568         .addr           = omap3xxx_timer9_addrs,
2569         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2570 };
2571
2572 /* l4_core -> timer10 */
2573 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
2574         .master         = &omap3xxx_l4_core_hwmod,
2575         .slave          = &omap3xxx_timer10_hwmod,
2576         .clk            = "gpt10_ick",
2577         .addr           = omap2_timer10_addrs,
2578         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2579 };
2580
2581 /* l4_core -> timer11 */
2582 static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
2583         .master         = &omap3xxx_l4_core_hwmod,
2584         .slave          = &omap3xxx_timer11_hwmod,
2585         .clk            = "gpt11_ick",
2586         .addr           = omap2_timer11_addrs,
2587         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2588 };
2589
2590 static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
2591         {
2592                 .pa_start       = 0x48304000,
2593                 .pa_end         = 0x48304000 + SZ_1K - 1,
2594                 .flags          = ADDR_TYPE_RT
2595         },
2596         { }
2597 };
2598
2599 /* l4_core -> timer12 */
2600 static struct omap_hwmod_ocp_if omap3xxx_l4_sec__timer12 = {
2601         .master         = &omap3xxx_l4_sec_hwmod,
2602         .slave          = &omap3xxx_timer12_hwmod,
2603         .clk            = "gpt12_ick",
2604         .addr           = omap3xxx_timer12_addrs,
2605         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2606 };
2607
2608 /* l4_wkup -> wd_timer2 */
2609 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
2610         {
2611                 .pa_start       = 0x48314000,
2612                 .pa_end         = 0x4831407f,
2613                 .flags          = ADDR_TYPE_RT
2614         },
2615         { }
2616 };
2617
2618 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
2619         .master         = &omap3xxx_l4_wkup_hwmod,
2620         .slave          = &omap3xxx_wd_timer2_hwmod,
2621         .clk            = "wdt2_ick",
2622         .addr           = omap3xxx_wd_timer2_addrs,
2623         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2624 };
2625
2626 /* l4_core -> dss */
2627 static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
2628         .master         = &omap3xxx_l4_core_hwmod,
2629         .slave          = &omap3430es1_dss_core_hwmod,
2630         .clk            = "dss_ick",
2631         .addr           = omap2_dss_addrs,
2632         .fw = {
2633                 .omap2 = {
2634                         .l4_fw_region  = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
2635                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2636                         .flags  = OMAP_FIREWALL_L4,
2637                 }
2638         },
2639         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2640 };
2641
2642 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
2643         .master         = &omap3xxx_l4_core_hwmod,
2644         .slave          = &omap3xxx_dss_core_hwmod,
2645         .clk            = "dss_ick",
2646         .addr           = omap2_dss_addrs,
2647         .fw = {
2648                 .omap2 = {
2649                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
2650                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2651                         .flags  = OMAP_FIREWALL_L4,
2652                 }
2653         },
2654         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2655 };
2656
2657 /* l4_core -> dss_dispc */
2658 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
2659         .master         = &omap3xxx_l4_core_hwmod,
2660         .slave          = &omap3xxx_dss_dispc_hwmod,
2661         .clk            = "dss_ick",
2662         .addr           = omap2_dss_dispc_addrs,
2663         .fw = {
2664                 .omap2 = {
2665                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
2666                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2667                         .flags  = OMAP_FIREWALL_L4,
2668                 }
2669         },
2670         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2671 };
2672
2673 static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
2674         {
2675                 .pa_start       = 0x4804FC00,
2676                 .pa_end         = 0x4804FFFF,
2677                 .flags          = ADDR_TYPE_RT
2678         },
2679         { }
2680 };
2681
2682 /* l4_core -> dss_dsi1 */
2683 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
2684         .master         = &omap3xxx_l4_core_hwmod,
2685         .slave          = &omap3xxx_dss_dsi1_hwmod,
2686         .clk            = "dss_ick",
2687         .addr           = omap3xxx_dss_dsi1_addrs,
2688         .fw = {
2689                 .omap2 = {
2690                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
2691                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2692                         .flags  = OMAP_FIREWALL_L4,
2693                 }
2694         },
2695         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2696 };
2697
2698 /* l4_core -> dss_rfbi */
2699 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
2700         .master         = &omap3xxx_l4_core_hwmod,
2701         .slave          = &omap3xxx_dss_rfbi_hwmod,
2702         .clk            = "dss_ick",
2703         .addr           = omap2_dss_rfbi_addrs,
2704         .fw = {
2705                 .omap2 = {
2706                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
2707                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP ,
2708                         .flags  = OMAP_FIREWALL_L4,
2709                 }
2710         },
2711         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2712 };
2713
2714 /* l4_core -> dss_venc */
2715 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
2716         .master         = &omap3xxx_l4_core_hwmod,
2717         .slave          = &omap3xxx_dss_venc_hwmod,
2718         .clk            = "dss_ick",
2719         .addr           = omap2_dss_venc_addrs,
2720         .fw = {
2721                 .omap2 = {
2722                         .l4_fw_region  = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
2723                         .l4_prot_group = OMAP3_L4_CORE_FW_DSS_PROT_GROUP,
2724                         .flags  = OMAP_FIREWALL_L4,
2725                 }
2726         },
2727         .flags          = OCPIF_SWSUP_IDLE,
2728         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2729 };
2730
2731 /* l4_wkup -> gpio1 */
2732 static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
2733         {
2734                 .pa_start       = 0x48310000,
2735                 .pa_end         = 0x483101ff,
2736                 .flags          = ADDR_TYPE_RT
2737         },
2738         { }
2739 };
2740
2741 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
2742         .master         = &omap3xxx_l4_wkup_hwmod,
2743         .slave          = &omap3xxx_gpio1_hwmod,
2744         .addr           = omap3xxx_gpio1_addrs,
2745         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2746 };
2747
2748 /* l4_per -> gpio2 */
2749 static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
2750         {
2751                 .pa_start       = 0x49050000,
2752                 .pa_end         = 0x490501ff,
2753                 .flags          = ADDR_TYPE_RT
2754         },
2755         { }
2756 };
2757
2758 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
2759         .master         = &omap3xxx_l4_per_hwmod,
2760         .slave          = &omap3xxx_gpio2_hwmod,
2761         .addr           = omap3xxx_gpio2_addrs,
2762         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2763 };
2764
2765 /* l4_per -> gpio3 */
2766 static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
2767         {
2768                 .pa_start       = 0x49052000,
2769                 .pa_end         = 0x490521ff,
2770                 .flags          = ADDR_TYPE_RT
2771         },
2772         { }
2773 };
2774
2775 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
2776         .master         = &omap3xxx_l4_per_hwmod,
2777         .slave          = &omap3xxx_gpio3_hwmod,
2778         .addr           = omap3xxx_gpio3_addrs,
2779         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2780 };
2781
2782 /* l4_per -> gpio4 */
2783 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
2784         {
2785                 .pa_start       = 0x49054000,
2786                 .pa_end         = 0x490541ff,
2787                 .flags          = ADDR_TYPE_RT
2788         },
2789         { }
2790 };
2791
2792 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
2793         .master         = &omap3xxx_l4_per_hwmod,
2794         .slave          = &omap3xxx_gpio4_hwmod,
2795         .addr           = omap3xxx_gpio4_addrs,
2796         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2797 };
2798
2799 /* l4_per -> gpio5 */
2800 static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
2801         {
2802                 .pa_start       = 0x49056000,
2803                 .pa_end         = 0x490561ff,
2804                 .flags          = ADDR_TYPE_RT
2805         },
2806         { }
2807 };
2808
2809 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
2810         .master         = &omap3xxx_l4_per_hwmod,
2811         .slave          = &omap3xxx_gpio5_hwmod,
2812         .addr           = omap3xxx_gpio5_addrs,
2813         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2814 };
2815
2816 /* l4_per -> gpio6 */
2817 static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
2818         {
2819                 .pa_start       = 0x49058000,
2820                 .pa_end         = 0x490581ff,
2821                 .flags          = ADDR_TYPE_RT
2822         },
2823         { }
2824 };
2825
2826 static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
2827         .master         = &omap3xxx_l4_per_hwmod,
2828         .slave          = &omap3xxx_gpio6_hwmod,
2829         .addr           = omap3xxx_gpio6_addrs,
2830         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2831 };
2832
2833 /* dma_system -> L3 */
2834 static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
2835         .master         = &omap3xxx_dma_system_hwmod,
2836         .slave          = &omap3xxx_l3_main_hwmod,
2837         .clk            = "core_l3_ick",
2838         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2839 };
2840
2841 static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
2842         {
2843                 .pa_start       = 0x48056000,
2844                 .pa_end         = 0x48056fff,
2845                 .flags          = ADDR_TYPE_RT
2846         },
2847         { }
2848 };
2849
2850 /* l4_cfg -> dma_system */
2851 static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
2852         .master         = &omap3xxx_l4_core_hwmod,
2853         .slave          = &omap3xxx_dma_system_hwmod,
2854         .clk            = "core_l4_ick",
2855         .addr           = omap3xxx_dma_system_addrs,
2856         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2857 };
2858
2859 static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
2860         {
2861                 .name           = "mpu",
2862                 .pa_start       = 0x48074000,
2863                 .pa_end         = 0x480740ff,
2864                 .flags          = ADDR_TYPE_RT
2865         },
2866         { }
2867 };
2868
2869 /* l4_core -> mcbsp1 */
2870 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
2871         .master         = &omap3xxx_l4_core_hwmod,
2872         .slave          = &omap3xxx_mcbsp1_hwmod,
2873         .clk            = "mcbsp1_ick",
2874         .addr           = omap3xxx_mcbsp1_addrs,
2875         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2876 };
2877
2878 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
2879         {
2880                 .name           = "mpu",
2881                 .pa_start       = 0x49022000,
2882                 .pa_end         = 0x490220ff,
2883                 .flags          = ADDR_TYPE_RT
2884         },
2885         { }
2886 };
2887
2888 /* l4_per -> mcbsp2 */
2889 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
2890         .master         = &omap3xxx_l4_per_hwmod,
2891         .slave          = &omap3xxx_mcbsp2_hwmod,
2892         .clk            = "mcbsp2_ick",
2893         .addr           = omap3xxx_mcbsp2_addrs,
2894         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2895 };
2896
2897 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
2898         {
2899                 .name           = "mpu",
2900                 .pa_start       = 0x49024000,
2901                 .pa_end         = 0x490240ff,
2902                 .flags          = ADDR_TYPE_RT
2903         },
2904         { }
2905 };
2906
2907 /* l4_per -> mcbsp3 */
2908 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
2909         .master         = &omap3xxx_l4_per_hwmod,
2910         .slave          = &omap3xxx_mcbsp3_hwmod,
2911         .clk            = "mcbsp3_ick",
2912         .addr           = omap3xxx_mcbsp3_addrs,
2913         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2914 };
2915
2916 static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
2917         {
2918                 .name           = "mpu",
2919                 .pa_start       = 0x49026000,
2920                 .pa_end         = 0x490260ff,
2921                 .flags          = ADDR_TYPE_RT
2922         },
2923         { }
2924 };
2925
2926 /* l4_per -> mcbsp4 */
2927 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
2928         .master         = &omap3xxx_l4_per_hwmod,
2929         .slave          = &omap3xxx_mcbsp4_hwmod,
2930         .clk            = "mcbsp4_ick",
2931         .addr           = omap3xxx_mcbsp4_addrs,
2932         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2933 };
2934
2935 static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
2936         {
2937                 .name           = "mpu",
2938                 .pa_start       = 0x48096000,
2939                 .pa_end         = 0x480960ff,
2940                 .flags          = ADDR_TYPE_RT
2941         },
2942         { }
2943 };
2944
2945 /* l4_core -> mcbsp5 */
2946 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
2947         .master         = &omap3xxx_l4_core_hwmod,
2948         .slave          = &omap3xxx_mcbsp5_hwmod,
2949         .clk            = "mcbsp5_ick",
2950         .addr           = omap3xxx_mcbsp5_addrs,
2951         .user           = OCP_USER_MPU | OCP_USER_SDMA,
2952 };
2953
2954 static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
2955         {
2956                 .name           = "sidetone",
2957                 .pa_start       = 0x49028000,
2958                 .pa_end         = 0x490280ff,
2959                 .flags          = ADDR_TYPE_RT
2960         },
2961         { }
2962 };
2963
2964 /* l4_per -> mcbsp2_sidetone */
2965 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
2966         .master         = &omap3xxx_l4_per_hwmod,
2967         .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
2968         .clk            = "mcbsp2_ick",
2969         .addr           = omap3xxx_mcbsp2_sidetone_addrs,
2970         .user           = OCP_USER_MPU,
2971 };
2972
2973 static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
2974         {
2975                 .name           = "sidetone",
2976                 .pa_start       = 0x4902A000,
2977                 .pa_end         = 0x4902A0ff,
2978                 .flags          = ADDR_TYPE_RT
2979         },
2980         { }
2981 };
2982
2983 /* l4_per -> mcbsp3_sidetone */
2984 static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
2985         .master         = &omap3xxx_l4_per_hwmod,
2986         .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
2987         .clk            = "mcbsp3_ick",
2988         .addr           = omap3xxx_mcbsp3_sidetone_addrs,
2989         .user           = OCP_USER_MPU,
2990 };
2991
2992 static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
2993         {
2994                 .pa_start       = 0x48094000,
2995                 .pa_end         = 0x480941ff,
2996                 .flags          = ADDR_TYPE_RT,
2997         },
2998         { }
2999 };
3000
3001 /* l4_core -> mailbox */
3002 static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
3003         .master         = &omap3xxx_l4_core_hwmod,
3004         .slave          = &omap3xxx_mailbox_hwmod,
3005         .addr           = omap3xxx_mailbox_addrs,
3006         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3007 };
3008
3009 /* l4 core -> mcspi1 interface */
3010 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
3011         .master         = &omap3xxx_l4_core_hwmod,
3012         .slave          = &omap34xx_mcspi1,
3013         .clk            = "mcspi1_ick",
3014         .addr           = omap2_mcspi1_addr_space,
3015         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3016 };
3017
3018 /* l4 core -> mcspi2 interface */
3019 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
3020         .master         = &omap3xxx_l4_core_hwmod,
3021         .slave          = &omap34xx_mcspi2,
3022         .clk            = "mcspi2_ick",
3023         .addr           = omap2_mcspi2_addr_space,
3024         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3025 };
3026
3027 /* l4 core -> mcspi3 interface */
3028 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
3029         .master         = &omap3xxx_l4_core_hwmod,
3030         .slave          = &omap34xx_mcspi3,
3031         .clk            = "mcspi3_ick",
3032         .addr           = omap2430_mcspi3_addr_space,
3033         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3034 };
3035
3036 /* l4 core -> mcspi4 interface */
3037 static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
3038         {
3039                 .pa_start       = 0x480ba000,
3040                 .pa_end         = 0x480ba0ff,
3041                 .flags          = ADDR_TYPE_RT,
3042         },
3043         { }
3044 };
3045
3046 static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
3047         .master         = &omap3xxx_l4_core_hwmod,
3048         .slave          = &omap34xx_mcspi4,
3049         .clk            = "mcspi4_ick",
3050         .addr           = omap34xx_mcspi4_addr_space,
3051         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3052 };
3053
3054 static struct omap_hwmod_ocp_if omap3xxx_usb_host_hs__l3_main_2 = {
3055         .master         = &omap3xxx_usb_host_hs_hwmod,
3056         .slave          = &omap3xxx_l3_main_hwmod,
3057         .clk            = "core_l3_ick",
3058         .user           = OCP_USER_MPU,
3059 };
3060
3061 static struct omap_hwmod_addr_space omap3xxx_usb_host_hs_addrs[] = {
3062         {
3063                 .name           = "uhh",
3064                 .pa_start       = 0x48064000,
3065                 .pa_end         = 0x480643ff,
3066                 .flags          = ADDR_TYPE_RT
3067         },
3068         {
3069                 .name           = "ohci",
3070                 .pa_start       = 0x48064400,
3071                 .pa_end         = 0x480647ff,
3072         },
3073         {
3074                 .name           = "ehci",
3075                 .pa_start       = 0x48064800,
3076                 .pa_end         = 0x48064cff,
3077         },
3078         {}
3079 };
3080
3081 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_host_hs = {
3082         .master         = &omap3xxx_l4_core_hwmod,
3083         .slave          = &omap3xxx_usb_host_hs_hwmod,
3084         .clk            = "usbhost_ick",
3085         .addr           = omap3xxx_usb_host_hs_addrs,
3086         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3087 };
3088
3089 static struct omap_hwmod_addr_space omap3xxx_usb_tll_hs_addrs[] = {
3090         {
3091                 .name           = "tll",
3092                 .pa_start       = 0x48062000,
3093                 .pa_end         = 0x48062fff,
3094                 .flags          = ADDR_TYPE_RT
3095         },
3096         {}
3097 };
3098
3099 static struct omap_hwmod_ocp_if omap3xxx_l4_core__usb_tll_hs = {
3100         .master         = &omap3xxx_l4_core_hwmod,
3101         .slave          = &omap3xxx_usb_tll_hs_hwmod,
3102         .clk            = "usbtll_ick",
3103         .addr           = omap3xxx_usb_tll_hs_addrs,
3104         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3105 };
3106
3107 /* l4_core -> hdq1w interface */
3108 static struct omap_hwmod_ocp_if omap3xxx_l4_core__hdq1w = {
3109         .master         = &omap3xxx_l4_core_hwmod,
3110         .slave          = &omap3xxx_hdq1w_hwmod,
3111         .clk            = "hdq_ick",
3112         .addr           = omap2_hdq1w_addr_space,
3113         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3114         .flags          = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
3115 };
3116
3117 /* l4_wkup -> 32ksync_counter */
3118 static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
3119         {
3120                 .pa_start       = 0x48320000,
3121                 .pa_end         = 0x4832001f,
3122                 .flags          = ADDR_TYPE_RT
3123         },
3124         { }
3125 };
3126
3127 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
3128         .master         = &omap3xxx_l4_wkup_hwmod,
3129         .slave          = &omap3xxx_counter_32k_hwmod,
3130         .clk            = "omap_32ksync_ick",
3131         .addr           = omap3xxx_counter_32k_addrs,
3132         .user           = OCP_USER_MPU | OCP_USER_SDMA,
3133 };
3134
3135 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
3136         &omap3xxx_l3_main__l4_core,
3137         &omap3xxx_l3_main__l4_per,
3138         &omap3xxx_mpu__l3_main,
3139         &omap3xxx_l4_core__l4_wkup,
3140         &omap3xxx_l4_core__mmc3,
3141         &omap3_l4_core__uart1,
3142         &omap3_l4_core__uart2,
3143         &omap3_l4_per__uart3,
3144         &omap3_l4_core__i2c1,
3145         &omap3_l4_core__i2c2,
3146         &omap3_l4_core__i2c3,
3147         &omap3xxx_l4_wkup__l4_sec,
3148         &omap3xxx_l4_wkup__timer1,
3149         &omap3xxx_l4_per__timer2,
3150         &omap3xxx_l4_per__timer3,
3151         &omap3xxx_l4_per__timer4,
3152         &omap3xxx_l4_per__timer5,
3153         &omap3xxx_l4_per__timer6,
3154         &omap3xxx_l4_per__timer7,
3155         &omap3xxx_l4_per__timer8,
3156         &omap3xxx_l4_per__timer9,
3157         &omap3xxx_l4_core__timer10,
3158         &omap3xxx_l4_core__timer11,
3159         &omap3xxx_l4_wkup__wd_timer2,
3160         &omap3xxx_l4_wkup__gpio1,
3161         &omap3xxx_l4_per__gpio2,
3162         &omap3xxx_l4_per__gpio3,
3163         &omap3xxx_l4_per__gpio4,
3164         &omap3xxx_l4_per__gpio5,
3165         &omap3xxx_l4_per__gpio6,
3166         &omap3xxx_dma_system__l3,
3167         &omap3xxx_l4_core__dma_system,
3168         &omap3xxx_l4_core__mcbsp1,
3169         &omap3xxx_l4_per__mcbsp2,
3170         &omap3xxx_l4_per__mcbsp3,
3171         &omap3xxx_l4_per__mcbsp4,
3172         &omap3xxx_l4_core__mcbsp5,
3173         &omap3xxx_l4_per__mcbsp2_sidetone,
3174         &omap3xxx_l4_per__mcbsp3_sidetone,
3175         &omap34xx_l4_core__mcspi1,
3176         &omap34xx_l4_core__mcspi2,
3177         &omap34xx_l4_core__mcspi3,
3178         &omap34xx_l4_core__mcspi4,
3179         &omap3xxx_l4_wkup__counter_32k,
3180         NULL,
3181 };
3182
3183 /* GP-only hwmod links */
3184 static struct omap_hwmod_ocp_if *omap3xxx_gp_hwmod_ocp_ifs[] __initdata = {
3185         &omap3xxx_l4_sec__timer12,
3186         NULL
3187 };
3188
3189 /* 3430ES1-only hwmod links */
3190 static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
3191         &omap3430es1_dss__l3,
3192         &omap3430es1_l4_core__dss,
3193         NULL
3194 };
3195
3196 /* 3430ES2+-only hwmod links */
3197 static struct omap_hwmod_ocp_if *omap3430es2plus_hwmod_ocp_ifs[] __initdata = {
3198         &omap3xxx_dss__l3,
3199         &omap3xxx_l4_core__dss,
3200         &omap3xxx_usbhsotg__l3,
3201         &omap3xxx_l4_core__usbhsotg,
3202         &omap3xxx_usb_host_hs__l3_main_2,
3203         &omap3xxx_l4_core__usb_host_hs,
3204         &omap3xxx_l4_core__usb_tll_hs,
3205         NULL
3206 };
3207
3208 /* <= 3430ES3-only hwmod links */
3209 static struct omap_hwmod_ocp_if *omap3430_pre_es3_hwmod_ocp_ifs[] __initdata = {
3210         &omap3xxx_l4_core__pre_es3_mmc1,
3211         &omap3xxx_l4_core__pre_es3_mmc2,
3212         NULL
3213 };
3214
3215 /* 3430ES3+-only hwmod links */
3216 static struct omap_hwmod_ocp_if *omap3430_es3plus_hwmod_ocp_ifs[] __initdata = {
3217         &omap3xxx_l4_core__es3plus_mmc1,
3218         &omap3xxx_l4_core__es3plus_mmc2,
3219         NULL
3220 };
3221
3222 /* 34xx-only hwmod links (all ES revisions) */
3223 static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
3224         &omap3xxx_l3__iva,
3225         &omap34xx_l4_core__sr1,
3226         &omap34xx_l4_core__sr2,
3227         &omap3xxx_l4_core__mailbox,
3228         &omap3xxx_l4_core__hdq1w,
3229         NULL
3230 };
3231
3232 /* 36xx-only hwmod links (all ES revisions) */
3233 static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
3234         &omap3xxx_l3__iva,
3235         &omap36xx_l4_per__uart4,
3236         &omap3xxx_dss__l3,
3237         &omap3xxx_l4_core__dss,
3238         &omap36xx_l4_core__sr1,
3239         &omap36xx_l4_core__sr2,
3240         &omap3xxx_usbhsotg__l3,
3241         &omap3xxx_l4_core__usbhsotg,
3242         &omap3xxx_l4_core__mailbox,
3243         &omap3xxx_usb_host_hs__l3_main_2,
3244         &omap3xxx_l4_core__usb_host_hs,
3245         &omap3xxx_l4_core__usb_tll_hs,
3246         &omap3xxx_l4_core__es3plus_mmc1,
3247         &omap3xxx_l4_core__es3plus_mmc2,
3248         &omap3xxx_l4_core__hdq1w,
3249         NULL
3250 };
3251
3252 static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
3253         &omap3xxx_dss__l3,
3254         &omap3xxx_l4_core__dss,
3255         &am35xx_usbhsotg__l3,
3256         &am35xx_l4_core__usbhsotg,
3257         &am35xx_l4_core__uart4,
3258         &omap3xxx_usb_host_hs__l3_main_2,
3259         &omap3xxx_l4_core__usb_host_hs,
3260         &omap3xxx_l4_core__usb_tll_hs,
3261         &omap3xxx_l4_core__es3plus_mmc1,
3262         &omap3xxx_l4_core__es3plus_mmc2,
3263         NULL
3264 };
3265
3266 static struct omap_hwmod_ocp_if *omap3xxx_dss_hwmod_ocp_ifs[] __initdata = {
3267         &omap3xxx_l4_core__dss_dispc,
3268         &omap3xxx_l4_core__dss_dsi1,
3269         &omap3xxx_l4_core__dss_rfbi,
3270         &omap3xxx_l4_core__dss_venc,
3271         NULL
3272 };
3273
3274 int __init omap3xxx_hwmod_init(void)
3275 {
3276         int r;
3277         struct omap_hwmod_ocp_if **h = NULL;
3278         unsigned int rev;
3279
3280         /* Register hwmod links common to all OMAP3 */
3281         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
3282         if (r < 0)
3283                 return r;
3284
3285         /* Register GP-only hwmod links. */
3286         if (omap_type() == OMAP2_DEVICE_TYPE_GP) {
3287                 r = omap_hwmod_register_links(omap3xxx_gp_hwmod_ocp_ifs);
3288                 if (r < 0)
3289                         return r;
3290         }
3291
3292         rev = omap_rev();
3293
3294         /*
3295          * Register hwmod links common to individual OMAP3 families, all
3296          * silicon revisions (e.g., 34xx, or AM3505/3517, or 36xx)
3297          * All possible revisions should be included in this conditional.
3298          */
3299         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3300             rev == OMAP3430_REV_ES2_1 || rev == OMAP3430_REV_ES3_0 ||
3301             rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
3302                 h = omap34xx_hwmod_ocp_ifs;
3303         } else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
3304                 h = am35xx_hwmod_ocp_ifs;
3305         } else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
3306                    rev == OMAP3630_REV_ES1_2) {
3307                 h = omap36xx_hwmod_ocp_ifs;
3308         } else {
3309                 WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
3310                 return -EINVAL;
3311         };
3312
3313         r = omap_hwmod_register_links(h);
3314         if (r < 0)
3315                 return r;
3316
3317         /*
3318          * Register hwmod links specific to certain ES levels of a
3319          * particular family of silicon (e.g., 34xx ES1.0)
3320          */
3321         h = NULL;
3322         if (rev == OMAP3430_REV_ES1_0) {
3323                 h = omap3430es1_hwmod_ocp_ifs;
3324         } else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
3325                    rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3326                    rev == OMAP3430_REV_ES3_1_2) {
3327                 h = omap3430es2plus_hwmod_ocp_ifs;
3328         };
3329
3330         if (h) {
3331                 r = omap_hwmod_register_links(h);
3332                 if (r < 0)
3333                         return r;
3334         }
3335
3336         h = NULL;
3337         if (rev == OMAP3430_REV_ES1_0 || rev == OMAP3430_REV_ES2_0 ||
3338             rev == OMAP3430_REV_ES2_1) {
3339                 h = omap3430_pre_es3_hwmod_ocp_ifs;
3340         } else if (rev == OMAP3430_REV_ES3_0 || rev == OMAP3430_REV_ES3_1 ||
3341                    rev == OMAP3430_REV_ES3_1_2) {
3342                 h = omap3430_es3plus_hwmod_ocp_ifs;
3343         };
3344
3345         if (h)
3346                 r = omap_hwmod_register_links(h);
3347         if (r < 0)
3348                 return r;
3349
3350         /*
3351          * DSS code presumes that dss_core hwmod is handled first,
3352          * _before_ any other DSS related hwmods so register common
3353          * DSS hwmod links last to ensure that dss_core is already
3354          * registered.  Otherwise some change things may happen, for
3355          * ex. if dispc is handled before dss_core and DSS is enabled
3356          * in bootloader DISPC will be reset with outputs enabled
3357          * which sometimes leads to unrecoverable L3 error.  XXX The
3358          * long-term fix to this is to ensure hwmods are set up in
3359          * dependency order in the hwmod core code.
3360          */
3361         r = omap_hwmod_register_links(omap3xxx_dss_hwmod_ocp_ifs);
3362
3363         return r;
3364 }