2 * omap_hwmod_33xx_data.c: Hardware modules present on the AM33XX chips
4 * Copyright (C) {2012} Texas Instruments Incorporated - http://www.ti.com/
6 * This file is automatically generated from the AM33XX hardware databases.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/i2c-omap.h>
19 #include "omap_hwmod.h"
20 #include <linux/platform_data/gpio-omap.h>
21 #include <linux/platform_data/spi-omap2-mcspi.h>
23 #include "omap_hwmod_common_data.h"
28 #include "prm-regbits-33xx.h"
39 * instance(s): emif_fw
41 static struct omap_hwmod_class am33xx_emif_fw_hwmod_class = {
46 static struct omap_hwmod am33xx_emif_fw_hwmod = {
48 .class = &am33xx_emif_fw_hwmod_class,
49 .clkdm_name = "l4fw_clkdm",
50 .main_clk = "l4fw_gclk",
51 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
54 .clkctrl_offs = AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET,
55 .modulemode = MODULEMODE_SWCTRL,
64 static struct omap_hwmod_class_sysconfig am33xx_emif_sysc = {
68 static struct omap_hwmod_class am33xx_emif_hwmod_class = {
70 .sysc = &am33xx_emif_sysc,
73 static struct omap_hwmod_irq_info am33xx_emif_irqs[] = {
74 { .name = "ddrerr0", .irq = 101 + OMAP_INTC_START, },
79 static struct omap_hwmod am33xx_emif_hwmod = {
81 .class = &am33xx_emif_hwmod_class,
82 .clkdm_name = "l3_clkdm",
83 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
84 .mpu_irqs = am33xx_emif_irqs,
85 .main_clk = "dpll_ddr_m2_div2_ck",
88 .clkctrl_offs = AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET,
89 .modulemode = MODULEMODE_SWCTRL,
96 * instance(s): l3_main, l3_s, l3_instr
98 static struct omap_hwmod_class am33xx_l3_hwmod_class = {
102 /* l3_main (l3_fast) */
103 static struct omap_hwmod_irq_info am33xx_l3_main_irqs[] = {
104 { .name = "l3debug", .irq = 9 + OMAP_INTC_START, },
105 { .name = "l3appint", .irq = 10 + OMAP_INTC_START, },
109 static struct omap_hwmod am33xx_l3_main_hwmod = {
111 .class = &am33xx_l3_hwmod_class,
112 .clkdm_name = "l3_clkdm",
113 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
114 .mpu_irqs = am33xx_l3_main_irqs,
115 .main_clk = "l3_gclk",
118 .clkctrl_offs = AM33XX_CM_PER_L3_CLKCTRL_OFFSET,
119 .modulemode = MODULEMODE_SWCTRL,
125 static struct omap_hwmod am33xx_l3_s_hwmod = {
127 .class = &am33xx_l3_hwmod_class,
128 .clkdm_name = "l3s_clkdm",
132 static struct omap_hwmod am33xx_l3_instr_hwmod = {
134 .class = &am33xx_l3_hwmod_class,
135 .clkdm_name = "l3_clkdm",
136 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
137 .main_clk = "l3_gclk",
140 .clkctrl_offs = AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET,
141 .modulemode = MODULEMODE_SWCTRL,
148 * instance(s): l4_ls, l4_hs, l4_wkup, l4_fw
150 static struct omap_hwmod_class am33xx_l4_hwmod_class = {
155 static struct omap_hwmod am33xx_l4_ls_hwmod = {
157 .class = &am33xx_l4_hwmod_class,
158 .clkdm_name = "l4ls_clkdm",
159 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
160 .main_clk = "l4ls_gclk",
163 .clkctrl_offs = AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET,
164 .modulemode = MODULEMODE_SWCTRL,
170 static struct omap_hwmod am33xx_l4_hs_hwmod = {
172 .class = &am33xx_l4_hwmod_class,
173 .clkdm_name = "l4hs_clkdm",
174 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
175 .main_clk = "l4hs_gclk",
178 .clkctrl_offs = AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET,
179 .modulemode = MODULEMODE_SWCTRL,
186 static struct omap_hwmod am33xx_l4_wkup_hwmod = {
188 .class = &am33xx_l4_hwmod_class,
189 .clkdm_name = "l4_wkup_clkdm",
190 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
193 .clkctrl_offs = AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
194 .modulemode = MODULEMODE_SWCTRL,
200 static struct omap_hwmod am33xx_l4_fw_hwmod = {
202 .class = &am33xx_l4_hwmod_class,
203 .clkdm_name = "l4fw_clkdm",
204 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
207 .clkctrl_offs = AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET,
208 .modulemode = MODULEMODE_SWCTRL,
216 static struct omap_hwmod_class am33xx_mpu_hwmod_class = {
221 static struct omap_hwmod_irq_info am33xx_mpu_irqs[] = {
222 { .name = "emuint", .irq = 0 + OMAP_INTC_START, },
223 { .name = "commtx", .irq = 1 + OMAP_INTC_START, },
224 { .name = "commrx", .irq = 2 + OMAP_INTC_START, },
225 { .name = "bench", .irq = 3 + OMAP_INTC_START, },
229 static struct omap_hwmod am33xx_mpu_hwmod = {
231 .class = &am33xx_mpu_hwmod_class,
232 .clkdm_name = "mpu_clkdm",
233 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
234 .mpu_irqs = am33xx_mpu_irqs,
235 .main_clk = "dpll_mpu_m2_ck",
238 .clkctrl_offs = AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET,
239 .modulemode = MODULEMODE_SWCTRL,
246 * Wakeup controller sub-system under wakeup domain
248 static struct omap_hwmod_class am33xx_wkup_m3_hwmod_class = {
252 static struct omap_hwmod_rst_info am33xx_wkup_m3_resets[] = {
253 { .name = "wkup_m3", .rst_shift = 3, .st_shift = 5 },
256 static struct omap_hwmod_irq_info am33xx_wkup_m3_irqs[] = {
257 { .name = "txev", .irq = 78 + OMAP_INTC_START, },
262 static struct omap_hwmod am33xx_wkup_m3_hwmod = {
264 .class = &am33xx_wkup_m3_hwmod_class,
265 .clkdm_name = "l4_wkup_aon_clkdm",
266 /* Keep hardreset asserted */
267 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
268 .mpu_irqs = am33xx_wkup_m3_irqs,
269 .main_clk = "dpll_core_m4_div2_ck",
272 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
273 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
274 .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
275 .modulemode = MODULEMODE_SWCTRL,
278 .rst_lines = am33xx_wkup_m3_resets,
279 .rst_lines_cnt = ARRAY_SIZE(am33xx_wkup_m3_resets),
284 * Programmable Real-Time Unit and Industrial Communication Subsystem
286 static struct omap_hwmod_class am33xx_pruss_hwmod_class = {
290 static struct omap_hwmod_rst_info am33xx_pruss_resets[] = {
291 { .name = "pruss", .rst_shift = 1 },
294 static struct omap_hwmod_irq_info am33xx_pruss_irqs[] = {
295 { .name = "evtout0", .irq = 20 + OMAP_INTC_START, },
296 { .name = "evtout1", .irq = 21 + OMAP_INTC_START, },
297 { .name = "evtout2", .irq = 22 + OMAP_INTC_START, },
298 { .name = "evtout3", .irq = 23 + OMAP_INTC_START, },
299 { .name = "evtout4", .irq = 24 + OMAP_INTC_START, },
300 { .name = "evtout5", .irq = 25 + OMAP_INTC_START, },
301 { .name = "evtout6", .irq = 26 + OMAP_INTC_START, },
302 { .name = "evtout7", .irq = 27 + OMAP_INTC_START, },
307 /* Pseudo hwmod for reset control purpose only */
308 static struct omap_hwmod am33xx_pruss_hwmod = {
310 .class = &am33xx_pruss_hwmod_class,
311 .clkdm_name = "pruss_ocp_clkdm",
312 .mpu_irqs = am33xx_pruss_irqs,
313 .main_clk = "pruss_ocp_gclk",
316 .clkctrl_offs = AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET,
317 .rstctrl_offs = AM33XX_RM_PER_RSTCTRL_OFFSET,
318 .modulemode = MODULEMODE_SWCTRL,
321 .rst_lines = am33xx_pruss_resets,
322 .rst_lines_cnt = ARRAY_SIZE(am33xx_pruss_resets),
326 /* Pseudo hwmod for reset control purpose only */
327 static struct omap_hwmod_class am33xx_gfx_hwmod_class = {
331 static struct omap_hwmod_rst_info am33xx_gfx_resets[] = {
332 { .name = "gfx", .rst_shift = 0 },
335 static struct omap_hwmod_irq_info am33xx_gfx_irqs[] = {
336 { .name = "gfxint", .irq = 37 + OMAP_INTC_START, },
340 static struct omap_hwmod am33xx_gfx_hwmod = {
342 .class = &am33xx_gfx_hwmod_class,
343 .clkdm_name = "gfx_l3_clkdm",
344 .mpu_irqs = am33xx_gfx_irqs,
345 .main_clk = "gfx_fck_div_ck",
348 .clkctrl_offs = AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET,
349 .rstctrl_offs = AM33XX_RM_GFX_RSTCTRL_OFFSET,
350 .modulemode = MODULEMODE_SWCTRL,
353 .rst_lines = am33xx_gfx_resets,
354 .rst_lines_cnt = ARRAY_SIZE(am33xx_gfx_resets),
359 * power and reset manager (whole prcm infrastructure)
361 static struct omap_hwmod_class am33xx_prcm_hwmod_class = {
366 static struct omap_hwmod am33xx_prcm_hwmod = {
368 .class = &am33xx_prcm_hwmod_class,
369 .clkdm_name = "l4_wkup_clkdm",
374 * TouchScreen Controller (Anolog-To-Digital Converter)
376 static struct omap_hwmod_class_sysconfig am33xx_adc_tsc_sysc = {
379 .sysc_flags = SYSC_HAS_SIDLEMODE,
380 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
382 .sysc_fields = &omap_hwmod_sysc_type2,
385 static struct omap_hwmod_class am33xx_adc_tsc_hwmod_class = {
387 .sysc = &am33xx_adc_tsc_sysc,
390 static struct omap_hwmod_irq_info am33xx_adc_tsc_irqs[] = {
391 { .irq = 16 + OMAP_INTC_START, },
395 static struct omap_hwmod am33xx_adc_tsc_hwmod = {
397 .class = &am33xx_adc_tsc_hwmod_class,
398 .clkdm_name = "l4_wkup_clkdm",
399 .mpu_irqs = am33xx_adc_tsc_irqs,
400 .main_clk = "adc_tsc_fck",
403 .clkctrl_offs = AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET,
404 .modulemode = MODULEMODE_SWCTRL,
410 * Modules omap_hwmod structures
412 * The following IPs are excluded for the moment because:
413 * - They do not need an explicit SW control using omap_hwmod API.
414 * - They still need to be validated with the driver
415 * properly adapted to omap_hwmod / omap_device
417 * - cEFUSE (doesn't fall under any ocp_if)
426 static struct omap_hwmod_class am33xx_cefuse_hwmod_class = {
430 static struct omap_hwmod am33xx_cefuse_hwmod = {
432 .class = &am33xx_cefuse_hwmod_class,
433 .clkdm_name = "l4_cefuse_clkdm",
434 .main_clk = "cefuse_fck",
437 .clkctrl_offs = AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET,
438 .modulemode = MODULEMODE_SWCTRL,
446 static struct omap_hwmod_class am33xx_clkdiv32k_hwmod_class = {
450 static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
452 .class = &am33xx_clkdiv32k_hwmod_class,
453 .clkdm_name = "clk_24mhz_clkdm",
454 .main_clk = "clkdiv32k_ick",
457 .clkctrl_offs = AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET,
458 .modulemode = MODULEMODE_SWCTRL,
467 static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
471 static struct omap_hwmod am33xx_debugss_hwmod = {
473 .class = &am33xx_debugss_hwmod_class,
474 .clkdm_name = "l3_aon_clkdm",
475 .main_clk = "debugss_ick",
478 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
479 .modulemode = MODULEMODE_SWCTRL,
485 static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
489 static struct omap_hwmod am33xx_ocpwp_hwmod = {
491 .class = &am33xx_ocpwp_hwmod_class,
492 .clkdm_name = "l4ls_clkdm",
493 .main_clk = "l4ls_gclk",
496 .clkctrl_offs = AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET,
497 .modulemode = MODULEMODE_SWCTRL,
506 static struct omap_hwmod_class_sysconfig am33xx_aes0_sysc = {
510 .sysc_flags = SYSS_HAS_RESET_STATUS,
513 static struct omap_hwmod_class am33xx_aes0_hwmod_class = {
515 .sysc = &am33xx_aes0_sysc,
518 static struct omap_hwmod_irq_info am33xx_aes0_irqs[] = {
519 { .irq = 103 + OMAP_INTC_START, },
523 static struct omap_hwmod_dma_info am33xx_aes0_edma_reqs[] = {
524 { .name = "tx", .dma_req = 6, },
525 { .name = "rx", .dma_req = 5, },
529 static struct omap_hwmod am33xx_aes0_hwmod = {
531 .class = &am33xx_aes0_hwmod_class,
532 .clkdm_name = "l3_clkdm",
533 .mpu_irqs = am33xx_aes0_irqs,
534 .sdma_reqs = am33xx_aes0_edma_reqs,
535 .main_clk = "aes0_fck",
538 .clkctrl_offs = AM33XX_CM_PER_AES0_CLKCTRL_OFFSET,
539 .modulemode = MODULEMODE_SWCTRL,
544 /* sha0 HIB2 (the 'P' (public) device) */
545 static struct omap_hwmod_class_sysconfig am33xx_sha0_sysc = {
549 .sysc_flags = SYSS_HAS_RESET_STATUS,
552 static struct omap_hwmod_class am33xx_sha0_hwmod_class = {
554 .sysc = &am33xx_sha0_sysc,
557 static struct omap_hwmod_irq_info am33xx_sha0_irqs[] = {
558 { .irq = 109 + OMAP_INTC_START, },
562 static struct omap_hwmod_dma_info am33xx_sha0_edma_reqs[] = {
563 { .name = "rx", .dma_req = 36, },
567 static struct omap_hwmod am33xx_sha0_hwmod = {
569 .class = &am33xx_sha0_hwmod_class,
570 .clkdm_name = "l3_clkdm",
571 .mpu_irqs = am33xx_sha0_irqs,
572 .sdma_reqs = am33xx_sha0_edma_reqs,
573 .main_clk = "l3_gclk",
576 .clkctrl_offs = AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET,
577 .modulemode = MODULEMODE_SWCTRL,
583 static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
587 static struct omap_hwmod am33xx_ocmcram_hwmod = {
589 .class = &am33xx_ocmcram_hwmod_class,
590 .clkdm_name = "l3_clkdm",
591 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
592 .main_clk = "l3_gclk",
595 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
596 .modulemode = MODULEMODE_SWCTRL,
601 /* 'smartreflex' class */
602 static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
603 .name = "smartreflex",
607 static struct omap_hwmod_irq_info am33xx_smartreflex0_irqs[] = {
608 { .irq = 120 + OMAP_INTC_START, },
612 static struct omap_hwmod am33xx_smartreflex0_hwmod = {
613 .name = "smartreflex0",
614 .class = &am33xx_smartreflex_hwmod_class,
615 .clkdm_name = "l4_wkup_clkdm",
616 .mpu_irqs = am33xx_smartreflex0_irqs,
617 .main_clk = "smartreflex0_fck",
620 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET,
621 .modulemode = MODULEMODE_SWCTRL,
627 static struct omap_hwmod_irq_info am33xx_smartreflex1_irqs[] = {
628 { .irq = 121 + OMAP_INTC_START, },
632 static struct omap_hwmod am33xx_smartreflex1_hwmod = {
633 .name = "smartreflex1",
634 .class = &am33xx_smartreflex_hwmod_class,
635 .clkdm_name = "l4_wkup_clkdm",
636 .mpu_irqs = am33xx_smartreflex1_irqs,
637 .main_clk = "smartreflex1_fck",
640 .clkctrl_offs = AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET,
641 .modulemode = MODULEMODE_SWCTRL,
647 * 'control' module class
649 static struct omap_hwmod_class am33xx_control_hwmod_class = {
653 static struct omap_hwmod_irq_info am33xx_control_irqs[] = {
654 { .irq = 8 + OMAP_INTC_START, },
658 static struct omap_hwmod am33xx_control_hwmod = {
660 .class = &am33xx_control_hwmod_class,
661 .clkdm_name = "l4_wkup_clkdm",
662 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
663 .mpu_irqs = am33xx_control_irqs,
664 .main_clk = "dpll_core_m4_div2_ck",
667 .clkctrl_offs = AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET,
668 .modulemode = MODULEMODE_SWCTRL,
675 * cpsw/cpgmac sub system
677 static struct omap_hwmod_class_sysconfig am33xx_cpgmac_sysc = {
681 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
682 SYSS_HAS_RESET_STATUS),
683 .idlemodes = (SIDLE_FORCE | SIDLE_NO | MSTANDBY_FORCE |
685 .sysc_fields = &omap_hwmod_sysc_type3,
688 static struct omap_hwmod_class am33xx_cpgmac0_hwmod_class = {
690 .sysc = &am33xx_cpgmac_sysc,
693 static struct omap_hwmod_irq_info am33xx_cpgmac0_irqs[] = {
694 { .name = "c0_rx_thresh_pend", .irq = 40 + OMAP_INTC_START, },
695 { .name = "c0_rx_pend", .irq = 41 + OMAP_INTC_START, },
696 { .name = "c0_tx_pend", .irq = 42 + OMAP_INTC_START, },
697 { .name = "c0_misc_pend", .irq = 43 + OMAP_INTC_START, },
701 static struct omap_hwmod am33xx_cpgmac0_hwmod = {
703 .class = &am33xx_cpgmac0_hwmod_class,
704 .clkdm_name = "cpsw_125mhz_clkdm",
705 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
706 .mpu_irqs = am33xx_cpgmac0_irqs,
707 .main_clk = "cpsw_125mhz_gclk",
710 .clkctrl_offs = AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET,
711 .modulemode = MODULEMODE_SWCTRL,
719 static struct omap_hwmod_class am33xx_mdio_hwmod_class = {
720 .name = "davinci_mdio",
723 static struct omap_hwmod am33xx_mdio_hwmod = {
724 .name = "davinci_mdio",
725 .class = &am33xx_mdio_hwmod_class,
726 .clkdm_name = "cpsw_125mhz_clkdm",
727 .main_clk = "cpsw_125mhz_gclk",
733 static struct omap_hwmod_class am33xx_dcan_hwmod_class = {
738 static struct omap_hwmod_irq_info am33xx_dcan0_irqs[] = {
739 { .name = "d_can_ms", .irq = 52 + OMAP_INTC_START, },
740 { .name = "d_can_mo", .irq = 53 + OMAP_INTC_START, },
744 static struct omap_hwmod am33xx_dcan0_hwmod = {
746 .class = &am33xx_dcan_hwmod_class,
747 .clkdm_name = "l4ls_clkdm",
748 .mpu_irqs = am33xx_dcan0_irqs,
749 .main_clk = "dcan0_fck",
752 .clkctrl_offs = AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET,
753 .modulemode = MODULEMODE_SWCTRL,
759 static struct omap_hwmod_irq_info am33xx_dcan1_irqs[] = {
760 { .name = "d_can_ms", .irq = 55 + OMAP_INTC_START, },
761 { .name = "d_can_mo", .irq = 56 + OMAP_INTC_START, },
764 static struct omap_hwmod am33xx_dcan1_hwmod = {
766 .class = &am33xx_dcan_hwmod_class,
767 .clkdm_name = "l4ls_clkdm",
768 .mpu_irqs = am33xx_dcan1_irqs,
769 .main_clk = "dcan1_fck",
772 .clkctrl_offs = AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET,
773 .modulemode = MODULEMODE_SWCTRL,
779 static struct omap_hwmod_class_sysconfig am33xx_elm_sysc = {
783 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
784 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
785 SYSS_HAS_RESET_STATUS),
786 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
787 .sysc_fields = &omap_hwmod_sysc_type1,
790 static struct omap_hwmod_class am33xx_elm_hwmod_class = {
792 .sysc = &am33xx_elm_sysc,
795 static struct omap_hwmod_irq_info am33xx_elm_irqs[] = {
796 { .irq = 4 + OMAP_INTC_START, },
800 static struct omap_hwmod am33xx_elm_hwmod = {
802 .class = &am33xx_elm_hwmod_class,
803 .clkdm_name = "l4ls_clkdm",
804 .mpu_irqs = am33xx_elm_irqs,
805 .main_clk = "l4ls_gclk",
808 .clkctrl_offs = AM33XX_CM_PER_ELM_CLKCTRL_OFFSET,
809 .modulemode = MODULEMODE_SWCTRL,
815 static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
818 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
819 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
820 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
821 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
822 .sysc_fields = &omap_hwmod_sysc_type2,
825 static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
827 .sysc = &am33xx_epwmss_sysc,
830 static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
834 static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
838 static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
843 static struct omap_hwmod am33xx_epwmss0_hwmod = {
845 .class = &am33xx_epwmss_hwmod_class,
846 .clkdm_name = "l4ls_clkdm",
847 .main_clk = "l4ls_gclk",
850 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET,
851 .modulemode = MODULEMODE_SWCTRL,
857 static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
858 { .irq = 31 + OMAP_INTC_START, },
862 static struct omap_hwmod am33xx_ecap0_hwmod = {
864 .class = &am33xx_ecap_hwmod_class,
865 .clkdm_name = "l4ls_clkdm",
866 .mpu_irqs = am33xx_ecap0_irqs,
867 .main_clk = "l4ls_gclk",
871 static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
872 { .irq = 79 + OMAP_INTC_START, },
876 static struct omap_hwmod am33xx_eqep0_hwmod = {
878 .class = &am33xx_eqep_hwmod_class,
879 .clkdm_name = "l4ls_clkdm",
880 .mpu_irqs = am33xx_eqep0_irqs,
881 .main_clk = "l4ls_gclk",
885 static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
886 { .name = "int", .irq = 86 + OMAP_INTC_START, },
887 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
891 static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
893 .class = &am33xx_ehrpwm_hwmod_class,
894 .clkdm_name = "l4ls_clkdm",
895 .mpu_irqs = am33xx_ehrpwm0_irqs,
896 .main_clk = "l4ls_gclk",
900 static struct omap_hwmod am33xx_epwmss1_hwmod = {
902 .class = &am33xx_epwmss_hwmod_class,
903 .clkdm_name = "l4ls_clkdm",
904 .main_clk = "l4ls_gclk",
907 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
908 .modulemode = MODULEMODE_SWCTRL,
914 static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
915 { .irq = 47 + OMAP_INTC_START, },
919 static struct omap_hwmod am33xx_ecap1_hwmod = {
921 .class = &am33xx_ecap_hwmod_class,
922 .clkdm_name = "l4ls_clkdm",
923 .mpu_irqs = am33xx_ecap1_irqs,
924 .main_clk = "l4ls_gclk",
928 static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
929 { .irq = 88 + OMAP_INTC_START, },
933 static struct omap_hwmod am33xx_eqep1_hwmod = {
935 .class = &am33xx_eqep_hwmod_class,
936 .clkdm_name = "l4ls_clkdm",
937 .mpu_irqs = am33xx_eqep1_irqs,
938 .main_clk = "l4ls_gclk",
942 static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
943 { .name = "int", .irq = 87 + OMAP_INTC_START, },
944 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
948 static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
950 .class = &am33xx_ehrpwm_hwmod_class,
951 .clkdm_name = "l4ls_clkdm",
952 .mpu_irqs = am33xx_ehrpwm1_irqs,
953 .main_clk = "l4ls_gclk",
957 static struct omap_hwmod am33xx_epwmss2_hwmod = {
959 .class = &am33xx_epwmss_hwmod_class,
960 .clkdm_name = "l4ls_clkdm",
961 .main_clk = "l4ls_gclk",
964 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
965 .modulemode = MODULEMODE_SWCTRL,
971 static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
972 { .irq = 61 + OMAP_INTC_START, },
976 static struct omap_hwmod am33xx_ecap2_hwmod = {
978 .class = &am33xx_ecap_hwmod_class,
979 .clkdm_name = "l4ls_clkdm",
980 .mpu_irqs = am33xx_ecap2_irqs,
981 .main_clk = "l4ls_gclk",
985 static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
986 { .irq = 89 + OMAP_INTC_START, },
990 static struct omap_hwmod am33xx_eqep2_hwmod = {
992 .class = &am33xx_eqep_hwmod_class,
993 .clkdm_name = "l4ls_clkdm",
994 .mpu_irqs = am33xx_eqep2_irqs,
995 .main_clk = "l4ls_gclk",
999 static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
1000 { .name = "int", .irq = 39 + OMAP_INTC_START, },
1001 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
1005 static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
1007 .class = &am33xx_ehrpwm_hwmod_class,
1008 .clkdm_name = "l4ls_clkdm",
1009 .mpu_irqs = am33xx_ehrpwm2_irqs,
1010 .main_clk = "l4ls_gclk",
1014 * 'gpio' class: for gpio 0,1,2,3
1016 static struct omap_hwmod_class_sysconfig am33xx_gpio_sysc = {
1018 .sysc_offs = 0x0010,
1019 .syss_offs = 0x0114,
1020 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1021 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1022 SYSS_HAS_RESET_STATUS),
1023 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1025 .sysc_fields = &omap_hwmod_sysc_type1,
1028 static struct omap_hwmod_class am33xx_gpio_hwmod_class = {
1030 .sysc = &am33xx_gpio_sysc,
1034 static struct omap_gpio_dev_attr gpio_dev_attr = {
1040 static struct omap_hwmod_opt_clk gpio0_opt_clks[] = {
1041 { .role = "dbclk", .clk = "gpio0_dbclk" },
1044 static struct omap_hwmod_irq_info am33xx_gpio0_irqs[] = {
1045 { .irq = 96 + OMAP_INTC_START, },
1049 static struct omap_hwmod am33xx_gpio0_hwmod = {
1051 .class = &am33xx_gpio_hwmod_class,
1052 .clkdm_name = "l4_wkup_clkdm",
1053 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1054 .mpu_irqs = am33xx_gpio0_irqs,
1055 .main_clk = "dpll_core_m4_div2_ck",
1058 .clkctrl_offs = AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET,
1059 .modulemode = MODULEMODE_SWCTRL,
1062 .opt_clks = gpio0_opt_clks,
1063 .opt_clks_cnt = ARRAY_SIZE(gpio0_opt_clks),
1064 .dev_attr = &gpio_dev_attr,
1068 static struct omap_hwmod_irq_info am33xx_gpio1_irqs[] = {
1069 { .irq = 98 + OMAP_INTC_START, },
1073 static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1074 { .role = "dbclk", .clk = "gpio1_dbclk" },
1077 static struct omap_hwmod am33xx_gpio1_hwmod = {
1079 .class = &am33xx_gpio_hwmod_class,
1080 .clkdm_name = "l4ls_clkdm",
1081 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1082 .mpu_irqs = am33xx_gpio1_irqs,
1083 .main_clk = "l4ls_gclk",
1086 .clkctrl_offs = AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1090 .opt_clks = gpio1_opt_clks,
1091 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
1092 .dev_attr = &gpio_dev_attr,
1096 static struct omap_hwmod_irq_info am33xx_gpio2_irqs[] = {
1097 { .irq = 32 + OMAP_INTC_START, },
1101 static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1102 { .role = "dbclk", .clk = "gpio2_dbclk" },
1105 static struct omap_hwmod am33xx_gpio2_hwmod = {
1107 .class = &am33xx_gpio_hwmod_class,
1108 .clkdm_name = "l4ls_clkdm",
1109 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1110 .mpu_irqs = am33xx_gpio2_irqs,
1111 .main_clk = "l4ls_gclk",
1114 .clkctrl_offs = AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET,
1115 .modulemode = MODULEMODE_SWCTRL,
1118 .opt_clks = gpio2_opt_clks,
1119 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
1120 .dev_attr = &gpio_dev_attr,
1124 static struct omap_hwmod_irq_info am33xx_gpio3_irqs[] = {
1125 { .irq = 62 + OMAP_INTC_START, },
1129 static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1130 { .role = "dbclk", .clk = "gpio3_dbclk" },
1133 static struct omap_hwmod am33xx_gpio3_hwmod = {
1135 .class = &am33xx_gpio_hwmod_class,
1136 .clkdm_name = "l4ls_clkdm",
1137 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1138 .mpu_irqs = am33xx_gpio3_irqs,
1139 .main_clk = "l4ls_gclk",
1142 .clkctrl_offs = AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET,
1143 .modulemode = MODULEMODE_SWCTRL,
1146 .opt_clks = gpio3_opt_clks,
1147 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
1148 .dev_attr = &gpio_dev_attr,
1152 static struct omap_hwmod_class_sysconfig gpmc_sysc = {
1156 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1157 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1158 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1159 .sysc_fields = &omap_hwmod_sysc_type1,
1162 static struct omap_hwmod_class am33xx_gpmc_hwmod_class = {
1167 static struct omap_hwmod_irq_info am33xx_gpmc_irqs[] = {
1168 { .irq = 100 + OMAP_INTC_START, },
1172 static struct omap_hwmod am33xx_gpmc_hwmod = {
1174 .class = &am33xx_gpmc_hwmod_class,
1175 .clkdm_name = "l3s_clkdm",
1176 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
1177 .mpu_irqs = am33xx_gpmc_irqs,
1178 .main_clk = "l3s_gclk",
1181 .clkctrl_offs = AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET,
1182 .modulemode = MODULEMODE_SWCTRL,
1188 static struct omap_hwmod_class_sysconfig am33xx_i2c_sysc = {
1189 .sysc_offs = 0x0010,
1190 .syss_offs = 0x0090,
1191 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1192 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1193 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1194 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1196 .sysc_fields = &omap_hwmod_sysc_type1,
1199 static struct omap_hwmod_class i2c_class = {
1201 .sysc = &am33xx_i2c_sysc,
1202 .rev = OMAP_I2C_IP_VERSION_2,
1203 .reset = &omap_i2c_reset,
1206 static struct omap_i2c_dev_attr i2c_dev_attr = {
1207 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
1211 static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
1212 { .irq = 70 + OMAP_INTC_START, },
1216 static struct omap_hwmod_dma_info i2c1_edma_reqs[] = {
1217 { .name = "tx", .dma_req = 0, },
1218 { .name = "rx", .dma_req = 0, },
1222 static struct omap_hwmod am33xx_i2c1_hwmod = {
1224 .class = &i2c_class,
1225 .clkdm_name = "l4_wkup_clkdm",
1226 .mpu_irqs = i2c1_mpu_irqs,
1227 .sdma_reqs = i2c1_edma_reqs,
1228 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1229 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
1232 .clkctrl_offs = AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET,
1233 .modulemode = MODULEMODE_SWCTRL,
1236 .dev_attr = &i2c_dev_attr,
1240 static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
1241 { .irq = 71 + OMAP_INTC_START, },
1245 static struct omap_hwmod_dma_info i2c2_edma_reqs[] = {
1246 { .name = "tx", .dma_req = 0, },
1247 { .name = "rx", .dma_req = 0, },
1251 static struct omap_hwmod am33xx_i2c2_hwmod = {
1253 .class = &i2c_class,
1254 .clkdm_name = "l4ls_clkdm",
1255 .mpu_irqs = i2c2_mpu_irqs,
1256 .sdma_reqs = i2c2_edma_reqs,
1257 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1258 .main_clk = "dpll_per_m2_div4_ck",
1261 .clkctrl_offs = AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET,
1262 .modulemode = MODULEMODE_SWCTRL,
1265 .dev_attr = &i2c_dev_attr,
1269 static struct omap_hwmod_dma_info i2c3_edma_reqs[] = {
1270 { .name = "tx", .dma_req = 0, },
1271 { .name = "rx", .dma_req = 0, },
1275 static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
1276 { .irq = 30 + OMAP_INTC_START, },
1280 static struct omap_hwmod am33xx_i2c3_hwmod = {
1282 .class = &i2c_class,
1283 .clkdm_name = "l4ls_clkdm",
1284 .mpu_irqs = i2c3_mpu_irqs,
1285 .sdma_reqs = i2c3_edma_reqs,
1286 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1287 .main_clk = "dpll_per_m2_div4_ck",
1290 .clkctrl_offs = AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET,
1291 .modulemode = MODULEMODE_SWCTRL,
1294 .dev_attr = &i2c_dev_attr,
1299 static struct omap_hwmod_class_sysconfig lcdc_sysc = {
1302 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
1303 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1304 .sysc_fields = &omap_hwmod_sysc_type2,
1307 static struct omap_hwmod_class am33xx_lcdc_hwmod_class = {
1312 static struct omap_hwmod_irq_info am33xx_lcdc_irqs[] = {
1313 { .irq = 36 + OMAP_INTC_START, },
1317 static struct omap_hwmod am33xx_lcdc_hwmod = {
1319 .class = &am33xx_lcdc_hwmod_class,
1320 .clkdm_name = "lcdc_clkdm",
1321 .mpu_irqs = am33xx_lcdc_irqs,
1322 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1323 .main_clk = "lcd_gclk",
1326 .clkctrl_offs = AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET,
1327 .modulemode = MODULEMODE_SWCTRL,
1334 * mailbox module allowing communication between the on-chip processors using a
1335 * queued mailbox-interrupt mechanism.
1337 static struct omap_hwmod_class_sysconfig am33xx_mailbox_sysc = {
1339 .sysc_offs = 0x0010,
1340 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1341 SYSC_HAS_SOFTRESET),
1342 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1343 .sysc_fields = &omap_hwmod_sysc_type2,
1346 static struct omap_hwmod_class am33xx_mailbox_hwmod_class = {
1348 .sysc = &am33xx_mailbox_sysc,
1351 static struct omap_hwmod_irq_info am33xx_mailbox_irqs[] = {
1352 { .irq = 77 + OMAP_INTC_START, },
1356 static struct omap_hwmod am33xx_mailbox_hwmod = {
1358 .class = &am33xx_mailbox_hwmod_class,
1359 .clkdm_name = "l4ls_clkdm",
1360 .mpu_irqs = am33xx_mailbox_irqs,
1361 .main_clk = "l4ls_gclk",
1364 .clkctrl_offs = AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET,
1365 .modulemode = MODULEMODE_SWCTRL,
1373 static struct omap_hwmod_class_sysconfig am33xx_mcasp_sysc = {
1376 .sysc_flags = SYSC_HAS_SIDLEMODE,
1377 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1378 .sysc_fields = &omap_hwmod_sysc_type3,
1381 static struct omap_hwmod_class am33xx_mcasp_hwmod_class = {
1383 .sysc = &am33xx_mcasp_sysc,
1387 static struct omap_hwmod_irq_info am33xx_mcasp0_irqs[] = {
1388 { .name = "ax", .irq = 80 + OMAP_INTC_START, },
1389 { .name = "ar", .irq = 81 + OMAP_INTC_START, },
1393 static struct omap_hwmod_dma_info am33xx_mcasp0_edma_reqs[] = {
1394 { .name = "tx", .dma_req = 8, },
1395 { .name = "rx", .dma_req = 9, },
1399 static struct omap_hwmod am33xx_mcasp0_hwmod = {
1401 .class = &am33xx_mcasp_hwmod_class,
1402 .clkdm_name = "l3s_clkdm",
1403 .mpu_irqs = am33xx_mcasp0_irqs,
1404 .sdma_reqs = am33xx_mcasp0_edma_reqs,
1405 .main_clk = "mcasp0_fck",
1408 .clkctrl_offs = AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET,
1409 .modulemode = MODULEMODE_SWCTRL,
1415 static struct omap_hwmod_irq_info am33xx_mcasp1_irqs[] = {
1416 { .name = "ax", .irq = 82 + OMAP_INTC_START, },
1417 { .name = "ar", .irq = 83 + OMAP_INTC_START, },
1421 static struct omap_hwmod_dma_info am33xx_mcasp1_edma_reqs[] = {
1422 { .name = "tx", .dma_req = 10, },
1423 { .name = "rx", .dma_req = 11, },
1427 static struct omap_hwmod am33xx_mcasp1_hwmod = {
1429 .class = &am33xx_mcasp_hwmod_class,
1430 .clkdm_name = "l3s_clkdm",
1431 .mpu_irqs = am33xx_mcasp1_irqs,
1432 .sdma_reqs = am33xx_mcasp1_edma_reqs,
1433 .main_clk = "mcasp1_fck",
1436 .clkctrl_offs = AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET,
1437 .modulemode = MODULEMODE_SWCTRL,
1443 static struct omap_hwmod_class_sysconfig am33xx_mmc_sysc = {
1447 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1448 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
1449 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
1450 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1451 .sysc_fields = &omap_hwmod_sysc_type1,
1454 static struct omap_hwmod_class am33xx_mmc_hwmod_class = {
1456 .sysc = &am33xx_mmc_sysc,
1460 static struct omap_hwmod_irq_info am33xx_mmc0_irqs[] = {
1461 { .irq = 64 + OMAP_INTC_START, },
1465 static struct omap_hwmod_dma_info am33xx_mmc0_edma_reqs[] = {
1466 { .name = "tx", .dma_req = 24, },
1467 { .name = "rx", .dma_req = 25, },
1471 static struct omap_mmc_dev_attr am33xx_mmc0_dev_attr = {
1472 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1475 static struct omap_hwmod am33xx_mmc0_hwmod = {
1477 .class = &am33xx_mmc_hwmod_class,
1478 .clkdm_name = "l4ls_clkdm",
1479 .mpu_irqs = am33xx_mmc0_irqs,
1480 .sdma_reqs = am33xx_mmc0_edma_reqs,
1481 .main_clk = "mmc_clk",
1484 .clkctrl_offs = AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET,
1485 .modulemode = MODULEMODE_SWCTRL,
1488 .dev_attr = &am33xx_mmc0_dev_attr,
1492 static struct omap_hwmod_irq_info am33xx_mmc1_irqs[] = {
1493 { .irq = 28 + OMAP_INTC_START, },
1497 static struct omap_hwmod_dma_info am33xx_mmc1_edma_reqs[] = {
1498 { .name = "tx", .dma_req = 2, },
1499 { .name = "rx", .dma_req = 3, },
1503 static struct omap_mmc_dev_attr am33xx_mmc1_dev_attr = {
1504 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1507 static struct omap_hwmod am33xx_mmc1_hwmod = {
1509 .class = &am33xx_mmc_hwmod_class,
1510 .clkdm_name = "l4ls_clkdm",
1511 .mpu_irqs = am33xx_mmc1_irqs,
1512 .sdma_reqs = am33xx_mmc1_edma_reqs,
1513 .main_clk = "mmc_clk",
1516 .clkctrl_offs = AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET,
1517 .modulemode = MODULEMODE_SWCTRL,
1520 .dev_attr = &am33xx_mmc1_dev_attr,
1524 static struct omap_hwmod_irq_info am33xx_mmc2_irqs[] = {
1525 { .irq = 29 + OMAP_INTC_START, },
1529 static struct omap_hwmod_dma_info am33xx_mmc2_edma_reqs[] = {
1530 { .name = "tx", .dma_req = 64, },
1531 { .name = "rx", .dma_req = 65, },
1535 static struct omap_mmc_dev_attr am33xx_mmc2_dev_attr = {
1536 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1538 static struct omap_hwmod am33xx_mmc2_hwmod = {
1540 .class = &am33xx_mmc_hwmod_class,
1541 .clkdm_name = "l3s_clkdm",
1542 .mpu_irqs = am33xx_mmc2_irqs,
1543 .sdma_reqs = am33xx_mmc2_edma_reqs,
1544 .main_clk = "mmc_clk",
1547 .clkctrl_offs = AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET,
1548 .modulemode = MODULEMODE_SWCTRL,
1551 .dev_attr = &am33xx_mmc2_dev_attr,
1558 static struct omap_hwmod_class_sysconfig am33xx_rtc_sysc = {
1560 .sysc_offs = 0x0078,
1561 .sysc_flags = SYSC_HAS_SIDLEMODE,
1562 .idlemodes = (SIDLE_FORCE | SIDLE_NO |
1563 SIDLE_SMART | SIDLE_SMART_WKUP),
1564 .sysc_fields = &omap_hwmod_sysc_type3,
1567 static struct omap_hwmod_class am33xx_rtc_hwmod_class = {
1569 .sysc = &am33xx_rtc_sysc,
1572 static struct omap_hwmod_irq_info am33xx_rtc_irqs[] = {
1573 { .name = "rtcint", .irq = 75 + OMAP_INTC_START, },
1574 { .name = "rtcalarmint", .irq = 76 + OMAP_INTC_START, },
1578 static struct omap_hwmod am33xx_rtc_hwmod = {
1580 .class = &am33xx_rtc_hwmod_class,
1581 .clkdm_name = "l4_rtc_clkdm",
1582 .mpu_irqs = am33xx_rtc_irqs,
1583 .main_clk = "clk_32768_ck",
1586 .clkctrl_offs = AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET,
1587 .modulemode = MODULEMODE_SWCTRL,
1593 static struct omap_hwmod_class_sysconfig am33xx_mcspi_sysc = {
1595 .sysc_offs = 0x0110,
1596 .syss_offs = 0x0114,
1597 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1598 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1599 SYSS_HAS_RESET_STATUS),
1600 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1601 .sysc_fields = &omap_hwmod_sysc_type1,
1604 static struct omap_hwmod_class am33xx_spi_hwmod_class = {
1606 .sysc = &am33xx_mcspi_sysc,
1607 .rev = OMAP4_MCSPI_REV,
1611 static struct omap_hwmod_irq_info am33xx_spi0_irqs[] = {
1612 { .irq = 65 + OMAP_INTC_START, },
1616 static struct omap_hwmod_dma_info am33xx_mcspi0_edma_reqs[] = {
1617 { .name = "rx0", .dma_req = 17 },
1618 { .name = "tx0", .dma_req = 16 },
1619 { .name = "rx1", .dma_req = 19 },
1620 { .name = "tx1", .dma_req = 18 },
1624 static struct omap2_mcspi_dev_attr mcspi_attrib = {
1625 .num_chipselect = 2,
1627 static struct omap_hwmod am33xx_spi0_hwmod = {
1629 .class = &am33xx_spi_hwmod_class,
1630 .clkdm_name = "l4ls_clkdm",
1631 .mpu_irqs = am33xx_spi0_irqs,
1632 .sdma_reqs = am33xx_mcspi0_edma_reqs,
1633 .main_clk = "dpll_per_m2_div4_ck",
1636 .clkctrl_offs = AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET,
1637 .modulemode = MODULEMODE_SWCTRL,
1640 .dev_attr = &mcspi_attrib,
1644 static struct omap_hwmod_irq_info am33xx_spi1_irqs[] = {
1645 { .irq = 125 + OMAP_INTC_START, },
1649 static struct omap_hwmod_dma_info am33xx_mcspi1_edma_reqs[] = {
1650 { .name = "rx0", .dma_req = 43 },
1651 { .name = "tx0", .dma_req = 42 },
1652 { .name = "rx1", .dma_req = 45 },
1653 { .name = "tx1", .dma_req = 44 },
1657 static struct omap_hwmod am33xx_spi1_hwmod = {
1659 .class = &am33xx_spi_hwmod_class,
1660 .clkdm_name = "l4ls_clkdm",
1661 .mpu_irqs = am33xx_spi1_irqs,
1662 .sdma_reqs = am33xx_mcspi1_edma_reqs,
1663 .main_clk = "dpll_per_m2_div4_ck",
1666 .clkctrl_offs = AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET,
1667 .modulemode = MODULEMODE_SWCTRL,
1670 .dev_attr = &mcspi_attrib,
1675 * spinlock provides hardware assistance for synchronizing the
1676 * processes running on multiple processors
1678 static struct omap_hwmod_class am33xx_spinlock_hwmod_class = {
1682 static struct omap_hwmod am33xx_spinlock_hwmod = {
1684 .class = &am33xx_spinlock_hwmod_class,
1685 .clkdm_name = "l4ls_clkdm",
1686 .main_clk = "l4ls_gclk",
1689 .clkctrl_offs = AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET,
1690 .modulemode = MODULEMODE_SWCTRL,
1695 /* 'timer 2-7' class */
1696 static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
1698 .sysc_offs = 0x0010,
1699 .syss_offs = 0x0014,
1700 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1701 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1703 .sysc_fields = &omap_hwmod_sysc_type2,
1706 static struct omap_hwmod_class am33xx_timer_hwmod_class = {
1708 .sysc = &am33xx_timer_sysc,
1712 static struct omap_hwmod_class_sysconfig am33xx_timer1ms_sysc = {
1714 .sysc_offs = 0x0010,
1715 .syss_offs = 0x0014,
1716 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
1717 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
1718 SYSS_HAS_RESET_STATUS),
1719 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1720 .sysc_fields = &omap_hwmod_sysc_type1,
1723 static struct omap_hwmod_class am33xx_timer1ms_hwmod_class = {
1725 .sysc = &am33xx_timer1ms_sysc,
1728 static struct omap_hwmod_irq_info am33xx_timer1_irqs[] = {
1729 { .irq = 67 + OMAP_INTC_START, },
1733 static struct omap_hwmod am33xx_timer1_hwmod = {
1735 .class = &am33xx_timer1ms_hwmod_class,
1736 .clkdm_name = "l4_wkup_clkdm",
1737 .mpu_irqs = am33xx_timer1_irqs,
1738 .main_clk = "timer1_fck",
1741 .clkctrl_offs = AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
1742 .modulemode = MODULEMODE_SWCTRL,
1747 static struct omap_hwmod_irq_info am33xx_timer2_irqs[] = {
1748 { .irq = 68 + OMAP_INTC_START, },
1752 static struct omap_hwmod am33xx_timer2_hwmod = {
1754 .class = &am33xx_timer_hwmod_class,
1755 .clkdm_name = "l4ls_clkdm",
1756 .mpu_irqs = am33xx_timer2_irqs,
1757 .main_clk = "timer2_fck",
1760 .clkctrl_offs = AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET,
1761 .modulemode = MODULEMODE_SWCTRL,
1766 static struct omap_hwmod_irq_info am33xx_timer3_irqs[] = {
1767 { .irq = 69 + OMAP_INTC_START, },
1771 static struct omap_hwmod am33xx_timer3_hwmod = {
1773 .class = &am33xx_timer_hwmod_class,
1774 .clkdm_name = "l4ls_clkdm",
1775 .mpu_irqs = am33xx_timer3_irqs,
1776 .main_clk = "timer3_fck",
1779 .clkctrl_offs = AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET,
1780 .modulemode = MODULEMODE_SWCTRL,
1785 static struct omap_hwmod_irq_info am33xx_timer4_irqs[] = {
1786 { .irq = 92 + OMAP_INTC_START, },
1790 static struct omap_hwmod am33xx_timer4_hwmod = {
1792 .class = &am33xx_timer_hwmod_class,
1793 .clkdm_name = "l4ls_clkdm",
1794 .mpu_irqs = am33xx_timer4_irqs,
1795 .main_clk = "timer4_fck",
1798 .clkctrl_offs = AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET,
1799 .modulemode = MODULEMODE_SWCTRL,
1804 static struct omap_hwmod_irq_info am33xx_timer5_irqs[] = {
1805 { .irq = 93 + OMAP_INTC_START, },
1809 static struct omap_hwmod am33xx_timer5_hwmod = {
1811 .class = &am33xx_timer_hwmod_class,
1812 .clkdm_name = "l4ls_clkdm",
1813 .mpu_irqs = am33xx_timer5_irqs,
1814 .main_clk = "timer5_fck",
1817 .clkctrl_offs = AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET,
1818 .modulemode = MODULEMODE_SWCTRL,
1823 static struct omap_hwmod_irq_info am33xx_timer6_irqs[] = {
1824 { .irq = 94 + OMAP_INTC_START, },
1828 static struct omap_hwmod am33xx_timer6_hwmod = {
1830 .class = &am33xx_timer_hwmod_class,
1831 .clkdm_name = "l4ls_clkdm",
1832 .mpu_irqs = am33xx_timer6_irqs,
1833 .main_clk = "timer6_fck",
1836 .clkctrl_offs = AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET,
1837 .modulemode = MODULEMODE_SWCTRL,
1842 static struct omap_hwmod_irq_info am33xx_timer7_irqs[] = {
1843 { .irq = 95 + OMAP_INTC_START, },
1847 static struct omap_hwmod am33xx_timer7_hwmod = {
1849 .class = &am33xx_timer_hwmod_class,
1850 .clkdm_name = "l4ls_clkdm",
1851 .mpu_irqs = am33xx_timer7_irqs,
1852 .main_clk = "timer7_fck",
1855 .clkctrl_offs = AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET,
1856 .modulemode = MODULEMODE_SWCTRL,
1862 static struct omap_hwmod_class am33xx_tpcc_hwmod_class = {
1866 static struct omap_hwmod_irq_info am33xx_tpcc_irqs[] = {
1867 { .name = "edma0", .irq = 12 + OMAP_INTC_START, },
1868 { .name = "edma0_mperr", .irq = 13 + OMAP_INTC_START, },
1869 { .name = "edma0_err", .irq = 14 + OMAP_INTC_START, },
1873 static struct omap_hwmod am33xx_tpcc_hwmod = {
1875 .class = &am33xx_tpcc_hwmod_class,
1876 .clkdm_name = "l3_clkdm",
1877 .mpu_irqs = am33xx_tpcc_irqs,
1878 .main_clk = "l3_gclk",
1881 .clkctrl_offs = AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET,
1882 .modulemode = MODULEMODE_SWCTRL,
1887 static struct omap_hwmod_class_sysconfig am33xx_tptc_sysc = {
1890 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1891 SYSC_HAS_MIDLEMODE),
1892 .idlemodes = (SIDLE_FORCE | SIDLE_SMART | MSTANDBY_FORCE),
1893 .sysc_fields = &omap_hwmod_sysc_type2,
1897 static struct omap_hwmod_class am33xx_tptc_hwmod_class = {
1899 .sysc = &am33xx_tptc_sysc,
1903 static struct omap_hwmod_irq_info am33xx_tptc0_irqs[] = {
1904 { .irq = 112 + OMAP_INTC_START, },
1908 static struct omap_hwmod am33xx_tptc0_hwmod = {
1910 .class = &am33xx_tptc_hwmod_class,
1911 .clkdm_name = "l3_clkdm",
1912 .mpu_irqs = am33xx_tptc0_irqs,
1913 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1914 .main_clk = "l3_gclk",
1917 .clkctrl_offs = AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET,
1918 .modulemode = MODULEMODE_SWCTRL,
1924 static struct omap_hwmod_irq_info am33xx_tptc1_irqs[] = {
1925 { .irq = 113 + OMAP_INTC_START, },
1929 static struct omap_hwmod am33xx_tptc1_hwmod = {
1931 .class = &am33xx_tptc_hwmod_class,
1932 .clkdm_name = "l3_clkdm",
1933 .mpu_irqs = am33xx_tptc1_irqs,
1934 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1935 .main_clk = "l3_gclk",
1938 .clkctrl_offs = AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET,
1939 .modulemode = MODULEMODE_SWCTRL,
1945 static struct omap_hwmod_irq_info am33xx_tptc2_irqs[] = {
1946 { .irq = 114 + OMAP_INTC_START, },
1950 static struct omap_hwmod am33xx_tptc2_hwmod = {
1952 .class = &am33xx_tptc_hwmod_class,
1953 .clkdm_name = "l3_clkdm",
1954 .mpu_irqs = am33xx_tptc2_irqs,
1955 .flags = (HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY),
1956 .main_clk = "l3_gclk",
1959 .clkctrl_offs = AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET,
1960 .modulemode = MODULEMODE_SWCTRL,
1966 static struct omap_hwmod_class_sysconfig uart_sysc = {
1970 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
1971 SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
1972 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1974 .sysc_fields = &omap_hwmod_sysc_type1,
1977 static struct omap_hwmod_class uart_class = {
1983 static struct omap_hwmod_dma_info uart1_edma_reqs[] = {
1984 { .name = "tx", .dma_req = 26, },
1985 { .name = "rx", .dma_req = 27, },
1989 static struct omap_hwmod_irq_info am33xx_uart1_irqs[] = {
1990 { .irq = 72 + OMAP_INTC_START, },
1994 static struct omap_hwmod am33xx_uart1_hwmod = {
1996 .class = &uart_class,
1997 .clkdm_name = "l4_wkup_clkdm",
1998 .mpu_irqs = am33xx_uart1_irqs,
1999 .sdma_reqs = uart1_edma_reqs,
2000 .main_clk = "dpll_per_m2_div4_wkupdm_ck",
2003 .clkctrl_offs = AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET,
2004 .modulemode = MODULEMODE_SWCTRL,
2009 static struct omap_hwmod_irq_info am33xx_uart2_irqs[] = {
2010 { .irq = 73 + OMAP_INTC_START, },
2014 static struct omap_hwmod am33xx_uart2_hwmod = {
2016 .class = &uart_class,
2017 .clkdm_name = "l4ls_clkdm",
2018 .mpu_irqs = am33xx_uart2_irqs,
2019 .sdma_reqs = uart1_edma_reqs,
2020 .main_clk = "dpll_per_m2_div4_ck",
2023 .clkctrl_offs = AM33XX_CM_PER_UART1_CLKCTRL_OFFSET,
2024 .modulemode = MODULEMODE_SWCTRL,
2030 static struct omap_hwmod_dma_info uart3_edma_reqs[] = {
2031 { .name = "tx", .dma_req = 30, },
2032 { .name = "rx", .dma_req = 31, },
2036 static struct omap_hwmod_irq_info am33xx_uart3_irqs[] = {
2037 { .irq = 74 + OMAP_INTC_START, },
2041 static struct omap_hwmod am33xx_uart3_hwmod = {
2043 .class = &uart_class,
2044 .clkdm_name = "l4ls_clkdm",
2045 .mpu_irqs = am33xx_uart3_irqs,
2046 .sdma_reqs = uart3_edma_reqs,
2047 .main_clk = "dpll_per_m2_div4_ck",
2050 .clkctrl_offs = AM33XX_CM_PER_UART2_CLKCTRL_OFFSET,
2051 .modulemode = MODULEMODE_SWCTRL,
2056 static struct omap_hwmod_irq_info am33xx_uart4_irqs[] = {
2057 { .irq = 44 + OMAP_INTC_START, },
2061 static struct omap_hwmod am33xx_uart4_hwmod = {
2063 .class = &uart_class,
2064 .clkdm_name = "l4ls_clkdm",
2065 .mpu_irqs = am33xx_uart4_irqs,
2066 .sdma_reqs = uart1_edma_reqs,
2067 .main_clk = "dpll_per_m2_div4_ck",
2070 .clkctrl_offs = AM33XX_CM_PER_UART3_CLKCTRL_OFFSET,
2071 .modulemode = MODULEMODE_SWCTRL,
2076 static struct omap_hwmod_irq_info am33xx_uart5_irqs[] = {
2077 { .irq = 45 + OMAP_INTC_START, },
2081 static struct omap_hwmod am33xx_uart5_hwmod = {
2083 .class = &uart_class,
2084 .clkdm_name = "l4ls_clkdm",
2085 .mpu_irqs = am33xx_uart5_irqs,
2086 .sdma_reqs = uart1_edma_reqs,
2087 .main_clk = "dpll_per_m2_div4_ck",
2090 .clkctrl_offs = AM33XX_CM_PER_UART4_CLKCTRL_OFFSET,
2091 .modulemode = MODULEMODE_SWCTRL,
2096 static struct omap_hwmod_irq_info am33xx_uart6_irqs[] = {
2097 { .irq = 46 + OMAP_INTC_START, },
2101 static struct omap_hwmod am33xx_uart6_hwmod = {
2103 .class = &uart_class,
2104 .clkdm_name = "l4ls_clkdm",
2105 .mpu_irqs = am33xx_uart6_irqs,
2106 .sdma_reqs = uart1_edma_reqs,
2107 .main_clk = "dpll_per_m2_div4_ck",
2110 .clkctrl_offs = AM33XX_CM_PER_UART5_CLKCTRL_OFFSET,
2111 .modulemode = MODULEMODE_SWCTRL,
2116 /* 'wd_timer' class */
2117 static struct omap_hwmod_class_sysconfig wdt_sysc = {
2121 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2122 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2123 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2125 .sysc_fields = &omap_hwmod_sysc_type1,
2128 static struct omap_hwmod_class am33xx_wd_timer_hwmod_class = {
2131 .pre_shutdown = &omap2_wd_timer_disable,
2135 * XXX: device.c file uses hardcoded name for watchdog timer
2136 * driver "wd_timer2, so we are also using same name as of now...
2138 static struct omap_hwmod am33xx_wd_timer1_hwmod = {
2139 .name = "wd_timer2",
2140 .class = &am33xx_wd_timer_hwmod_class,
2141 .clkdm_name = "l4_wkup_clkdm",
2142 .flags = HWMOD_SWSUP_SIDLE,
2143 .main_clk = "wdt1_fck",
2146 .clkctrl_offs = AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET,
2147 .modulemode = MODULEMODE_SWCTRL,
2154 * high-speed on-the-go universal serial bus (usb_otg) controller
2156 static struct omap_hwmod_class_sysconfig am33xx_usbhsotg_sysc = {
2159 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE),
2160 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2161 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
2162 .sysc_fields = &omap_hwmod_sysc_type2,
2165 static struct omap_hwmod_class am33xx_usbotg_class = {
2167 .sysc = &am33xx_usbhsotg_sysc,
2170 static struct omap_hwmod_irq_info am33xx_usbss_mpu_irqs[] = {
2171 { .name = "usbss-irq", .irq = 17 + OMAP_INTC_START, },
2172 { .name = "musb0-irq", .irq = 18 + OMAP_INTC_START, },
2173 { .name = "musb1-irq", .irq = 19 + OMAP_INTC_START, },
2177 static struct omap_hwmod am33xx_usbss_hwmod = {
2178 .name = "usb_otg_hs",
2179 .class = &am33xx_usbotg_class,
2180 .clkdm_name = "l3s_clkdm",
2181 .mpu_irqs = am33xx_usbss_mpu_irqs,
2182 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2183 .main_clk = "usbotg_fck",
2186 .clkctrl_offs = AM33XX_CM_PER_USB0_CLKCTRL_OFFSET,
2187 .modulemode = MODULEMODE_SWCTRL,
2197 /* l4 fw -> emif fw */
2198 static struct omap_hwmod_ocp_if am33xx_l4_fw__emif_fw = {
2199 .master = &am33xx_l4_fw_hwmod,
2200 .slave = &am33xx_emif_fw_hwmod,
2202 .user = OCP_USER_MPU,
2205 static struct omap_hwmod_addr_space am33xx_emif_addrs[] = {
2207 .pa_start = 0x4c000000,
2208 .pa_end = 0x4c000fff,
2209 .flags = ADDR_TYPE_RT
2213 /* l3 main -> emif */
2214 static struct omap_hwmod_ocp_if am33xx_l3_main__emif = {
2215 .master = &am33xx_l3_main_hwmod,
2216 .slave = &am33xx_emif_hwmod,
2217 .clk = "dpll_core_m4_ck",
2218 .addr = am33xx_emif_addrs,
2219 .user = OCP_USER_MPU | OCP_USER_SDMA,
2222 /* mpu -> l3 main */
2223 static struct omap_hwmod_ocp_if am33xx_mpu__l3_main = {
2224 .master = &am33xx_mpu_hwmod,
2225 .slave = &am33xx_l3_main_hwmod,
2226 .clk = "dpll_mpu_m2_ck",
2227 .user = OCP_USER_MPU,
2230 /* l3 main -> l4 hs */
2231 static struct omap_hwmod_ocp_if am33xx_l3_main__l4_hs = {
2232 .master = &am33xx_l3_main_hwmod,
2233 .slave = &am33xx_l4_hs_hwmod,
2235 .user = OCP_USER_MPU | OCP_USER_SDMA,
2238 /* l3 main -> l3 s */
2239 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_s = {
2240 .master = &am33xx_l3_main_hwmod,
2241 .slave = &am33xx_l3_s_hwmod,
2243 .user = OCP_USER_MPU | OCP_USER_SDMA,
2246 /* l3 s -> l4 per/ls */
2247 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_ls = {
2248 .master = &am33xx_l3_s_hwmod,
2249 .slave = &am33xx_l4_ls_hwmod,
2251 .user = OCP_USER_MPU | OCP_USER_SDMA,
2254 /* l3 s -> l4 wkup */
2255 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_wkup = {
2256 .master = &am33xx_l3_s_hwmod,
2257 .slave = &am33xx_l4_wkup_hwmod,
2259 .user = OCP_USER_MPU | OCP_USER_SDMA,
2263 static struct omap_hwmod_ocp_if am33xx_l3_s__l4_fw = {
2264 .master = &am33xx_l3_s_hwmod,
2265 .slave = &am33xx_l4_fw_hwmod,
2267 .user = OCP_USER_MPU | OCP_USER_SDMA,
2270 /* l3 main -> l3 instr */
2271 static struct omap_hwmod_ocp_if am33xx_l3_main__l3_instr = {
2272 .master = &am33xx_l3_main_hwmod,
2273 .slave = &am33xx_l3_instr_hwmod,
2275 .user = OCP_USER_MPU | OCP_USER_SDMA,
2279 static struct omap_hwmod_ocp_if am33xx_mpu__prcm = {
2280 .master = &am33xx_mpu_hwmod,
2281 .slave = &am33xx_prcm_hwmod,
2282 .clk = "dpll_mpu_m2_ck",
2283 .user = OCP_USER_MPU | OCP_USER_SDMA,
2286 /* l3 s -> l3 main*/
2287 static struct omap_hwmod_ocp_if am33xx_l3_s__l3_main = {
2288 .master = &am33xx_l3_s_hwmod,
2289 .slave = &am33xx_l3_main_hwmod,
2291 .user = OCP_USER_MPU | OCP_USER_SDMA,
2294 /* pru-icss -> l3 main */
2295 static struct omap_hwmod_ocp_if am33xx_pruss__l3_main = {
2296 .master = &am33xx_pruss_hwmod,
2297 .slave = &am33xx_l3_main_hwmod,
2299 .user = OCP_USER_MPU | OCP_USER_SDMA,
2302 /* wkup m3 -> l4 wkup */
2303 static struct omap_hwmod_ocp_if am33xx_wkup_m3__l4_wkup = {
2304 .master = &am33xx_wkup_m3_hwmod,
2305 .slave = &am33xx_l4_wkup_hwmod,
2306 .clk = "dpll_core_m4_div2_ck",
2307 .user = OCP_USER_MPU | OCP_USER_SDMA,
2310 /* gfx -> l3 main */
2311 static struct omap_hwmod_ocp_if am33xx_gfx__l3_main = {
2312 .master = &am33xx_gfx_hwmod,
2313 .slave = &am33xx_l3_main_hwmod,
2314 .clk = "dpll_core_m4_ck",
2315 .user = OCP_USER_MPU | OCP_USER_SDMA,
2318 /* l4 wkup -> wkup m3 */
2319 static struct omap_hwmod_addr_space am33xx_wkup_m3_addrs[] = {
2322 .pa_start = 0x44d00000,
2323 .pa_end = 0x44d00000 + SZ_16K - 1,
2324 .flags = ADDR_TYPE_RT
2328 .pa_start = 0x44d80000,
2329 .pa_end = 0x44d80000 + SZ_8K - 1,
2330 .flags = ADDR_TYPE_RT
2335 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wkup_m3 = {
2336 .master = &am33xx_l4_wkup_hwmod,
2337 .slave = &am33xx_wkup_m3_hwmod,
2338 .clk = "dpll_core_m4_div2_ck",
2339 .addr = am33xx_wkup_m3_addrs,
2340 .user = OCP_USER_MPU | OCP_USER_SDMA,
2343 /* l4 hs -> pru-icss */
2344 static struct omap_hwmod_addr_space am33xx_pruss_addrs[] = {
2346 .pa_start = 0x4a300000,
2347 .pa_end = 0x4a300000 + SZ_512K - 1,
2348 .flags = ADDR_TYPE_RT
2353 static struct omap_hwmod_ocp_if am33xx_l4_hs__pruss = {
2354 .master = &am33xx_l4_hs_hwmod,
2355 .slave = &am33xx_pruss_hwmod,
2356 .clk = "dpll_core_m4_ck",
2357 .addr = am33xx_pruss_addrs,
2358 .user = OCP_USER_MPU | OCP_USER_SDMA,
2361 /* l3 main -> gfx */
2362 static struct omap_hwmod_addr_space am33xx_gfx_addrs[] = {
2364 .pa_start = 0x56000000,
2365 .pa_end = 0x56000000 + SZ_16M - 1,
2366 .flags = ADDR_TYPE_RT
2371 static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
2372 .master = &am33xx_l3_main_hwmod,
2373 .slave = &am33xx_gfx_hwmod,
2374 .clk = "dpll_core_m4_ck",
2375 .addr = am33xx_gfx_addrs,
2376 .user = OCP_USER_MPU | OCP_USER_SDMA,
2379 /* l4 wkup -> smartreflex0 */
2380 static struct omap_hwmod_addr_space am33xx_smartreflex0_addrs[] = {
2382 .pa_start = 0x44e37000,
2383 .pa_end = 0x44e37000 + SZ_4K - 1,
2384 .flags = ADDR_TYPE_RT
2389 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
2390 .master = &am33xx_l4_wkup_hwmod,
2391 .slave = &am33xx_smartreflex0_hwmod,
2392 .clk = "dpll_core_m4_div2_ck",
2393 .addr = am33xx_smartreflex0_addrs,
2394 .user = OCP_USER_MPU,
2397 /* l4 wkup -> smartreflex1 */
2398 static struct omap_hwmod_addr_space am33xx_smartreflex1_addrs[] = {
2400 .pa_start = 0x44e39000,
2401 .pa_end = 0x44e39000 + SZ_4K - 1,
2402 .flags = ADDR_TYPE_RT
2407 static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex1 = {
2408 .master = &am33xx_l4_wkup_hwmod,
2409 .slave = &am33xx_smartreflex1_hwmod,
2410 .clk = "dpll_core_m4_div2_ck",
2411 .addr = am33xx_smartreflex1_addrs,
2412 .user = OCP_USER_MPU,
2415 /* l4 wkup -> control */
2416 static struct omap_hwmod_addr_space am33xx_control_addrs[] = {
2418 .pa_start = 0x44e10000,
2419 .pa_end = 0x44e10000 + SZ_8K - 1,
2420 .flags = ADDR_TYPE_RT
2425 static struct omap_hwmod_ocp_if am33xx_l4_wkup__control = {
2426 .master = &am33xx_l4_wkup_hwmod,
2427 .slave = &am33xx_control_hwmod,
2428 .clk = "dpll_core_m4_div2_ck",
2429 .addr = am33xx_control_addrs,
2430 .user = OCP_USER_MPU,
2433 /* l4 wkup -> rtc */
2434 static struct omap_hwmod_addr_space am33xx_rtc_addrs[] = {
2436 .pa_start = 0x44e3e000,
2437 .pa_end = 0x44e3e000 + SZ_4K - 1,
2438 .flags = ADDR_TYPE_RT
2443 static struct omap_hwmod_ocp_if am33xx_l4_wkup__rtc = {
2444 .master = &am33xx_l4_wkup_hwmod,
2445 .slave = &am33xx_rtc_hwmod,
2446 .clk = "clkdiv32k_ick",
2447 .addr = am33xx_rtc_addrs,
2448 .user = OCP_USER_MPU,
2451 /* l4 per/ls -> DCAN0 */
2452 static struct omap_hwmod_addr_space am33xx_dcan0_addrs[] = {
2454 .pa_start = 0x481CC000,
2455 .pa_end = 0x481CC000 + SZ_4K - 1,
2456 .flags = ADDR_TYPE_RT
2461 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan0 = {
2462 .master = &am33xx_l4_ls_hwmod,
2463 .slave = &am33xx_dcan0_hwmod,
2465 .addr = am33xx_dcan0_addrs,
2466 .user = OCP_USER_MPU | OCP_USER_SDMA,
2469 /* l4 per/ls -> DCAN1 */
2470 static struct omap_hwmod_addr_space am33xx_dcan1_addrs[] = {
2472 .pa_start = 0x481D0000,
2473 .pa_end = 0x481D0000 + SZ_4K - 1,
2474 .flags = ADDR_TYPE_RT
2479 static struct omap_hwmod_ocp_if am33xx_l4_per__dcan1 = {
2480 .master = &am33xx_l4_ls_hwmod,
2481 .slave = &am33xx_dcan1_hwmod,
2483 .addr = am33xx_dcan1_addrs,
2484 .user = OCP_USER_MPU | OCP_USER_SDMA,
2487 /* l4 per/ls -> GPIO2 */
2488 static struct omap_hwmod_addr_space am33xx_gpio1_addrs[] = {
2490 .pa_start = 0x4804C000,
2491 .pa_end = 0x4804C000 + SZ_4K - 1,
2492 .flags = ADDR_TYPE_RT,
2497 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio1 = {
2498 .master = &am33xx_l4_ls_hwmod,
2499 .slave = &am33xx_gpio1_hwmod,
2501 .addr = am33xx_gpio1_addrs,
2502 .user = OCP_USER_MPU | OCP_USER_SDMA,
2505 /* l4 per/ls -> gpio3 */
2506 static struct omap_hwmod_addr_space am33xx_gpio2_addrs[] = {
2508 .pa_start = 0x481AC000,
2509 .pa_end = 0x481AC000 + SZ_4K - 1,
2510 .flags = ADDR_TYPE_RT,
2515 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio2 = {
2516 .master = &am33xx_l4_ls_hwmod,
2517 .slave = &am33xx_gpio2_hwmod,
2519 .addr = am33xx_gpio2_addrs,
2520 .user = OCP_USER_MPU | OCP_USER_SDMA,
2523 /* l4 per/ls -> gpio4 */
2524 static struct omap_hwmod_addr_space am33xx_gpio3_addrs[] = {
2526 .pa_start = 0x481AE000,
2527 .pa_end = 0x481AE000 + SZ_4K - 1,
2528 .flags = ADDR_TYPE_RT,
2533 static struct omap_hwmod_ocp_if am33xx_l4_per__gpio3 = {
2534 .master = &am33xx_l4_ls_hwmod,
2535 .slave = &am33xx_gpio3_hwmod,
2537 .addr = am33xx_gpio3_addrs,
2538 .user = OCP_USER_MPU | OCP_USER_SDMA,
2541 /* L4 WKUP -> I2C1 */
2542 static struct omap_hwmod_addr_space am33xx_i2c1_addr_space[] = {
2544 .pa_start = 0x44E0B000,
2545 .pa_end = 0x44E0B000 + SZ_4K - 1,
2546 .flags = ADDR_TYPE_RT,
2551 static struct omap_hwmod_ocp_if am33xx_l4_wkup__i2c1 = {
2552 .master = &am33xx_l4_wkup_hwmod,
2553 .slave = &am33xx_i2c1_hwmod,
2554 .clk = "dpll_core_m4_div2_ck",
2555 .addr = am33xx_i2c1_addr_space,
2556 .user = OCP_USER_MPU,
2559 /* L4 WKUP -> GPIO1 */
2560 static struct omap_hwmod_addr_space am33xx_gpio0_addrs[] = {
2562 .pa_start = 0x44E07000,
2563 .pa_end = 0x44E07000 + SZ_4K - 1,
2564 .flags = ADDR_TYPE_RT,
2569 static struct omap_hwmod_ocp_if am33xx_l4_wkup__gpio0 = {
2570 .master = &am33xx_l4_wkup_hwmod,
2571 .slave = &am33xx_gpio0_hwmod,
2572 .clk = "dpll_core_m4_div2_ck",
2573 .addr = am33xx_gpio0_addrs,
2574 .user = OCP_USER_MPU | OCP_USER_SDMA,
2577 /* L4 WKUP -> ADC_TSC */
2578 static struct omap_hwmod_addr_space am33xx_adc_tsc_addrs[] = {
2580 .pa_start = 0x44E0D000,
2581 .pa_end = 0x44E0D000 + SZ_8K - 1,
2582 .flags = ADDR_TYPE_RT
2587 static struct omap_hwmod_ocp_if am33xx_l4_wkup__adc_tsc = {
2588 .master = &am33xx_l4_wkup_hwmod,
2589 .slave = &am33xx_adc_tsc_hwmod,
2590 .clk = "dpll_core_m4_div2_ck",
2591 .addr = am33xx_adc_tsc_addrs,
2592 .user = OCP_USER_MPU,
2595 static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2598 .pa_start = 0x4a100000,
2599 .pa_end = 0x4a100000 + SZ_2K - 1,
2603 .pa_start = 0x4a101200,
2604 .pa_end = 0x4a101200 + SZ_256 - 1,
2605 .flags = ADDR_TYPE_RT,
2610 static struct omap_hwmod_ocp_if am33xx_l4_hs__cpgmac0 = {
2611 .master = &am33xx_l4_hs_hwmod,
2612 .slave = &am33xx_cpgmac0_hwmod,
2613 .clk = "cpsw_125mhz_gclk",
2614 .addr = am33xx_cpgmac0_addr_space,
2615 .user = OCP_USER_MPU,
2618 static struct omap_hwmod_addr_space am33xx_mdio_addr_space[] = {
2620 .pa_start = 0x4A101000,
2621 .pa_end = 0x4A101000 + SZ_256 - 1,
2626 static struct omap_hwmod_ocp_if am33xx_cpgmac0__mdio = {
2627 .master = &am33xx_cpgmac0_hwmod,
2628 .slave = &am33xx_mdio_hwmod,
2629 .addr = am33xx_mdio_addr_space,
2630 .user = OCP_USER_MPU,
2633 static struct omap_hwmod_addr_space am33xx_elm_addr_space[] = {
2635 .pa_start = 0x48080000,
2636 .pa_end = 0x48080000 + SZ_8K - 1,
2637 .flags = ADDR_TYPE_RT
2642 static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2643 .master = &am33xx_l4_ls_hwmod,
2644 .slave = &am33xx_elm_hwmod,
2646 .addr = am33xx_elm_addr_space,
2647 .user = OCP_USER_MPU,
2650 static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
2652 .pa_start = 0x48300000,
2653 .pa_end = 0x48300000 + SZ_16 - 1,
2654 .flags = ADDR_TYPE_RT
2659 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
2660 .master = &am33xx_l4_ls_hwmod,
2661 .slave = &am33xx_epwmss0_hwmod,
2663 .addr = am33xx_epwmss0_addr_space,
2664 .user = OCP_USER_MPU,
2667 static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2669 .pa_start = 0x48300100,
2670 .pa_end = 0x48300100 + SZ_128 - 1,
2675 static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
2676 .master = &am33xx_epwmss0_hwmod,
2677 .slave = &am33xx_ecap0_hwmod,
2679 .addr = am33xx_ecap0_addr_space,
2680 .user = OCP_USER_MPU,
2683 static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
2685 .pa_start = 0x48300180,
2686 .pa_end = 0x48300180 + SZ_128 - 1,
2691 static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
2692 .master = &am33xx_epwmss0_hwmod,
2693 .slave = &am33xx_eqep0_hwmod,
2695 .addr = am33xx_eqep0_addr_space,
2696 .user = OCP_USER_MPU,
2699 static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2701 .pa_start = 0x48300200,
2702 .pa_end = 0x48300200 + SZ_128 - 1,
2707 static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
2708 .master = &am33xx_epwmss0_hwmod,
2709 .slave = &am33xx_ehrpwm0_hwmod,
2711 .addr = am33xx_ehrpwm0_addr_space,
2712 .user = OCP_USER_MPU,
2716 static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
2718 .pa_start = 0x48302000,
2719 .pa_end = 0x48302000 + SZ_16 - 1,
2720 .flags = ADDR_TYPE_RT
2725 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
2726 .master = &am33xx_l4_ls_hwmod,
2727 .slave = &am33xx_epwmss1_hwmod,
2729 .addr = am33xx_epwmss1_addr_space,
2730 .user = OCP_USER_MPU,
2733 static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2735 .pa_start = 0x48302100,
2736 .pa_end = 0x48302100 + SZ_128 - 1,
2741 static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
2742 .master = &am33xx_epwmss1_hwmod,
2743 .slave = &am33xx_ecap1_hwmod,
2745 .addr = am33xx_ecap1_addr_space,
2746 .user = OCP_USER_MPU,
2749 static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
2751 .pa_start = 0x48302180,
2752 .pa_end = 0x48302180 + SZ_128 - 1,
2757 static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
2758 .master = &am33xx_epwmss1_hwmod,
2759 .slave = &am33xx_eqep1_hwmod,
2761 .addr = am33xx_eqep1_addr_space,
2762 .user = OCP_USER_MPU,
2765 static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2767 .pa_start = 0x48302200,
2768 .pa_end = 0x48302200 + SZ_128 - 1,
2773 static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2774 .master = &am33xx_epwmss1_hwmod,
2775 .slave = &am33xx_ehrpwm1_hwmod,
2777 .addr = am33xx_ehrpwm1_addr_space,
2778 .user = OCP_USER_MPU,
2781 static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
2783 .pa_start = 0x48304000,
2784 .pa_end = 0x48304000 + SZ_16 - 1,
2785 .flags = ADDR_TYPE_RT
2790 static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
2791 .master = &am33xx_l4_ls_hwmod,
2792 .slave = &am33xx_epwmss2_hwmod,
2794 .addr = am33xx_epwmss2_addr_space,
2795 .user = OCP_USER_MPU,
2798 static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2800 .pa_start = 0x48304100,
2801 .pa_end = 0x48304100 + SZ_128 - 1,
2806 static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2807 .master = &am33xx_epwmss2_hwmod,
2808 .slave = &am33xx_ecap2_hwmod,
2810 .addr = am33xx_ecap2_addr_space,
2811 .user = OCP_USER_MPU,
2814 static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
2816 .pa_start = 0x48304180,
2817 .pa_end = 0x48304180 + SZ_128 - 1,
2822 static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2823 .master = &am33xx_epwmss2_hwmod,
2824 .slave = &am33xx_eqep2_hwmod,
2826 .addr = am33xx_eqep2_addr_space,
2827 .user = OCP_USER_MPU,
2830 static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2832 .pa_start = 0x48304200,
2833 .pa_end = 0x48304200 + SZ_128 - 1,
2838 static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2839 .master = &am33xx_epwmss2_hwmod,
2840 .slave = &am33xx_ehrpwm2_hwmod,
2842 .addr = am33xx_ehrpwm2_addr_space,
2843 .user = OCP_USER_MPU,
2846 /* l3s cfg -> gpmc */
2847 static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2849 .pa_start = 0x50000000,
2850 .pa_end = 0x50000000 + SZ_8K - 1,
2851 .flags = ADDR_TYPE_RT,
2856 static struct omap_hwmod_ocp_if am33xx_l3_s__gpmc = {
2857 .master = &am33xx_l3_s_hwmod,
2858 .slave = &am33xx_gpmc_hwmod,
2860 .addr = am33xx_gpmc_addr_space,
2861 .user = OCP_USER_MPU,
2865 static struct omap_hwmod_addr_space am33xx_i2c2_addr_space[] = {
2867 .pa_start = 0x4802A000,
2868 .pa_end = 0x4802A000 + SZ_4K - 1,
2869 .flags = ADDR_TYPE_RT,
2874 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c2 = {
2875 .master = &am33xx_l4_ls_hwmod,
2876 .slave = &am33xx_i2c2_hwmod,
2878 .addr = am33xx_i2c2_addr_space,
2879 .user = OCP_USER_MPU,
2882 static struct omap_hwmod_addr_space am33xx_i2c3_addr_space[] = {
2884 .pa_start = 0x4819C000,
2885 .pa_end = 0x4819C000 + SZ_4K - 1,
2886 .flags = ADDR_TYPE_RT
2891 static struct omap_hwmod_ocp_if am33xx_l4_per__i2c3 = {
2892 .master = &am33xx_l4_ls_hwmod,
2893 .slave = &am33xx_i2c3_hwmod,
2895 .addr = am33xx_i2c3_addr_space,
2896 .user = OCP_USER_MPU,
2899 static struct omap_hwmod_addr_space am33xx_lcdc_addr_space[] = {
2901 .pa_start = 0x4830E000,
2902 .pa_end = 0x4830E000 + SZ_8K - 1,
2903 .flags = ADDR_TYPE_RT,
2908 static struct omap_hwmod_ocp_if am33xx_l3_main__lcdc = {
2909 .master = &am33xx_l3_main_hwmod,
2910 .slave = &am33xx_lcdc_hwmod,
2911 .clk = "dpll_core_m4_ck",
2912 .addr = am33xx_lcdc_addr_space,
2913 .user = OCP_USER_MPU,
2916 static struct omap_hwmod_addr_space am33xx_mailbox_addrs[] = {
2918 .pa_start = 0x480C8000,
2919 .pa_end = 0x480C8000 + (SZ_4K - 1),
2920 .flags = ADDR_TYPE_RT
2925 /* l4 ls -> mailbox */
2926 static struct omap_hwmod_ocp_if am33xx_l4_per__mailbox = {
2927 .master = &am33xx_l4_ls_hwmod,
2928 .slave = &am33xx_mailbox_hwmod,
2930 .addr = am33xx_mailbox_addrs,
2931 .user = OCP_USER_MPU,
2934 /* l4 ls -> spinlock */
2935 static struct omap_hwmod_addr_space am33xx_spinlock_addrs[] = {
2937 .pa_start = 0x480Ca000,
2938 .pa_end = 0x480Ca000 + SZ_4K - 1,
2939 .flags = ADDR_TYPE_RT
2944 static struct omap_hwmod_ocp_if am33xx_l4_ls__spinlock = {
2945 .master = &am33xx_l4_ls_hwmod,
2946 .slave = &am33xx_spinlock_hwmod,
2948 .addr = am33xx_spinlock_addrs,
2949 .user = OCP_USER_MPU,
2952 /* l4 ls -> mcasp0 */
2953 static struct omap_hwmod_addr_space am33xx_mcasp0_addr_space[] = {
2955 .pa_start = 0x48038000,
2956 .pa_end = 0x48038000 + SZ_8K - 1,
2957 .flags = ADDR_TYPE_RT
2962 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp0 = {
2963 .master = &am33xx_l4_ls_hwmod,
2964 .slave = &am33xx_mcasp0_hwmod,
2966 .addr = am33xx_mcasp0_addr_space,
2967 .user = OCP_USER_MPU,
2970 /* l3 s -> mcasp0 data */
2971 static struct omap_hwmod_addr_space am33xx_mcasp0_data_addr_space[] = {
2973 .pa_start = 0x46000000,
2974 .pa_end = 0x46000000 + SZ_4M - 1,
2975 .flags = ADDR_TYPE_RT
2980 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp0_data = {
2981 .master = &am33xx_l3_s_hwmod,
2982 .slave = &am33xx_mcasp0_hwmod,
2984 .addr = am33xx_mcasp0_data_addr_space,
2985 .user = OCP_USER_SDMA,
2988 /* l4 ls -> mcasp1 */
2989 static struct omap_hwmod_addr_space am33xx_mcasp1_addr_space[] = {
2991 .pa_start = 0x4803C000,
2992 .pa_end = 0x4803C000 + SZ_8K - 1,
2993 .flags = ADDR_TYPE_RT
2998 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcasp1 = {
2999 .master = &am33xx_l4_ls_hwmod,
3000 .slave = &am33xx_mcasp1_hwmod,
3002 .addr = am33xx_mcasp1_addr_space,
3003 .user = OCP_USER_MPU,
3006 /* l3 s -> mcasp1 data */
3007 static struct omap_hwmod_addr_space am33xx_mcasp1_data_addr_space[] = {
3009 .pa_start = 0x46400000,
3010 .pa_end = 0x46400000 + SZ_4M - 1,
3011 .flags = ADDR_TYPE_RT
3016 static struct omap_hwmod_ocp_if am33xx_l3_s__mcasp1_data = {
3017 .master = &am33xx_l3_s_hwmod,
3018 .slave = &am33xx_mcasp1_hwmod,
3020 .addr = am33xx_mcasp1_data_addr_space,
3021 .user = OCP_USER_SDMA,
3025 static struct omap_hwmod_addr_space am33xx_mmc0_addr_space[] = {
3027 .pa_start = 0x48060100,
3028 .pa_end = 0x48060100 + SZ_4K - 1,
3029 .flags = ADDR_TYPE_RT,
3034 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc0 = {
3035 .master = &am33xx_l4_ls_hwmod,
3036 .slave = &am33xx_mmc0_hwmod,
3038 .addr = am33xx_mmc0_addr_space,
3039 .user = OCP_USER_MPU,
3043 static struct omap_hwmod_addr_space am33xx_mmc1_addr_space[] = {
3045 .pa_start = 0x481d8100,
3046 .pa_end = 0x481d8100 + SZ_4K - 1,
3047 .flags = ADDR_TYPE_RT,
3052 static struct omap_hwmod_ocp_if am33xx_l4_ls__mmc1 = {
3053 .master = &am33xx_l4_ls_hwmod,
3054 .slave = &am33xx_mmc1_hwmod,
3056 .addr = am33xx_mmc1_addr_space,
3057 .user = OCP_USER_MPU,
3061 static struct omap_hwmod_addr_space am33xx_mmc2_addr_space[] = {
3063 .pa_start = 0x47810100,
3064 .pa_end = 0x47810100 + SZ_64K - 1,
3065 .flags = ADDR_TYPE_RT,
3070 static struct omap_hwmod_ocp_if am33xx_l3_s__mmc2 = {
3071 .master = &am33xx_l3_s_hwmod,
3072 .slave = &am33xx_mmc2_hwmod,
3074 .addr = am33xx_mmc2_addr_space,
3075 .user = OCP_USER_MPU,
3078 /* l4 ls -> mcspi0 */
3079 static struct omap_hwmod_addr_space am33xx_mcspi0_addr_space[] = {
3081 .pa_start = 0x48030000,
3082 .pa_end = 0x48030000 + SZ_1K - 1,
3083 .flags = ADDR_TYPE_RT,
3088 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi0 = {
3089 .master = &am33xx_l4_ls_hwmod,
3090 .slave = &am33xx_spi0_hwmod,
3092 .addr = am33xx_mcspi0_addr_space,
3093 .user = OCP_USER_MPU,
3096 /* l4 ls -> mcspi1 */
3097 static struct omap_hwmod_addr_space am33xx_mcspi1_addr_space[] = {
3099 .pa_start = 0x481A0000,
3100 .pa_end = 0x481A0000 + SZ_1K - 1,
3101 .flags = ADDR_TYPE_RT,
3106 static struct omap_hwmod_ocp_if am33xx_l4_ls__mcspi1 = {
3107 .master = &am33xx_l4_ls_hwmod,
3108 .slave = &am33xx_spi1_hwmod,
3110 .addr = am33xx_mcspi1_addr_space,
3111 .user = OCP_USER_MPU,
3114 /* l4 wkup -> timer1 */
3115 static struct omap_hwmod_addr_space am33xx_timer1_addr_space[] = {
3117 .pa_start = 0x44E31000,
3118 .pa_end = 0x44E31000 + SZ_1K - 1,
3119 .flags = ADDR_TYPE_RT
3124 static struct omap_hwmod_ocp_if am33xx_l4_wkup__timer1 = {
3125 .master = &am33xx_l4_wkup_hwmod,
3126 .slave = &am33xx_timer1_hwmod,
3127 .clk = "dpll_core_m4_div2_ck",
3128 .addr = am33xx_timer1_addr_space,
3129 .user = OCP_USER_MPU,
3132 /* l4 per -> timer2 */
3133 static struct omap_hwmod_addr_space am33xx_timer2_addr_space[] = {
3135 .pa_start = 0x48040000,
3136 .pa_end = 0x48040000 + SZ_1K - 1,
3137 .flags = ADDR_TYPE_RT
3142 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer2 = {
3143 .master = &am33xx_l4_ls_hwmod,
3144 .slave = &am33xx_timer2_hwmod,
3146 .addr = am33xx_timer2_addr_space,
3147 .user = OCP_USER_MPU,
3150 /* l4 per -> timer3 */
3151 static struct omap_hwmod_addr_space am33xx_timer3_addr_space[] = {
3153 .pa_start = 0x48042000,
3154 .pa_end = 0x48042000 + SZ_1K - 1,
3155 .flags = ADDR_TYPE_RT
3160 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer3 = {
3161 .master = &am33xx_l4_ls_hwmod,
3162 .slave = &am33xx_timer3_hwmod,
3164 .addr = am33xx_timer3_addr_space,
3165 .user = OCP_USER_MPU,
3168 /* l4 per -> timer4 */
3169 static struct omap_hwmod_addr_space am33xx_timer4_addr_space[] = {
3171 .pa_start = 0x48044000,
3172 .pa_end = 0x48044000 + SZ_1K - 1,
3173 .flags = ADDR_TYPE_RT
3178 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer4 = {
3179 .master = &am33xx_l4_ls_hwmod,
3180 .slave = &am33xx_timer4_hwmod,
3182 .addr = am33xx_timer4_addr_space,
3183 .user = OCP_USER_MPU,
3186 /* l4 per -> timer5 */
3187 static struct omap_hwmod_addr_space am33xx_timer5_addr_space[] = {
3189 .pa_start = 0x48046000,
3190 .pa_end = 0x48046000 + SZ_1K - 1,
3191 .flags = ADDR_TYPE_RT
3196 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer5 = {
3197 .master = &am33xx_l4_ls_hwmod,
3198 .slave = &am33xx_timer5_hwmod,
3200 .addr = am33xx_timer5_addr_space,
3201 .user = OCP_USER_MPU,
3204 /* l4 per -> timer6 */
3205 static struct omap_hwmod_addr_space am33xx_timer6_addr_space[] = {
3207 .pa_start = 0x48048000,
3208 .pa_end = 0x48048000 + SZ_1K - 1,
3209 .flags = ADDR_TYPE_RT
3214 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer6 = {
3215 .master = &am33xx_l4_ls_hwmod,
3216 .slave = &am33xx_timer6_hwmod,
3218 .addr = am33xx_timer6_addr_space,
3219 .user = OCP_USER_MPU,
3222 /* l4 per -> timer7 */
3223 static struct omap_hwmod_addr_space am33xx_timer7_addr_space[] = {
3225 .pa_start = 0x4804A000,
3226 .pa_end = 0x4804A000 + SZ_1K - 1,
3227 .flags = ADDR_TYPE_RT
3232 static struct omap_hwmod_ocp_if am33xx_l4_ls__timer7 = {
3233 .master = &am33xx_l4_ls_hwmod,
3234 .slave = &am33xx_timer7_hwmod,
3236 .addr = am33xx_timer7_addr_space,
3237 .user = OCP_USER_MPU,
3240 /* l3 main -> tpcc */
3241 static struct omap_hwmod_addr_space am33xx_tpcc_addr_space[] = {
3243 .pa_start = 0x49000000,
3244 .pa_end = 0x49000000 + SZ_32K - 1,
3245 .flags = ADDR_TYPE_RT
3250 static struct omap_hwmod_ocp_if am33xx_l3_main__tpcc = {
3251 .master = &am33xx_l3_main_hwmod,
3252 .slave = &am33xx_tpcc_hwmod,
3254 .addr = am33xx_tpcc_addr_space,
3255 .user = OCP_USER_MPU,
3258 /* l3 main -> tpcc0 */
3259 static struct omap_hwmod_addr_space am33xx_tptc0_addr_space[] = {
3261 .pa_start = 0x49800000,
3262 .pa_end = 0x49800000 + SZ_8K - 1,
3263 .flags = ADDR_TYPE_RT,
3268 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc0 = {
3269 .master = &am33xx_l3_main_hwmod,
3270 .slave = &am33xx_tptc0_hwmod,
3272 .addr = am33xx_tptc0_addr_space,
3273 .user = OCP_USER_MPU,
3276 /* l3 main -> tpcc1 */
3277 static struct omap_hwmod_addr_space am33xx_tptc1_addr_space[] = {
3279 .pa_start = 0x49900000,
3280 .pa_end = 0x49900000 + SZ_8K - 1,
3281 .flags = ADDR_TYPE_RT,
3286 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc1 = {
3287 .master = &am33xx_l3_main_hwmod,
3288 .slave = &am33xx_tptc1_hwmod,
3290 .addr = am33xx_tptc1_addr_space,
3291 .user = OCP_USER_MPU,
3294 /* l3 main -> tpcc2 */
3295 static struct omap_hwmod_addr_space am33xx_tptc2_addr_space[] = {
3297 .pa_start = 0x49a00000,
3298 .pa_end = 0x49a00000 + SZ_8K - 1,
3299 .flags = ADDR_TYPE_RT,
3304 static struct omap_hwmod_ocp_if am33xx_l3_main__tptc2 = {
3305 .master = &am33xx_l3_main_hwmod,
3306 .slave = &am33xx_tptc2_hwmod,
3308 .addr = am33xx_tptc2_addr_space,
3309 .user = OCP_USER_MPU,
3312 /* l4 wkup -> uart1 */
3313 static struct omap_hwmod_addr_space am33xx_uart1_addr_space[] = {
3315 .pa_start = 0x44E09000,
3316 .pa_end = 0x44E09000 + SZ_8K - 1,
3317 .flags = ADDR_TYPE_RT,
3322 static struct omap_hwmod_ocp_if am33xx_l4_wkup__uart1 = {
3323 .master = &am33xx_l4_wkup_hwmod,
3324 .slave = &am33xx_uart1_hwmod,
3325 .clk = "dpll_core_m4_div2_ck",
3326 .addr = am33xx_uart1_addr_space,
3327 .user = OCP_USER_MPU,
3330 /* l4 ls -> uart2 */
3331 static struct omap_hwmod_addr_space am33xx_uart2_addr_space[] = {
3333 .pa_start = 0x48022000,
3334 .pa_end = 0x48022000 + SZ_8K - 1,
3335 .flags = ADDR_TYPE_RT,
3340 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart2 = {
3341 .master = &am33xx_l4_ls_hwmod,
3342 .slave = &am33xx_uart2_hwmod,
3344 .addr = am33xx_uart2_addr_space,
3345 .user = OCP_USER_MPU,
3348 /* l4 ls -> uart3 */
3349 static struct omap_hwmod_addr_space am33xx_uart3_addr_space[] = {
3351 .pa_start = 0x48024000,
3352 .pa_end = 0x48024000 + SZ_8K - 1,
3353 .flags = ADDR_TYPE_RT,
3358 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart3 = {
3359 .master = &am33xx_l4_ls_hwmod,
3360 .slave = &am33xx_uart3_hwmod,
3362 .addr = am33xx_uart3_addr_space,
3363 .user = OCP_USER_MPU,
3366 /* l4 ls -> uart4 */
3367 static struct omap_hwmod_addr_space am33xx_uart4_addr_space[] = {
3369 .pa_start = 0x481A6000,
3370 .pa_end = 0x481A6000 + SZ_8K - 1,
3371 .flags = ADDR_TYPE_RT,
3376 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart4 = {
3377 .master = &am33xx_l4_ls_hwmod,
3378 .slave = &am33xx_uart4_hwmod,
3380 .addr = am33xx_uart4_addr_space,
3381 .user = OCP_USER_MPU,
3384 /* l4 ls -> uart5 */
3385 static struct omap_hwmod_addr_space am33xx_uart5_addr_space[] = {
3387 .pa_start = 0x481A8000,
3388 .pa_end = 0x481A8000 + SZ_8K - 1,
3389 .flags = ADDR_TYPE_RT,
3394 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart5 = {
3395 .master = &am33xx_l4_ls_hwmod,
3396 .slave = &am33xx_uart5_hwmod,
3398 .addr = am33xx_uart5_addr_space,
3399 .user = OCP_USER_MPU,
3402 /* l4 ls -> uart6 */
3403 static struct omap_hwmod_addr_space am33xx_uart6_addr_space[] = {
3405 .pa_start = 0x481aa000,
3406 .pa_end = 0x481aa000 + SZ_8K - 1,
3407 .flags = ADDR_TYPE_RT,
3412 static struct omap_hwmod_ocp_if am33xx_l4_ls__uart6 = {
3413 .master = &am33xx_l4_ls_hwmod,
3414 .slave = &am33xx_uart6_hwmod,
3416 .addr = am33xx_uart6_addr_space,
3417 .user = OCP_USER_MPU,
3420 /* l4 wkup -> wd_timer1 */
3421 static struct omap_hwmod_addr_space am33xx_wd_timer1_addrs[] = {
3423 .pa_start = 0x44e35000,
3424 .pa_end = 0x44e35000 + SZ_4K - 1,
3425 .flags = ADDR_TYPE_RT
3430 static struct omap_hwmod_ocp_if am33xx_l4_wkup__wd_timer1 = {
3431 .master = &am33xx_l4_wkup_hwmod,
3432 .slave = &am33xx_wd_timer1_hwmod,
3433 .clk = "dpll_core_m4_div2_ck",
3434 .addr = am33xx_wd_timer1_addrs,
3435 .user = OCP_USER_MPU,
3439 /* l3 s -> USBSS interface */
3440 static struct omap_hwmod_addr_space am33xx_usbss_addr_space[] = {
3443 .pa_start = 0x47400000,
3444 .pa_end = 0x47400000 + SZ_4K - 1,
3445 .flags = ADDR_TYPE_RT
3449 .pa_start = 0x47401000,
3450 .pa_end = 0x47401000 + SZ_2K - 1,
3451 .flags = ADDR_TYPE_RT
3455 .pa_start = 0x47401800,
3456 .pa_end = 0x47401800 + SZ_2K - 1,
3457 .flags = ADDR_TYPE_RT
3462 static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3463 .master = &am33xx_l3_s_hwmod,
3464 .slave = &am33xx_usbss_hwmod,
3466 .addr = am33xx_usbss_addr_space,
3467 .user = OCP_USER_MPU,
3468 .flags = OCPIF_SWSUP_IDLE,
3471 /* l3 main -> ocmc */
3472 static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
3473 .master = &am33xx_l3_main_hwmod,
3474 .slave = &am33xx_ocmcram_hwmod,
3475 .user = OCP_USER_MPU | OCP_USER_SDMA,
3478 /* l3 main -> sha0 HIB2 */
3479 static struct omap_hwmod_addr_space am33xx_sha0_addrs[] = {
3481 .pa_start = 0x53100000,
3482 .pa_end = 0x53100000 + SZ_512 - 1,
3483 .flags = ADDR_TYPE_RT
3488 static struct omap_hwmod_ocp_if am33xx_l3_main__sha0 = {
3489 .master = &am33xx_l3_main_hwmod,
3490 .slave = &am33xx_sha0_hwmod,
3492 .addr = am33xx_sha0_addrs,
3493 .user = OCP_USER_MPU | OCP_USER_SDMA,
3496 /* l3 main -> AES0 HIB2 */
3497 static struct omap_hwmod_addr_space am33xx_aes0_addrs[] = {
3499 .pa_start = 0x53500000,
3500 .pa_end = 0x53500000 + SZ_1M - 1,
3501 .flags = ADDR_TYPE_RT
3506 static struct omap_hwmod_ocp_if am33xx_l3_main__aes0 = {
3507 .master = &am33xx_l3_main_hwmod,
3508 .slave = &am33xx_aes0_hwmod,
3510 .addr = am33xx_aes0_addrs,
3511 .user = OCP_USER_MPU | OCP_USER_SDMA,
3514 static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3515 &am33xx_l4_fw__emif_fw,
3516 &am33xx_l3_main__emif,
3517 &am33xx_mpu__l3_main,
3519 &am33xx_l3_s__l4_ls,
3520 &am33xx_l3_s__l4_wkup,
3521 &am33xx_l3_s__l4_fw,
3522 &am33xx_l3_main__l4_hs,
3523 &am33xx_l3_main__l3_s,
3524 &am33xx_l3_main__l3_instr,
3525 &am33xx_l3_main__gfx,
3526 &am33xx_l3_s__l3_main,
3527 &am33xx_pruss__l3_main,
3528 &am33xx_wkup_m3__l4_wkup,
3529 &am33xx_gfx__l3_main,
3530 &am33xx_l4_wkup__wkup_m3,
3531 &am33xx_l4_wkup__control,
3532 &am33xx_l4_wkup__smartreflex0,
3533 &am33xx_l4_wkup__smartreflex1,
3534 &am33xx_l4_wkup__uart1,
3535 &am33xx_l4_wkup__timer1,
3536 &am33xx_l4_wkup__rtc,
3537 &am33xx_l4_wkup__i2c1,
3538 &am33xx_l4_wkup__gpio0,
3539 &am33xx_l4_wkup__adc_tsc,
3540 &am33xx_l4_wkup__wd_timer1,
3541 &am33xx_l4_hs__pruss,
3542 &am33xx_l4_per__dcan0,
3543 &am33xx_l4_per__dcan1,
3544 &am33xx_l4_per__gpio1,
3545 &am33xx_l4_per__gpio2,
3546 &am33xx_l4_per__gpio3,
3547 &am33xx_l4_per__i2c2,
3548 &am33xx_l4_per__i2c3,
3549 &am33xx_l4_per__mailbox,
3550 &am33xx_l4_ls__mcasp0,
3551 &am33xx_l3_s__mcasp0_data,
3552 &am33xx_l4_ls__mcasp1,
3553 &am33xx_l3_s__mcasp1_data,
3554 &am33xx_l4_ls__mmc0,
3555 &am33xx_l4_ls__mmc1,
3557 &am33xx_l4_ls__timer2,
3558 &am33xx_l4_ls__timer3,
3559 &am33xx_l4_ls__timer4,
3560 &am33xx_l4_ls__timer5,
3561 &am33xx_l4_ls__timer6,
3562 &am33xx_l4_ls__timer7,
3563 &am33xx_l3_main__tpcc,
3564 &am33xx_l4_ls__uart2,
3565 &am33xx_l4_ls__uart3,
3566 &am33xx_l4_ls__uart4,
3567 &am33xx_l4_ls__uart5,
3568 &am33xx_l4_ls__uart6,
3569 &am33xx_l4_ls__spinlock,
3571 &am33xx_l4_ls__epwmss0,
3572 &am33xx_epwmss0__ecap0,
3573 &am33xx_epwmss0__eqep0,
3574 &am33xx_epwmss0__ehrpwm0,
3575 &am33xx_l4_ls__epwmss1,
3576 &am33xx_epwmss1__ecap1,
3577 &am33xx_epwmss1__eqep1,
3578 &am33xx_epwmss1__ehrpwm1,
3579 &am33xx_l4_ls__epwmss2,
3580 &am33xx_epwmss2__ecap2,
3581 &am33xx_epwmss2__eqep2,
3582 &am33xx_epwmss2__ehrpwm2,
3584 &am33xx_l3_main__lcdc,
3585 &am33xx_l4_ls__mcspi0,
3586 &am33xx_l4_ls__mcspi1,
3587 &am33xx_l3_main__tptc0,
3588 &am33xx_l3_main__tptc1,
3589 &am33xx_l3_main__tptc2,
3590 &am33xx_l3_main__ocmc,
3591 &am33xx_l3_s__usbss,
3592 &am33xx_l4_hs__cpgmac0,
3593 &am33xx_cpgmac0__mdio,
3594 &am33xx_l3_main__sha0,
3595 &am33xx_l3_main__aes0,
3599 int __init am33xx_hwmod_init(void)
3602 return omap_hwmod_register_links(am33xx_hwmod_ocp_ifs);