1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
5 * Copyright (C) 2009-2011 Nokia Corporation
6 * Copyright (C) 2012 Texas Instruments, Inc.
9 * XXX handle crossbar/shared link difference for L3?
10 * XXX these should be marked initdata for multi-OMAP kernels
13 #include <linux/platform_data/i2c-omap.h>
14 #include <linux/platform_data/hsmmc-omap.h>
16 #include "omap_hwmod.h"
20 #include "omap_hwmod_common_data.h"
21 #include "prm-regbits-24xx.h"
22 #include "cm-regbits-24xx.h"
27 * OMAP2430 hardware module integration data
29 * All of the data in this section should be autogeneratable from the
30 * TI hardware database or other technical documentation. Data that
31 * is driver-specific or driver-kernel integration-specific belongs
40 static struct omap_hwmod_rst_info omap2430_iva_resets[] = {
41 { .name = "logic", .rst_shift = 0 },
42 { .name = "mmu", .rst_shift = 1 },
45 static struct omap_hwmod omap2430_iva_hwmod = {
47 .class = &iva_hwmod_class,
48 .clkdm_name = "dsp_clkdm",
49 .rst_lines = omap2430_iva_resets,
50 .rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets),
51 .main_clk = "dsp_fck",
55 static struct omap_hwmod_class_sysconfig i2c_sysc = {
59 .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
60 SYSS_HAS_RESET_STATUS),
61 .sysc_fields = &omap_hwmod_sysc_type1,
64 static struct omap_hwmod_class i2c_class = {
67 .reset = &omap_i2c_reset,
71 static struct omap_hwmod omap2430_i2c1_hwmod = {
73 .flags = HWMOD_16BIT_REG,
74 .main_clk = "i2chs1_fck",
78 * NOTE: The CM_FCLKEN* and CM_ICLKEN* for
79 * I2CHS IP's do not follow the usual pattern.
80 * prcm_reg_id alone cannot be used to program
81 * the iclk and fclk. Needs to be handled using
82 * additional flags when clk handling is moved
85 .module_offs = CORE_MOD,
87 .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
94 static struct omap_hwmod omap2430_i2c2_hwmod = {
96 .flags = HWMOD_16BIT_REG,
97 .main_clk = "i2chs2_fck",
100 .module_offs = CORE_MOD,
102 .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
109 static struct omap_hwmod omap2430_gpio5_hwmod = {
111 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
112 .main_clk = "gpio5_fck",
115 .module_offs = CORE_MOD,
117 .idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
120 .class = &omap2xxx_gpio_hwmod_class,
124 static struct omap_hwmod omap2430_mailbox_hwmod = {
126 .class = &omap2xxx_mailbox_hwmod_class,
127 .main_clk = "mailboxes_ick",
130 .module_offs = CORE_MOD,
132 .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
138 static struct omap_hwmod omap2430_mcspi3_hwmod = {
140 .main_clk = "mcspi3_fck",
143 .module_offs = CORE_MOD,
145 .idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
148 .class = &omap2xxx_mcspi_class,
152 static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = {
156 .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE|
157 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
159 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
160 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
161 .sysc_fields = &omap_hwmod_sysc_type1,
164 static struct omap_hwmod_class usbotg_class = {
166 .sysc = &omap2430_usbhsotg_sysc,
170 static struct omap_hwmod omap2430_usbhsotg_hwmod = {
171 .name = "usb_otg_hs",
172 .main_clk = "usbhs_ick",
175 .module_offs = CORE_MOD,
177 .idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
180 .class = &usbotg_class,
182 * Erratum ID: i479 idle_req / idle_ack mechanism potentially
183 * broken when autoidle is enabled
184 * workaround is to disable the autoidle bit at module level.
186 .flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE
187 | HWMOD_SWSUP_MSTANDBY,
192 * multi channel buffered serial port controller
195 static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
198 .sysc_flags = (SYSC_HAS_SOFTRESET),
199 .sysc_fields = &omap_hwmod_sysc_type1,
202 static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
204 .sysc = &omap2430_mcbsp_sysc,
207 static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
208 { .role = "pad_fck", .clk = "mcbsp_clks" },
209 { .role = "prcm_fck", .clk = "func_96m_ck" },
213 static struct omap_hwmod omap2430_mcbsp1_hwmod = {
215 .class = &omap2430_mcbsp_hwmod_class,
216 .main_clk = "mcbsp1_fck",
219 .module_offs = CORE_MOD,
221 .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
224 .opt_clks = mcbsp_opt_clks,
225 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
229 static struct omap_hwmod omap2430_mcbsp2_hwmod = {
231 .class = &omap2430_mcbsp_hwmod_class,
232 .main_clk = "mcbsp2_fck",
235 .module_offs = CORE_MOD,
237 .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
240 .opt_clks = mcbsp_opt_clks,
241 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
245 static struct omap_hwmod omap2430_mcbsp3_hwmod = {
247 .class = &omap2430_mcbsp_hwmod_class,
248 .main_clk = "mcbsp3_fck",
251 .module_offs = CORE_MOD,
253 .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
256 .opt_clks = mcbsp_opt_clks,
257 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
261 static struct omap_hwmod omap2430_mcbsp4_hwmod = {
263 .class = &omap2430_mcbsp_hwmod_class,
264 .main_clk = "mcbsp4_fck",
267 .module_offs = CORE_MOD,
269 .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
272 .opt_clks = mcbsp_opt_clks,
273 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
277 static struct omap_hwmod omap2430_mcbsp5_hwmod = {
279 .class = &omap2430_mcbsp_hwmod_class,
280 .main_clk = "mcbsp5_fck",
283 .module_offs = CORE_MOD,
285 .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
288 .opt_clks = mcbsp_opt_clks,
289 .opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks),
292 /* MMC/SD/SDIO common */
293 static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
297 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
298 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
299 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
300 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
301 .sysc_fields = &omap_hwmod_sysc_type1,
304 static struct omap_hwmod_class omap2430_mmc_class = {
306 .sysc = &omap2430_mmc_sysc,
310 static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
311 { .role = "dbck", .clk = "mmchsdb1_fck" },
314 static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
315 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
318 static struct omap_hwmod omap2430_mmc1_hwmod = {
320 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
321 .opt_clks = omap2430_mmc1_opt_clks,
322 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
323 .main_clk = "mmchs1_fck",
326 .module_offs = CORE_MOD,
328 .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
331 .dev_attr = &mmc1_dev_attr,
332 .class = &omap2430_mmc_class,
336 static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
337 { .role = "dbck", .clk = "mmchsdb2_fck" },
340 static struct omap_hwmod omap2430_mmc2_hwmod = {
342 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
343 .opt_clks = omap2430_mmc2_opt_clks,
344 .opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
345 .main_clk = "mmchs2_fck",
348 .module_offs = CORE_MOD,
350 .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
353 .class = &omap2430_mmc_class,
357 static struct omap_hwmod omap2430_hdq1w_hwmod = {
359 .main_clk = "hdq_fck",
362 .module_offs = CORE_MOD,
364 .idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
367 .class = &omap2_hdq1w_class,
374 /* L3 -> L4_CORE interface */
375 /* l3_core -> usbhsotg interface */
376 static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
377 .master = &omap2430_usbhsotg_hwmod,
378 .slave = &omap2xxx_l3_main_hwmod,
380 .user = OCP_USER_MPU,
383 /* L4 CORE -> I2C1 interface */
384 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
385 .master = &omap2xxx_l4_core_hwmod,
386 .slave = &omap2430_i2c1_hwmod,
388 .user = OCP_USER_MPU | OCP_USER_SDMA,
391 /* L4 CORE -> I2C2 interface */
392 static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
393 .master = &omap2xxx_l4_core_hwmod,
394 .slave = &omap2430_i2c2_hwmod,
396 .user = OCP_USER_MPU | OCP_USER_SDMA,
399 /* l4_core ->usbhsotg interface */
400 static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
401 .master = &omap2xxx_l4_core_hwmod,
402 .slave = &omap2430_usbhsotg_hwmod,
404 .user = OCP_USER_MPU,
407 /* L4 CORE -> MMC1 interface */
408 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
409 .master = &omap2xxx_l4_core_hwmod,
410 .slave = &omap2430_mmc1_hwmod,
412 .user = OCP_USER_MPU | OCP_USER_SDMA,
415 /* L4 CORE -> MMC2 interface */
416 static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
417 .master = &omap2xxx_l4_core_hwmod,
418 .slave = &omap2430_mmc2_hwmod,
420 .user = OCP_USER_MPU | OCP_USER_SDMA,
423 /* l4 core -> mcspi3 interface */
424 static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
425 .master = &omap2xxx_l4_core_hwmod,
426 .slave = &omap2430_mcspi3_hwmod,
428 .user = OCP_USER_MPU | OCP_USER_SDMA,
431 /* IVA2 <- L3 interface */
432 static struct omap_hwmod_ocp_if omap2430_l3__iva = {
433 .master = &omap2xxx_l3_main_hwmod,
434 .slave = &omap2430_iva_hwmod,
436 .user = OCP_USER_MPU | OCP_USER_SDMA,
439 /* l4_wkup -> wd_timer2 */
440 static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
441 .master = &omap2xxx_l4_wkup_hwmod,
442 .slave = &omap2xxx_wd_timer2_hwmod,
443 .clk = "mpu_wdt_ick",
444 .user = OCP_USER_MPU | OCP_USER_SDMA,
447 /* l4_wkup -> gpio1 */
448 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
449 .master = &omap2xxx_l4_wkup_hwmod,
450 .slave = &omap2xxx_gpio1_hwmod,
452 .user = OCP_USER_MPU | OCP_USER_SDMA,
455 /* l4_wkup -> gpio2 */
456 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
457 .master = &omap2xxx_l4_wkup_hwmod,
458 .slave = &omap2xxx_gpio2_hwmod,
460 .user = OCP_USER_MPU | OCP_USER_SDMA,
463 /* l4_wkup -> gpio3 */
464 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
465 .master = &omap2xxx_l4_wkup_hwmod,
466 .slave = &omap2xxx_gpio3_hwmod,
468 .user = OCP_USER_MPU | OCP_USER_SDMA,
471 /* l4_wkup -> gpio4 */
472 static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
473 .master = &omap2xxx_l4_wkup_hwmod,
474 .slave = &omap2xxx_gpio4_hwmod,
476 .user = OCP_USER_MPU | OCP_USER_SDMA,
479 /* l4_core -> gpio5 */
480 static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
481 .master = &omap2xxx_l4_core_hwmod,
482 .slave = &omap2430_gpio5_hwmod,
484 .user = OCP_USER_MPU | OCP_USER_SDMA,
487 /* l4_core -> mailbox */
488 static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
489 .master = &omap2xxx_l4_core_hwmod,
490 .slave = &omap2430_mailbox_hwmod,
491 .user = OCP_USER_MPU | OCP_USER_SDMA,
494 /* l4_core -> mcbsp1 */
495 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
496 .master = &omap2xxx_l4_core_hwmod,
497 .slave = &omap2430_mcbsp1_hwmod,
499 .user = OCP_USER_MPU | OCP_USER_SDMA,
502 /* l4_core -> mcbsp2 */
503 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
504 .master = &omap2xxx_l4_core_hwmod,
505 .slave = &omap2430_mcbsp2_hwmod,
507 .user = OCP_USER_MPU | OCP_USER_SDMA,
510 /* l4_core -> mcbsp3 */
511 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
512 .master = &omap2xxx_l4_core_hwmod,
513 .slave = &omap2430_mcbsp3_hwmod,
515 .user = OCP_USER_MPU | OCP_USER_SDMA,
518 /* l4_core -> mcbsp4 */
519 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
520 .master = &omap2xxx_l4_core_hwmod,
521 .slave = &omap2430_mcbsp4_hwmod,
523 .user = OCP_USER_MPU | OCP_USER_SDMA,
526 /* l4_core -> mcbsp5 */
527 static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
528 .master = &omap2xxx_l4_core_hwmod,
529 .slave = &omap2430_mcbsp5_hwmod,
531 .user = OCP_USER_MPU | OCP_USER_SDMA,
534 /* l4_core -> hdq1w */
535 static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = {
536 .master = &omap2xxx_l4_core_hwmod,
537 .slave = &omap2430_hdq1w_hwmod,
539 .user = OCP_USER_MPU | OCP_USER_SDMA,
540 .flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE,
543 static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
544 .master = &omap2xxx_l3_main_hwmod,
545 .slave = &omap2xxx_gpmc_hwmod,
547 .user = OCP_USER_MPU | OCP_USER_SDMA,
550 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
551 &omap2xxx_l3_main__l4_core,
552 &omap2xxx_mpu__l3_main,
554 &omap2430_usbhsotg__l3,
555 &omap2430_l4_core__i2c1,
556 &omap2430_l4_core__i2c2,
557 &omap2xxx_l4_core__l4_wkup,
558 &omap2_l4_core__uart1,
559 &omap2_l4_core__uart2,
560 &omap2_l4_core__uart3,
561 &omap2430_l4_core__usbhsotg,
562 &omap2430_l4_core__mmc1,
563 &omap2430_l4_core__mmc2,
564 &omap2xxx_l4_core__mcspi1,
565 &omap2xxx_l4_core__mcspi2,
566 &omap2430_l4_core__mcspi3,
568 &omap2xxx_l4_core__timer3,
569 &omap2xxx_l4_core__timer4,
570 &omap2xxx_l4_core__timer5,
571 &omap2xxx_l4_core__timer6,
572 &omap2xxx_l4_core__timer7,
573 &omap2xxx_l4_core__timer8,
574 &omap2xxx_l4_core__timer9,
575 &omap2xxx_l4_core__timer10,
576 &omap2xxx_l4_core__timer11,
577 &omap2xxx_l4_core__timer12,
578 &omap2430_l4_wkup__wd_timer2,
579 &omap2xxx_l4_core__dss,
580 &omap2xxx_l4_core__dss_dispc,
581 &omap2xxx_l4_core__dss_rfbi,
582 &omap2xxx_l4_core__dss_venc,
583 &omap2430_l4_wkup__gpio1,
584 &omap2430_l4_wkup__gpio2,
585 &omap2430_l4_wkup__gpio3,
586 &omap2430_l4_wkup__gpio4,
587 &omap2430_l4_core__gpio5,
588 &omap2430_l4_core__mailbox,
589 &omap2430_l4_core__mcbsp1,
590 &omap2430_l4_core__mcbsp2,
591 &omap2430_l4_core__mcbsp3,
592 &omap2430_l4_core__mcbsp4,
593 &omap2430_l4_core__mcbsp5,
594 &omap2430_l4_core__hdq1w,
595 &omap2xxx_l4_core__rng,
596 &omap2xxx_l4_core__sham,
597 &omap2xxx_l4_core__aes,
602 int __init omap2430_hwmod_init(void)
605 return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);