1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP4 specific common source file.
5 * Copyright (C) 2010 Texas Instruments, Inc.
7 * Santosh Shilimkar <santosh.shilimkar@ti.com>
10 #include <linux/kernel.h>
11 #include <linux/init.h>
13 #include <linux/irq.h>
14 #include <linux/irqchip.h>
15 #include <linux/platform_device.h>
16 #include <linux/memblock.h>
17 #include <linux/of_irq.h>
18 #include <linux/of_platform.h>
19 #include <linux/export.h>
20 #include <linux/irqchip/arm-gic.h>
21 #include <linux/of_address.h>
22 #include <linux/reboot.h>
23 #include <linux/genalloc.h>
25 #include <asm/hardware/cache-l2x0.h>
26 #include <asm/mach/map.h>
27 #include <asm/memblock.h>
28 #include <asm/smp_twd.h>
30 #include "omap-wakeupgen.h"
34 #include "prminst44xx.h"
35 #include "prcm_mpu44xx.h"
36 #include "omap4-sar-layout.h"
37 #include "omap-secure.h"
40 #ifdef CONFIG_CACHE_L2X0
41 static void __iomem *l2cache_base;
44 static void __iomem *sar_ram_base;
45 static void __iomem *gic_dist_base_addr;
46 static void __iomem *twd_base;
48 #define IRQ_LOCALTIMER 29
50 #ifdef CONFIG_OMAP_INTERCONNECT_BARRIER
52 /* Used to implement memory barrier on DRAM path */
53 #define OMAP4_DRAM_BARRIER_VA 0xfe600000
55 static void __iomem *dram_sync, *sram_sync;
56 static phys_addr_t dram_sync_paddr;
57 static u32 dram_sync_size;
60 * The OMAP4 bus structure contains asynchronous bridges which can buffer
61 * data writes from the MPU. These asynchronous bridges can be found on
62 * paths between the MPU to EMIF, and the MPU to L3 interconnects.
64 * We need to be careful about re-ordering which can happen as a result
65 * of different accesses being performed via different paths, and
66 * therefore different asynchronous bridges.
70 * OMAP4 interconnect barrier which is called for each mb() and wmb().
71 * This is to ensure that normal paths to DRAM (normal memory, cacheable
72 * accesses) are properly synchronised with writes to DMA coherent memory
73 * (normal memory, uncacheable) and device writes.
75 * The mb() and wmb() barriers only operate only on the MPU->MA->EMIF
76 * path, as we need to ensure that data is visible to other system
77 * masters prior to writes to those system masters being seen.
79 * Note: the SRAM path is not synchronised via mb() and wmb().
81 static void omap4_mb(void)
84 writel_relaxed(0, dram_sync);
88 * OMAP4 Errata i688 - asynchronous bridge corruption when entering WFI.
90 * If a data is stalled inside asynchronous bridge because of back
91 * pressure, it may be accepted multiple times, creating pointer
92 * misalignment that will corrupt next transfers on that data path until
93 * next reset of the system. No recovery procedure once the issue is hit,
94 * the path remains consistently broken.
96 * Async bridges can be found on paths between MPU to EMIF and MPU to L3
99 * This situation can happen only when the idle is initiated by a Master
100 * Request Disconnection (which is trigged by software when executing WFI
103 * The work-around for this errata needs all the initiators connected
104 * through an async bridge to ensure that data path is properly drained
105 * before issuing WFI. This condition will be met if one Strongly ordered
106 * access is performed to the target right before executing the WFI.
108 * In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained.
109 * IO barrier ensure that there is no synchronisation loss on initiators
110 * operating on both interconnect port simultaneously.
112 * This is a stronger version of the OMAP4 memory barrier below, and
113 * operates on both the MPU->MA->EMIF path but also the MPU->OCP path
114 * as well, and is necessary prior to executing a WFI.
116 void omap_interconnect_sync(void)
118 if (dram_sync && sram_sync) {
119 writel_relaxed(readl_relaxed(dram_sync), dram_sync);
120 writel_relaxed(readl_relaxed(sram_sync), sram_sync);
125 static int __init omap4_sram_init(void)
127 struct device_node *np;
128 struct gen_pool *sram_pool;
130 np = of_find_compatible_node(NULL, NULL, "ti,omap4-mpu");
132 pr_warn("%s:Unable to allocate sram needed to handle errata I688\n",
134 sram_pool = of_gen_pool_get(np, "sram", 0);
136 pr_warn("%s:Unable to get sram pool needed to handle errata I688\n",
139 sram_sync = (void *)gen_pool_alloc(sram_pool, PAGE_SIZE);
143 omap_arch_initcall(omap4_sram_init);
145 /* Steal one page physical memory for barrier implementation */
146 void __init omap_barrier_reserve_memblock(void)
148 dram_sync_size = ALIGN(PAGE_SIZE, SZ_1M);
149 dram_sync_paddr = arm_memblock_steal(dram_sync_size, SZ_1M);
152 void __init omap_barriers_init(void)
154 struct map_desc dram_io_desc[1];
156 dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
157 dram_io_desc[0].pfn = __phys_to_pfn(dram_sync_paddr);
158 dram_io_desc[0].length = dram_sync_size;
159 dram_io_desc[0].type = MT_MEMORY_RW_SO;
160 iotable_init(dram_io_desc, ARRAY_SIZE(dram_io_desc));
161 dram_sync = (void __iomem *) dram_io_desc[0].virtual;
163 pr_info("OMAP4: Map %pa to %p for dram barrier\n",
164 &dram_sync_paddr, dram_sync);
171 void gic_dist_disable(void)
173 if (gic_dist_base_addr)
174 writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
177 void gic_dist_enable(void)
179 if (gic_dist_base_addr)
180 writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
183 bool gic_dist_disabled(void)
185 return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
188 void gic_timer_retrigger(void)
190 u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
191 u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
192 u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
194 if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
196 * The local timer interrupt got lost while the distributor was
197 * disabled. Ack the pending interrupt, and retrigger it.
199 pr_warn("%s: lost localtimer interrupt\n", __func__);
200 writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
201 if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
202 writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
203 twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
204 writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
209 #ifdef CONFIG_CACHE_L2X0
211 void __iomem *omap4_get_l2cache_base(void)
216 void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
222 smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
226 smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
229 case L2X0_DEBUG_CTRL:
230 smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
233 case L310_PREFETCH_CTRL:
234 smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
237 case L310_POWER_CTRL:
238 pr_info_once("OMAP L2C310: ROM does not support power control setting\n");
242 WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
246 omap_smc1(smc_op, val);
249 int __init omap_l2_cache_init(void)
251 /* Static mapping, never released */
252 l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
253 if (WARN_ON(!l2cache_base))
259 void __iomem *omap4_get_sar_ram_base(void)
265 * SAR RAM used to save and restore the HW context in low power modes.
266 * Note that we need to initialize this very early for kexec. See
267 * omap4_mpuss_early_init().
269 void __init omap4_sar_ram_init(void)
271 unsigned long sar_base;
274 * To avoid code running on other OMAPs in
277 if (cpu_is_omap44xx())
278 sar_base = OMAP44XX_SAR_RAM_BASE;
279 else if (soc_is_omap54xx())
280 sar_base = OMAP54XX_SAR_RAM_BASE;
284 /* Static mapping, never released */
285 sar_ram_base = ioremap(sar_base, SZ_16K);
286 if (WARN_ON(!sar_ram_base))
290 static const struct of_device_id intc_match[] = {
291 { .compatible = "ti,omap4-wugen-mpu", },
292 { .compatible = "ti,omap5-wugen-mpu", },
296 static struct device_node *intc_node;
298 void __init omap_gic_of_init(void)
300 struct device_node *np;
302 intc_node = of_find_matching_node(NULL, intc_match);
303 if (WARN_ON(!intc_node)) {
304 pr_err("No WUGEN found in DT, system will misbehave.\n");
305 pr_err("UPDATE YOUR DEVICE TREE!\n");
308 /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
309 if (!cpu_is_omap446x())
310 goto skip_errata_init;
312 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
313 gic_dist_base_addr = of_iomap(np, 0);
314 WARN_ON(!gic_dist_base_addr);
316 np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
317 twd_base = of_iomap(np, 0);