1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP Secure API infrastructure.
5 * Copyright (C) 2011 Texas Instruments, Inc.
6 * Santosh Shilimkar <santosh.shilimkar@ti.com>
7 * Copyright (C) 2012 Ivaylo Dimitrov <freemangordon@abv.bg>
8 * Copyright (C) 2013 Pali Rohár <pali.rohar@gmail.com>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
14 #include <linux/memblock.h>
16 #include <asm/cacheflush.h>
17 #include <asm/memblock.h>
19 #include "omap-secure.h"
21 static phys_addr_t omap_secure_memblock_base;
24 * omap_sec_dispatcher: Routine to dispatch low power secure
26 * @idx: The HAL API index
27 * @flag: The flag indicating criticality of operation
28 * @nargs: Number of valid arguments out of four.
29 * @arg1, arg2, arg3 args4: Parameters passed to secure API
31 * Return the non-zero error value on failure.
33 u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
46 * Secure API needs physical address
47 * pointer for the parameters
50 outer_clean_range(__pa(param), __pa(param + 5));
51 ret = omap_smc2(idx, flag, __pa(param));
56 /* Allocate the memory to save secure ram */
57 int __init omap_secure_ram_reserve_memblock(void)
59 u32 size = OMAP_SECURE_RAM_STORAGE;
61 size = ALIGN(size, SECTION_SIZE);
62 omap_secure_memblock_base = arm_memblock_steal(size, SECTION_SIZE);
67 phys_addr_t omap_secure_ram_mempool_base(void)
69 return omap_secure_memblock_base;
72 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
73 u32 omap3_save_secure_ram(void __iomem *addr, int size)
78 if (size != OMAP3_SAVE_SECURE_RAM_SZ)
79 return OMAP3_SAVE_SECURE_RAM_SZ;
81 param[0] = 4; /* Number of arguments */
82 param[1] = __pa(addr); /* Physical address for saving */
87 ret = save_secure_ram_context(__pa(param));
94 * rx51_secure_dispatcher: Routine to dispatch secure PPA API calls
95 * @idx: The PPA API index
96 * @process: Process ID
97 * @flag: The flag indicating criticality of operation
98 * @nargs: Number of valid arguments out of four.
99 * @arg1, arg2, arg3 args4: Parameters passed to secure API
101 * Return the non-zero error value on failure.
103 * NOTE: rx51_secure_dispatcher differs from omap_secure_dispatcher because
104 * it calling omap_smc3() instead omap_smc2() and param[0] is nargs+1
106 u32 rx51_secure_dispatcher(u32 idx, u32 process, u32 flag, u32 nargs,
107 u32 arg1, u32 arg2, u32 arg3, u32 arg4)
112 param[0] = nargs+1; /* RX-51 needs number of arguments + 1 */
119 * Secure API needs physical address
120 * pointer for the parameters
125 outer_clean_range(__pa(param), __pa(param + 5));
126 ret = omap_smc3(idx, process, flag, __pa(param));
135 * rx51_secure_update_aux_cr: Routine to modify the contents of Auxiliary Control Register
136 * @set_bits: bits to set in ACR
137 * @clr_bits: bits to clear in ACR
139 * Return the non-zero error value on failure.
141 u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits)
146 asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r" (acr));
150 return rx51_secure_dispatcher(RX51_PPA_WRITE_ACR,
157 * rx51_secure_rng_call: Routine for HW random generator
159 u32 rx51_secure_rng_call(u32 ptr, u32 count, u32 flag)
161 return rx51_secure_dispatcher(RX51_PPA_HWRNG,
164 3, ptr, count, flag, 0);