arch/arm/mach-omap2/io.c

   1 /*
   2  * linux/arch/arm/mach-omap2/io.c
   3  *
   4  * OMAP2 I/O mapping code
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Copyright (C) 2007-2009 Texas Instruments
   8  *
   9  * Author:
  10  *      Juha Yrjola <juha.yrjola@nokia.com>
  11  *      Syed Khasim <x0khasim@ti.com>
  12  *
  13  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License version 2 as
  17  * published by the Free Software Foundation.
  18  */
  19 #include <linux/module.h>
  20 #include <linux/kernel.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23 #include <linux/clk.h>
  24
  25 #include <asm/tlb.h>
  26 #include <asm/mach/map.h>
  27
  28 #include <linux/omap-dma.h>
  29
  30 #include "omap_hwmod.h"
  31 #include "soc.h"
  32 #include "iomap.h"
  33 #include "voltage.h"
  34 #include "powerdomain.h"
  35 #include "clockdomain.h"
  36 #include "common.h"
  37 #include "clock.h"
  38 #include "clock2xxx.h"
  39 #include "clock3xxx.h"
  40 #include "clock44xx.h"
  41 #include "omap-pm.h"
  42 #include "sdrc.h"
  43 #include "control.h"
  44 #include "serial.h"
  45 #include "sram.h"
  46 #include "cm2xxx.h"
  47 #include "cm3xxx.h"
  48 #include "prm.h"
  49 #include "cm.h"
  50 #include "prcm_mpu44xx.h"
  51 #include "prminst44xx.h"
  52 #include "cminst44xx.h"
  53 #include "prm2xxx.h"
  54 #include "prm3xxx.h"
  55 #include "prm44xx.h"
  56 #include "opp2xxx.h"
  57
  58 /*
  59  * omap_clk_soc_init: points to a function that does the SoC-specific
  60  * clock initializations
  61  */
  62 static int (*omap_clk_soc_init)(void);
  63
  64 /*
  65  * The machine specific code may provide the extra mapping besides the
  66  * default mapping provided here.
  67  */
  68
  69 #if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
  70 static struct map_desc omap24xx_io_desc[] __initdata = {
  71         {
  72                 .virtual        = L3_24XX_VIRT,
  73                 .pfn            = __phys_to_pfn(L3_24XX_PHYS),
  74                 .length         = L3_24XX_SIZE,
  75                 .type           = MT_DEVICE
  76         },
  77         {
  78                 .virtual        = L4_24XX_VIRT,
  79                 .pfn            = __phys_to_pfn(L4_24XX_PHYS),
  80                 .length         = L4_24XX_SIZE,
  81                 .type           = MT_DEVICE
  82         },
  83 };
  84
  85 #ifdef CONFIG_SOC_OMAP2420
  86 static struct map_desc omap242x_io_desc[] __initdata = {
  87         {
  88                 .virtual        = DSP_MEM_2420_VIRT,
  89                 .pfn            = __phys_to_pfn(DSP_MEM_2420_PHYS),
  90                 .length         = DSP_MEM_2420_SIZE,
  91                 .type           = MT_DEVICE
  92         },
  93         {
  94                 .virtual        = DSP_IPI_2420_VIRT,
  95                 .pfn            = __phys_to_pfn(DSP_IPI_2420_PHYS),
  96                 .length         = DSP_IPI_2420_SIZE,
  97                 .type           = MT_DEVICE
  98         },
  99         {
 100                 .virtual        = DSP_MMU_2420_VIRT,
 101                 .pfn            = __phys_to_pfn(DSP_MMU_2420_PHYS),
 102                 .length         = DSP_MMU_2420_SIZE,
 103                 .type           = MT_DEVICE
 104         },
 105 };
 106
 107 #endif
 108
 109 #ifdef CONFIG_SOC_OMAP2430
 110 static struct map_desc omap243x_io_desc[] __initdata = {
 111         {
 112                 .virtual        = L4_WK_243X_VIRT,
 113                 .pfn            = __phys_to_pfn(L4_WK_243X_PHYS),
 114                 .length         = L4_WK_243X_SIZE,
 115                 .type           = MT_DEVICE
 116         },
 117         {
 118                 .virtual        = OMAP243X_GPMC_VIRT,
 119                 .pfn            = __phys_to_pfn(OMAP243X_GPMC_PHYS),
 120                 .length         = OMAP243X_GPMC_SIZE,
 121                 .type           = MT_DEVICE
 122         },
 123         {
 124                 .virtual        = OMAP243X_SDRC_VIRT,
 125                 .pfn            = __phys_to_pfn(OMAP243X_SDRC_PHYS),
 126                 .length         = OMAP243X_SDRC_SIZE,
 127                 .type           = MT_DEVICE
 128         },
 129         {
 130                 .virtual        = OMAP243X_SMS_VIRT,
 131                 .pfn            = __phys_to_pfn(OMAP243X_SMS_PHYS),
 132                 .length         = OMAP243X_SMS_SIZE,
 133                 .type           = MT_DEVICE
 134         },
 135 };
 136 #endif
 137 #endif
 138
 139 #ifdef  CONFIG_ARCH_OMAP3
 140 static struct map_desc omap34xx_io_desc[] __initdata = {
 141         {
 142                 .virtual        = L3_34XX_VIRT,
 143                 .pfn            = __phys_to_pfn(L3_34XX_PHYS),
 144                 .length         = L3_34XX_SIZE,
 145                 .type           = MT_DEVICE
 146         },
 147         {
 148                 .virtual        = L4_34XX_VIRT,
 149                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 150                 .length         = L4_34XX_SIZE,
 151                 .type           = MT_DEVICE
 152         },
 153         {
 154                 .virtual        = OMAP34XX_GPMC_VIRT,
 155                 .pfn            = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
 156                 .length         = OMAP34XX_GPMC_SIZE,
 157                 .type           = MT_DEVICE
 158         },
 159         {
 160                 .virtual        = OMAP343X_SMS_VIRT,
 161                 .pfn            = __phys_to_pfn(OMAP343X_SMS_PHYS),
 162                 .length         = OMAP343X_SMS_SIZE,
 163                 .type           = MT_DEVICE
 164         },
 165         {
 166                 .virtual        = OMAP343X_SDRC_VIRT,
 167                 .pfn            = __phys_to_pfn(OMAP343X_SDRC_PHYS),
 168                 .length         = OMAP343X_SDRC_SIZE,
 169                 .type           = MT_DEVICE
 170         },
 171         {
 172                 .virtual        = L4_PER_34XX_VIRT,
 173                 .pfn            = __phys_to_pfn(L4_PER_34XX_PHYS),
 174                 .length         = L4_PER_34XX_SIZE,
 175                 .type           = MT_DEVICE
 176         },
 177         {
 178                 .virtual        = L4_EMU_34XX_VIRT,
 179                 .pfn            = __phys_to_pfn(L4_EMU_34XX_PHYS),
 180                 .length         = L4_EMU_34XX_SIZE,
 181                 .type           = MT_DEVICE
 182         },
 183 };
 184 #endif
 185
 186 #ifdef CONFIG_SOC_TI81XX
 187 static struct map_desc omapti81xx_io_desc[] __initdata = {
 188         {
 189                 .virtual        = L4_34XX_VIRT,
 190                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 191                 .length         = L4_34XX_SIZE,
 192                 .type           = MT_DEVICE
 193         }
 194 };
 195 #endif
 196
 197 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 198 static struct map_desc omapam33xx_io_desc[] __initdata = {
 199         {
 200                 .virtual        = L4_34XX_VIRT,
 201                 .pfn            = __phys_to_pfn(L4_34XX_PHYS),
 202                 .length         = L4_34XX_SIZE,
 203                 .type           = MT_DEVICE
 204         },
 205         {
 206                 .virtual        = L4_WK_AM33XX_VIRT,
 207                 .pfn            = __phys_to_pfn(L4_WK_AM33XX_PHYS),
 208                 .length         = L4_WK_AM33XX_SIZE,
 209                 .type           = MT_DEVICE
 210         }
 211 };
 212 #endif
 213
 214 #ifdef  CONFIG_ARCH_OMAP4
 215 static struct map_desc omap44xx_io_desc[] __initdata = {
 216         {
 217                 .virtual        = L3_44XX_VIRT,
 218                 .pfn            = __phys_to_pfn(L3_44XX_PHYS),
 219                 .length         = L3_44XX_SIZE,
 220                 .type           = MT_DEVICE,
 221         },
 222         {
 223                 .virtual        = L4_44XX_VIRT,
 224                 .pfn            = __phys_to_pfn(L4_44XX_PHYS),
 225                 .length         = L4_44XX_SIZE,
 226                 .type           = MT_DEVICE,
 227         },
 228         {
 229                 .virtual        = L4_PER_44XX_VIRT,
 230                 .pfn            = __phys_to_pfn(L4_PER_44XX_PHYS),
 231                 .length         = L4_PER_44XX_SIZE,
 232                 .type           = MT_DEVICE,
 233         },
 234 #ifdef CONFIG_OMAP4_ERRATA_I688
 235         {
 236                 .virtual        = OMAP4_SRAM_VA,
 237                 .pfn            = __phys_to_pfn(OMAP4_SRAM_PA),
 238                 .length         = PAGE_SIZE,
 239                 .type           = MT_MEMORY_RW_SO,
 240         },
 241 #endif
 242
 243 };
 244 #endif
 245
 246 #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
 247 static struct map_desc omap54xx_io_desc[] __initdata = {
 248         {
 249                 .virtual        = L3_54XX_VIRT,
 250                 .pfn            = __phys_to_pfn(L3_54XX_PHYS),
 251                 .length         = L3_54XX_SIZE,
 252                 .type           = MT_DEVICE,
 253         },
 254         {
 255                 .virtual        = L4_54XX_VIRT,
 256                 .pfn            = __phys_to_pfn(L4_54XX_PHYS),
 257                 .length         = L4_54XX_SIZE,
 258                 .type           = MT_DEVICE,
 259         },
 260         {
 261                 .virtual        = L4_WK_54XX_VIRT,
 262                 .pfn            = __phys_to_pfn(L4_WK_54XX_PHYS),
 263                 .length         = L4_WK_54XX_SIZE,
 264                 .type           = MT_DEVICE,
 265         },
 266         {
 267                 .virtual        = L4_PER_54XX_VIRT,
 268                 .pfn            = __phys_to_pfn(L4_PER_54XX_PHYS),
 269                 .length         = L4_PER_54XX_SIZE,
 270                 .type           = MT_DEVICE,
 271         },
 272 #ifdef CONFIG_OMAP4_ERRATA_I688
 273         {
 274                 .virtual        = OMAP4_SRAM_VA,
 275                 .pfn            = __phys_to_pfn(OMAP4_SRAM_PA),
 276                 .length         = PAGE_SIZE,
 277                 .type           = MT_MEMORY_RW_SO,
 278         },
 279 #endif
 280 };
 281 #endif
 282
 283 #ifdef CONFIG_SOC_OMAP2420
 284 void __init omap242x_map_io(void)
 285 {
 286         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
 287         iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
 288 }
 289 #endif
 290
 291 #ifdef CONFIG_SOC_OMAP2430
 292 void __init omap243x_map_io(void)
 293 {
 294         iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
 295         iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
 296 }
 297 #endif
 298
 299 #ifdef CONFIG_ARCH_OMAP3
 300 void __init omap3_map_io(void)
 301 {
 302         iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
 303 }
 304 #endif
 305
 306 #ifdef CONFIG_SOC_TI81XX
 307 void __init ti81xx_map_io(void)
 308 {
 309         iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
 310 }
 311 #endif
 312
 313 #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
 314 void __init am33xx_map_io(void)
 315 {
 316         iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
 317 }
 318 #endif
 319
 320 #ifdef CONFIG_ARCH_OMAP4
 321 void __init omap4_map_io(void)
 322 {
 323         iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
 324         omap_barriers_init();
 325 }
 326 #endif
 327
 328 #if defined(CONFIG_SOC_OMAP5) ||  defined(CONFIG_SOC_DRA7XX)
 329 void __init omap5_map_io(void)
 330 {
 331         iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
 332         omap_barriers_init();
 333 }
 334 #endif
 335 /*
 336  * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
 337  *
 338  * Sets the CORE DPLL3 M2 divider to the same value that it's at
 339  * currently.  This has the effect of setting the SDRC SDRAM AC timing
 340  * registers to the values currently defined by the kernel.  Currently
 341  * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
 342  * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
 343  * or passes along the return value of clk_set_rate().
 344  */
 345 static int __init _omap2_init_reprogram_sdrc(void)
 346 {
 347         struct clk *dpll3_m2_ck;
 348         int v = -EINVAL;
 349         long rate;
 350
 351         if (!cpu_is_omap34xx())
 352                 return 0;
 353
 354         dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
 355         if (IS_ERR(dpll3_m2_ck))
 356                 return -EINVAL;
 357
 358         rate = clk_get_rate(dpll3_m2_ck);
 359         pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
 360         v = clk_set_rate(dpll3_m2_ck, rate);
 361         if (v)
 362                 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
 363
 364         clk_put(dpll3_m2_ck);
 365
 366         return v;
 367 }
 368
 369 static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
 370 {
 371         return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
 372 }
 373
 374 static void __init omap_hwmod_init_postsetup(void)
 375 {
 376         u8 postsetup_state;
 377
 378         /* Set the default postsetup state for all hwmods */
 379 #ifdef CONFIG_PM_RUNTIME
 380         postsetup_state = _HWMOD_STATE_IDLE;
 381 #else
 382         postsetup_state = _HWMOD_STATE_ENABLED;
 383 #endif
 384         omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
 385
 386         omap_pm_if_early_init();
 387 }
 388
 389 static void __init __maybe_unused omap_common_late_init(void)
 390 {
 391         omap_mux_late_init();
 392         omap2_common_pm_late_init();
 393         omap_soc_device_init();
 394 }
 395
 396 #ifdef CONFIG_SOC_OMAP2420
 397 void __init omap2420_init_early(void)
 398 {
 399         omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
 400         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
 401                                OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
 402         omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
 403                                   NULL);
 404         omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
 405         omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
 406         omap2xxx_check_revision();
 407         omap2xxx_prm_init();
 408         omap2xxx_cm_init();
 409         omap2xxx_voltagedomains_init();
 410         omap242x_powerdomains_init();
 411         omap242x_clockdomains_init();
 412         omap2420_hwmod_init();
 413         omap_hwmod_init_postsetup();
 414         if (of_have_populated_dt()) {
 415                 omap_clk_soc_init = omap2420_dt_clk_init;
 416                 rate_table = omap2420_rate_table;
 417         } else {
 418                 omap_clk_soc_init = omap2420_clk_init;
 419         }
 420 }
 421
 422 void __init omap2420_init_late(void)
 423 {
 424         omap_common_late_init();
 425         omap2_pm_init();
 426         omap2_clk_enable_autoidle_all();
 427 }
 428 #endif
 429
 430 #ifdef CONFIG_SOC_OMAP2430
 431 void __init omap2430_init_early(void)
 432 {
 433         omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
 434         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
 435                                OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
 436         omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
 437                                   NULL);
 438         omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
 439         omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
 440         omap2xxx_check_revision();
 441         omap2xxx_prm_init();
 442         omap2xxx_cm_init();
 443         omap2xxx_voltagedomains_init();
 444         omap243x_powerdomains_init();
 445         omap243x_clockdomains_init();
 446         omap2430_hwmod_init();
 447         omap_hwmod_init_postsetup();
 448         if (of_have_populated_dt()) {
 449                 omap_clk_soc_init = omap2430_dt_clk_init;
 450                 rate_table = omap2430_rate_table;
 451         } else {
 452                 omap_clk_soc_init = omap2430_clk_init;
 453         }
 454 }
 455
 456 void __init omap2430_init_late(void)
 457 {
 458         omap_common_late_init();
 459         omap2_pm_init();
 460         omap2_clk_enable_autoidle_all();
 461 }
 462 #endif
 463
 464 /*
 465  * Currently only board-omap3beagle.c should call this because of the
 466  * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
 467  */
 468 #ifdef CONFIG_ARCH_OMAP3
 469 void __init omap3_init_early(void)
 470 {
 471         omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
 472         omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
 473                                OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
 474         omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
 475                                   NULL);
 476         omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
 477         omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
 478         omap3xxx_check_revision();
 479         omap3xxx_check_features();
 480         omap3xxx_prm_init();
 481         omap3xxx_cm_init();
 482         omap3xxx_voltagedomains_init();
 483         omap3xxx_powerdomains_init();
 484         omap3xxx_clockdomains_init();
 485         omap3xxx_hwmod_init();
 486         omap_hwmod_init_postsetup();
 487         omap_clk_soc_init = omap3xxx_clk_init;
 488 }
 489
 490 void __init omap3430_init_early(void)
 491 {
 492         omap3_init_early();
 493         if (of_have_populated_dt())
 494                 omap_clk_soc_init = omap3430_dt_clk_init;
 495 }
 496
 497 void __init omap35xx_init_early(void)
 498 {
 499         omap3_init_early();
 500         if (of_have_populated_dt())
 501                 omap_clk_soc_init = omap3430_dt_clk_init;
 502 }
 503
 504 void __init omap3630_init_early(void)
 505 {
 506         omap3_init_early();
 507         if (of_have_populated_dt())
 508                 omap_clk_soc_init = omap3630_dt_clk_init;
 509 }
 510
 511 void __init am35xx_init_early(void)
 512 {
 513         omap3_init_early();
 514         if (of_have_populated_dt())
 515                 omap_clk_soc_init = am35xx_dt_clk_init;
 516 }
 517
 518 void __init ti81xx_init_early(void)
 519 {
 520         omap2_set_globals_tap(OMAP343X_CLASS,
 521                               OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
 522         omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
 523                                   NULL);
 524         omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
 525         omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
 526         omap3xxx_check_revision();
 527         ti81xx_check_features();
 528         omap3xxx_voltagedomains_init();
 529         omap3xxx_powerdomains_init();
 530         omap3xxx_clockdomains_init();
 531         omap3xxx_hwmod_init();
 532         omap_hwmod_init_postsetup();
 533         if (of_have_populated_dt())
 534                 omap_clk_soc_init = ti81xx_dt_clk_init;
 535         else
 536                 omap_clk_soc_init = omap3xxx_clk_init;
 537 }
 538
 539 void __init omap3_init_late(void)
 540 {
 541         omap_common_late_init();
 542         omap3_pm_init();
 543         omap2_clk_enable_autoidle_all();
 544 }
 545
 546 void __init omap3430_init_late(void)
 547 {
 548         omap_common_late_init();
 549         omap3_pm_init();
 550         omap2_clk_enable_autoidle_all();
 551 }
 552
 553 void __init omap35xx_init_late(void)
 554 {
 555         omap_common_late_init();
 556         omap3_pm_init();
 557         omap2_clk_enable_autoidle_all();
 558 }
 559
 560 void __init omap3630_init_late(void)
 561 {
 562         omap_common_late_init();
 563         omap3_pm_init();
 564         omap2_clk_enable_autoidle_all();
 565 }
 566
 567 void __init am35xx_init_late(void)
 568 {
 569         omap_common_late_init();
 570         omap3_pm_init();
 571         omap2_clk_enable_autoidle_all();
 572 }
 573
 574 void __init ti81xx_init_late(void)
 575 {
 576         omap_common_late_init();
 577         omap3_pm_init();
 578         omap2_clk_enable_autoidle_all();
 579 }
 580 #endif
 581
 582 #ifdef CONFIG_SOC_AM33XX
 583 void __init am33xx_init_early(void)
 584 {
 585         omap2_set_globals_tap(AM335X_CLASS,
 586                               AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
 587         omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
 588                                   NULL);
 589         omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
 590         omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
 591         omap3xxx_check_revision();
 592         am33xx_check_features();
 593         am33xx_powerdomains_init();
 594         am33xx_clockdomains_init();
 595         am33xx_hwmod_init();
 596         omap_hwmod_init_postsetup();
 597         omap_clk_soc_init = am33xx_dt_clk_init;
 598 }
 599
 600 void __init am33xx_init_late(void)
 601 {
 602         omap_common_late_init();
 603 }
 604 #endif
 605
 606 #ifdef CONFIG_SOC_AM43XX
 607 void __init am43xx_init_early(void)
 608 {
 609         omap2_set_globals_tap(AM335X_CLASS,
 610                               AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
 611         omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
 612                                   NULL);
 613         omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
 614         omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
 615         omap_prm_base_init();
 616         omap_cm_base_init();
 617         omap3xxx_check_revision();
 618         am33xx_check_features();
 619         am43xx_powerdomains_init();
 620         am43xx_clockdomains_init();
 621         am43xx_hwmod_init();
 622         omap_hwmod_init_postsetup();
 623         omap_l2_cache_init();
 624         omap_clk_soc_init = am43xx_dt_clk_init;
 625 }
 626
 627 void __init am43xx_init_late(void)
 628 {
 629         omap_common_late_init();
 630 }
 631 #endif
 632
 633 #ifdef CONFIG_ARCH_OMAP4
 634 void __init omap4430_init_early(void)
 635 {
 636         omap2_set_globals_tap(OMAP443X_CLASS,
 637                               OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
 638         omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
 639                                   OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
 640         omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
 641         omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
 642                              OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
 643         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
 644         omap_prm_base_init();
 645         omap_cm_base_init();
 646         omap4xxx_check_revision();
 647         omap4xxx_check_features();
 648         omap4_pm_init_early();
 649         omap44xx_prm_init();
 650         omap44xx_voltagedomains_init();
 651         omap44xx_powerdomains_init();
 652         omap44xx_clockdomains_init();
 653         omap44xx_hwmod_init();
 654         omap_hwmod_init_postsetup();
 655         omap_l2_cache_init();
 656         omap_clk_soc_init = omap4xxx_dt_clk_init;
 657 }
 658
 659 void __init omap4430_init_late(void)
 660 {
 661         omap_common_late_init();
 662         omap4_pm_init();
 663         omap2_clk_enable_autoidle_all();
 664 }
 665 #endif
 666
 667 #ifdef CONFIG_SOC_OMAP5
 668 void __init omap5_init_early(void)
 669 {
 670         omap2_set_globals_tap(OMAP54XX_CLASS,
 671                               OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
 672         omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
 673                                   OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
 674         omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
 675         omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
 676                              OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
 677         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 678         omap_prm_base_init();
 679         omap_cm_base_init();
 680         omap44xx_prm_init();
 681         omap5xxx_check_revision();
 682         omap54xx_voltagedomains_init();
 683         omap54xx_powerdomains_init();
 684         omap54xx_clockdomains_init();
 685         omap54xx_hwmod_init();
 686         omap_hwmod_init_postsetup();
 687         omap_clk_soc_init = omap5xxx_dt_clk_init;
 688 }
 689
 690 void __init omap5_init_late(void)
 691 {
 692         omap_common_late_init();
 693 }
 694 #endif
 695
 696 #ifdef CONFIG_SOC_DRA7XX
 697 void __init dra7xx_init_early(void)
 698 {
 699         omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
 700         omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
 701                                   OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
 702         omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
 703         omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
 704                              OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
 705         omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
 706         omap_prm_base_init();
 707         omap_cm_base_init();
 708         omap44xx_prm_init();
 709         dra7xxx_check_revision();
 710         dra7xx_powerdomains_init();
 711         dra7xx_clockdomains_init();
 712         dra7xx_hwmod_init();
 713         omap_hwmod_init_postsetup();
 714         omap_clk_soc_init = dra7xx_dt_clk_init;
 715 }
 716
 717 void __init dra7xx_init_late(void)
 718 {
 719         omap_common_late_init();
 720 }
 721 #endif
 722
 723
 724 void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
 725                                       struct omap_sdrc_params *sdrc_cs1)
 726 {
 727         omap_sram_init();
 728
 729         if (cpu_is_omap24xx() || omap3_has_sdrc()) {
 730                 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
 731                 _omap2_init_reprogram_sdrc();
 732         }
 733 }
 734
 735 int __init omap_clk_init(void)
 736 {
 737         int ret = 0;
 738
 739         if (!omap_clk_soc_init)
 740                 return 0;
 741
 742         ret = of_prcm_init();
 743         if (!ret)
 744                 ret = omap_clk_soc_init();
 745
 746         return ret;
 747 }