2 * OMAP4-specific DPLL control functions
4 * Copyright (C) 2011 Texas Instruments, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/errno.h>
14 #include <linux/clk.h>
16 #include <linux/bitops.h>
21 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
22 * can supported when using the DPLL low-power mode. Frequencies are
23 * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control,
24 * Status, and Low-Power Operation Mode".
26 #define OMAP4_DPLL_LP_FINT_MAX 1000000
27 #define OMAP4_DPLL_LP_FOUT_MAX 100000000
30 * Bitfield declarations
32 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
33 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
34 #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
36 /* Static rate multiplier for OMAP4 REGM4XEN clocks */
37 #define OMAP4430_REGM4XEN_MULT 4
39 /* Supported only on OMAP4 */
40 int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk)
45 if (!clk || !clk->clksel_reg)
48 mask = clk->flags & CLOCK_CLKOUTX2 ?
49 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
50 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
52 v = omap2_clk_readl(clk, clk->clksel_reg);
59 void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk)
64 if (!clk || !clk->clksel_reg)
67 mask = clk->flags & CLOCK_CLKOUTX2 ?
68 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
69 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
71 v = omap2_clk_readl(clk, clk->clksel_reg);
72 /* Clear the bit to allow gatectrl */
74 omap2_clk_writel(v, clk, clk->clksel_reg);
77 void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk)
82 if (!clk || !clk->clksel_reg)
85 mask = clk->flags & CLOCK_CLKOUTX2 ?
86 OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
87 OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
89 v = omap2_clk_readl(clk, clk->clksel_reg);
90 /* Set the bit to deny gatectrl */
92 omap2_clk_writel(v, clk, clk->clksel_reg);
95 const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = {
96 .allow_idle = omap4_dpllmx_allow_gatectrl,
97 .deny_idle = omap4_dpllmx_deny_gatectrl,
101 * omap4_dpll_lpmode_recalc - compute DPLL low-power setting
102 * @dd: pointer to the dpll data structure
104 * Calculates if low-power mode can be enabled based upon the last
105 * multiplier and divider values calculated. If low-power mode can be
106 * enabled, then the bit to enable low-power mode is stored in the
107 * last_rounded_lpmode variable. This implementation is based upon the
108 * criteria for enabling low-power mode as described in the OMAP4430/60
109 * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power
112 static void omap4_dpll_lpmode_recalc(struct dpll_data *dd)
116 fint = __clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1);
117 fout = fint * dd->last_rounded_m;
119 if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX))
120 dd->last_rounded_lpmode = 1;
122 dd->last_rounded_lpmode = 0;
126 * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit
127 * @clk: struct clk * of the DPLL to compute the rate for
129 * Compute the output rate for the OMAP4 DPLL represented by @clk.
130 * Takes the REGM4XEN bit into consideration, which is needed for the
131 * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers)
132 * upon success, or 0 upon error.
134 unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
135 unsigned long parent_rate)
137 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
140 struct dpll_data *dd;
142 if (!clk || !clk->dpll_data)
147 rate = omap2_get_dpll_rate(clk);
149 /* regm4xen adds a multiplier of 4 to DPLL calculations */
150 v = omap2_clk_readl(clk, dd->control_reg);
151 if (v & OMAP4430_DPLL_REGM4XEN_MASK)
152 rate *= OMAP4430_REGM4XEN_MULT;
158 * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit
159 * @clk: struct clk * of the DPLL to round a rate for
160 * @target_rate: the desired rate of the DPLL
162 * Compute the rate that would be programmed into the DPLL hardware
163 * for @clk if set_rate() were to be provided with the rate
164 * @target_rate. Takes the REGM4XEN bit into consideration, which is
165 * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before
166 * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
167 * ~0 if an error occurred in omap2_dpll_round_rate().
169 long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
170 unsigned long target_rate,
171 unsigned long *parent_rate)
173 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
174 struct dpll_data *dd;
177 if (!clk || !clk->dpll_data)
182 dd->last_rounded_m4xen = 0;
185 * First try to compute the DPLL configuration for
186 * target rate without using the 4X multiplier.
188 r = omap2_dpll_round_rate(hw, target_rate, NULL);
193 * If we did not find a valid DPLL configuration, try again, but
194 * this time see if using the 4X multiplier can help. Enabling the
195 * 4X multiplier is equivalent to dividing the target rate by 4.
197 r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT,
202 dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT;
203 dd->last_rounded_m4xen = 1;
206 omap4_dpll_lpmode_recalc(dd);
208 return dd->last_rounded_rate;
212 * omap4_dpll_regm4xen_determine_rate - determine rate for a DPLL
213 * @hw: pointer to the clock to determine rate for
214 * @rate: target rate for the DPLL
215 * @best_parent_rate: pointer for returning best parent rate
216 * @best_parent_clk: pointer for returning best parent clock
218 * Determines which DPLL mode to use for reaching a desired rate.
219 * Checks whether the DPLL shall be in bypass or locked mode, and if
220 * locked, calculates the M,N values for the DPLL via round-rate.
221 * Returns a positive clock rate with success, negative error value
224 long omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw, unsigned long rate,
225 unsigned long min_rate,
226 unsigned long max_rate,
227 unsigned long *best_parent_rate,
228 struct clk_hw **best_parent_clk)
230 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
231 struct dpll_data *dd;
240 if (__clk_get_rate(dd->clk_bypass) == rate &&
241 (dd->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
242 *best_parent_clk = __clk_get_hw(dd->clk_bypass);
244 rate = omap4_dpll_regm4xen_round_rate(hw, rate,
246 *best_parent_clk = __clk_get_hw(dd->clk_ref);
249 *best_parent_rate = rate;