2 * OMAP2plus display device setup / initialization.
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
5 * Senthilvadivu Guruswamy
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
13 * kind, whether express or implied; without even the implied warranty
14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
23 #include <linux/clk.h>
24 #include <linux/err.h>
25 #include <linux/delay.h>
27 #include <linux/of_platform.h>
28 #include <linux/slab.h>
29 #include <linux/mfd/syscon.h>
30 #include <linux/regmap.h>
32 #include <linux/platform_data/omapdss.h>
33 #include "omap_hwmod.h"
34 #include "omap_device.h"
43 #define DISPC_CONTROL 0x0040
44 #define DISPC_CONTROL2 0x0238
45 #define DISPC_CONTROL3 0x0848
46 #define DISPC_IRQSTATUS 0x0018
48 #define DSS_CONTROL 0x40
49 #define DSS_SDI_CONTROL 0x44
50 #define DSS_PLL_CONTROL 0x48
52 #define LCD_EN_MASK (0x1 << 0)
53 #define DIGIT_EN_MASK (0x1 << 1)
55 #define FRAMEDONE_IRQ_SHIFT 0
56 #define EVSYNC_EVEN_IRQ_SHIFT 2
57 #define EVSYNC_ODD_IRQ_SHIFT 3
58 #define FRAMEDONE2_IRQ_SHIFT 22
59 #define FRAMEDONE3_IRQ_SHIFT 30
60 #define FRAMEDONETV_IRQ_SHIFT 24
63 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
64 * reset before deciding that something has gone wrong
66 #define FRAMEDONE_IRQ_TIMEOUT 100
68 #if defined(CONFIG_FB_OMAP2)
69 static struct platform_device omap_display_device = {
73 .platform_data = NULL,
77 #define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
79 static struct regmap *omap4_dsi_mux_syscon;
81 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
83 u32 enable_mask, enable_shift;
84 u32 pipd_mask, pipd_shift;
88 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
89 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
90 pipd_mask = OMAP4_DSI1_PIPD_MASK;
91 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
92 } else if (dsi_id == 1) {
93 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
94 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
95 pipd_mask = OMAP4_DSI2_PIPD_MASK;
96 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
101 regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, ®);
106 reg |= (lanes << enable_shift) & enable_mask;
107 reg |= (lanes << pipd_shift) & pipd_mask;
109 regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
114 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
116 if (cpu_is_omap44xx())
117 return omap4_dsi_mux_pads(dsi_id, lane_mask);
122 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
124 if (cpu_is_omap44xx())
125 omap4_dsi_mux_pads(dsi_id, 0);
128 static enum omapdss_version __init omap_display_get_version(void)
130 if (cpu_is_omap24xx())
131 return OMAPDSS_VER_OMAP24xx;
132 else if (cpu_is_omap3630())
133 return OMAPDSS_VER_OMAP3630;
134 else if (cpu_is_omap34xx()) {
135 if (soc_is_am35xx()) {
136 return OMAPDSS_VER_AM35xx;
138 if (omap_rev() < OMAP3430_REV_ES3_0)
139 return OMAPDSS_VER_OMAP34xx_ES1;
141 return OMAPDSS_VER_OMAP34xx_ES3;
143 } else if (omap_rev() == OMAP4430_REV_ES1_0)
144 return OMAPDSS_VER_OMAP4430_ES1;
145 else if (omap_rev() == OMAP4430_REV_ES2_0 ||
146 omap_rev() == OMAP4430_REV_ES2_1 ||
147 omap_rev() == OMAP4430_REV_ES2_2)
148 return OMAPDSS_VER_OMAP4430_ES2;
149 else if (cpu_is_omap44xx())
150 return OMAPDSS_VER_OMAP4;
151 else if (soc_is_omap54xx())
152 return OMAPDSS_VER_OMAP5;
153 else if (soc_is_am43xx())
154 return OMAPDSS_VER_AM43xx;
155 else if (soc_is_dra7xx())
156 return OMAPDSS_VER_DRA7xx;
158 return OMAPDSS_VER_UNKNOWN;
161 static int __init omapdss_init_fbdev(void)
163 static struct omap_dss_board_info board_data = {
164 .dsi_enable_pads = omap_dsi_enable_pads,
165 .dsi_disable_pads = omap_dsi_disable_pads,
167 struct device_node *node;
170 board_data.version = omap_display_get_version();
171 if (board_data.version == OMAPDSS_VER_UNKNOWN) {
172 pr_err("DSS not supported on this SoC\n");
176 omap_display_device.dev.platform_data = &board_data;
178 r = platform_device_register(&omap_display_device);
180 pr_err("Unable to register omapdss device\n");
184 /* create vrfb device */
185 r = omap_init_vrfb();
187 pr_err("Unable to register omapvrfb device\n");
191 /* create FB device */
194 pr_err("Unable to register omapfb device\n");
198 /* create V4L2 display device */
199 r = omap_init_vout();
201 pr_err("Unable to register omap_vout device\n");
205 /* add DSI info for omap4 */
206 node = of_find_node_by_name(NULL, "omap4_padconf_global");
208 omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
213 static const char * const omapdss_compat_names[] __initconst = {
221 static struct device_node * __init omapdss_find_dss_of_node(void)
223 struct device_node *node;
226 for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
227 node = of_find_compatible_node(NULL, NULL,
228 omapdss_compat_names[i]);
236 static int __init omapdss_init_of(void)
239 struct device_node *node;
240 struct platform_device *pdev;
242 /* only create dss helper devices if dss is enabled in the .dts */
244 node = omapdss_find_dss_of_node();
248 if (!of_device_is_available(node))
251 pdev = of_find_device_by_node(node);
254 pr_err("Unable to find DSS platform device\n");
258 r = of_platform_populate(node, NULL, NULL, &pdev->dev);
260 pr_err("Unable to populate DSS submodule devices\n");
264 return omapdss_init_fbdev();
266 omap_device_initcall(omapdss_init_of);
267 #endif /* CONFIG_FB_OMAP2 */
269 static void dispc_disable_outputs(void)
272 bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
274 struct omap_dss_dispc_dev_attr *da;
275 struct omap_hwmod *oh;
277 oh = omap_hwmod_lookup("dss_dispc");
279 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
284 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
288 da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
290 /* store value of LCDENABLE and DIGITENABLE bits */
291 v = omap_hwmod_read(oh, DISPC_CONTROL);
292 lcd_en = v & LCD_EN_MASK;
293 digit_en = v & DIGIT_EN_MASK;
295 /* store value of LCDENABLE for LCD2 */
296 if (da->manager_count > 2) {
297 v = omap_hwmod_read(oh, DISPC_CONTROL2);
298 lcd2_en = v & LCD_EN_MASK;
301 /* store value of LCDENABLE for LCD3 */
302 if (da->manager_count > 3) {
303 v = omap_hwmod_read(oh, DISPC_CONTROL3);
304 lcd3_en = v & LCD_EN_MASK;
307 if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
308 return; /* no managers currently enabled */
311 * If any manager was enabled, we need to disable it before
312 * DSS clocks are disabled or DISPC module is reset
315 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
318 if (da->has_framedonetv_irq) {
319 irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
321 irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
322 1 << EVSYNC_ODD_IRQ_SHIFT;
327 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
329 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
332 * clear any previous FRAMEDONE, FRAMEDONETV,
333 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
335 omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
337 /* disable LCD and TV managers */
338 v = omap_hwmod_read(oh, DISPC_CONTROL);
339 v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
340 omap_hwmod_write(v, oh, DISPC_CONTROL);
342 /* disable LCD2 manager */
343 if (da->manager_count > 2) {
344 v = omap_hwmod_read(oh, DISPC_CONTROL2);
346 omap_hwmod_write(v, oh, DISPC_CONTROL2);
349 /* disable LCD3 manager */
350 if (da->manager_count > 3) {
351 v = omap_hwmod_read(oh, DISPC_CONTROL3);
353 omap_hwmod_write(v, oh, DISPC_CONTROL3);
357 while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
360 if (i > FRAMEDONE_IRQ_TIMEOUT) {
361 pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
368 int omap_dss_reset(struct omap_hwmod *oh)
370 struct omap_hwmod_opt_clk *oc;
374 if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
375 pr_err("dss_core: hwmod data doesn't contain reset data\n");
379 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
381 clk_prepare_enable(oc->_clk);
383 dispc_disable_outputs();
385 /* clear SDI registers */
386 if (cpu_is_omap3430()) {
387 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
388 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
392 * clear DSS_CONTROL register to switch DSS clock sources to
395 omap_hwmod_write(0x0, oh, DSS_CONTROL);
397 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
398 & SYSS_RESETDONE_MASK),
399 MAX_MODULE_SOFTRESET_WAIT, c);
401 if (c == MAX_MODULE_SOFTRESET_WAIT)
402 pr_warn("dss_core: waiting for reset to finish failed\n");
404 pr_debug("dss_core: softreset done\n");
406 for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
408 clk_disable_unprepare(oc->_clk);
410 r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;