arch/arm/mach-omap2/display.c

   1 /*
   2  * OMAP2plus display device setup / initialization.
   3  *
   4  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   5  *      Senthilvadivu Guruswamy
   6  *      Sumit Semwal
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/string.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/io.h>
  23 #include <linux/clk.h>
  24 #include <linux/err.h>
  25 #include <linux/delay.h>
  26
  27 #include <video/omapdss.h>
  28 #include <plat/omap_hwmod.h>
  29 #include <plat/omap_device.h>
  30 #include <plat/omap-pm.h>
  31 #include "common.h"
  32
  33 #include "iomap.h"
  34 #include "mux.h"
  35 #include "control.h"
  36 #include "display.h"
  37
  38 #define DISPC_CONTROL           0x0040
  39 #define DISPC_CONTROL2          0x0238
  40 #define DISPC_CONTROL3          0x0848
  41 #define DISPC_IRQSTATUS         0x0018
  42
  43 #define DSS_SYSCONFIG           0x10
  44 #define DSS_SYSSTATUS           0x14
  45 #define DSS_CONTROL             0x40
  46 #define DSS_SDI_CONTROL         0x44
  47 #define DSS_PLL_CONTROL         0x48
  48
  49 #define LCD_EN_MASK             (0x1 << 0)
  50 #define DIGIT_EN_MASK           (0x1 << 1)
  51
  52 #define FRAMEDONE_IRQ_SHIFT     0
  53 #define EVSYNC_EVEN_IRQ_SHIFT   2
  54 #define EVSYNC_ODD_IRQ_SHIFT    3
  55 #define FRAMEDONE2_IRQ_SHIFT    22
  56 #define FRAMEDONE3_IRQ_SHIFT    30
  57 #define FRAMEDONETV_IRQ_SHIFT   24
  58
  59 /*
  60  * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
  61  *     reset before deciding that something has gone wrong
  62  */
  63 #define FRAMEDONE_IRQ_TIMEOUT           100
  64
  65 static struct platform_device omap_display_device = {
  66         .name          = "omapdss",
  67         .id            = -1,
  68         .dev            = {
  69                 .platform_data = NULL,
  70         },
  71 };
  72
  73 struct omap_dss_hwmod_data {
  74         const char *oh_name;
  75         const char *dev_name;
  76         const int id;
  77 };
  78
  79 static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
  80         { "dss_core", "omapdss_dss", -1 },
  81         { "dss_dispc", "omapdss_dispc", -1 },
  82         { "dss_rfbi", "omapdss_rfbi", -1 },
  83         { "dss_venc", "omapdss_venc", -1 },
  84 };
  85
  86 static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
  87         { "dss_core", "omapdss_dss", -1 },
  88         { "dss_dispc", "omapdss_dispc", -1 },
  89         { "dss_rfbi", "omapdss_rfbi", -1 },
  90         { "dss_venc", "omapdss_venc", -1 },
  91         { "dss_dsi1", "omapdss_dsi", 0 },
  92 };
  93
  94 static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
  95         { "dss_core", "omapdss_dss", -1 },
  96         { "dss_dispc", "omapdss_dispc", -1 },
  97         { "dss_rfbi", "omapdss_rfbi", -1 },
  98         { "dss_venc", "omapdss_venc", -1 },
  99         { "dss_dsi1", "omapdss_dsi", 0 },
 100         { "dss_dsi2", "omapdss_dsi", 1 },
 101         { "dss_hdmi", "omapdss_hdmi", -1 },
 102 };
 103
 104 static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
 105 {
 106         u32 reg;
 107         u16 control_i2c_1;
 108
 109         omap_mux_init_signal("hdmi_cec",
 110                         OMAP_PIN_INPUT_PULLUP);
 111         omap_mux_init_signal("hdmi_ddc_scl",
 112                         OMAP_PIN_INPUT_PULLUP);
 113         omap_mux_init_signal("hdmi_ddc_sda",
 114                         OMAP_PIN_INPUT_PULLUP);
 115
 116         /*
 117          * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
 118          * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
 119          * internal pull up resistor.
 120          */
 121         if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
 122                 control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
 123                 reg = omap4_ctrl_pad_readl(control_i2c_1);
 124                 reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
 125                         OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
 126                         omap4_ctrl_pad_writel(reg, control_i2c_1);
 127         }
 128 }
 129
 130 static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
 131 {
 132         u32 enable_mask, enable_shift;
 133         u32 pipd_mask, pipd_shift;
 134         u32 reg;
 135
 136         if (dsi_id == 0) {
 137                 enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
 138                 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
 139                 pipd_mask = OMAP4_DSI1_PIPD_MASK;
 140                 pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
 141         } else if (dsi_id == 1) {
 142                 enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
 143                 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
 144                 pipd_mask = OMAP4_DSI2_PIPD_MASK;
 145                 pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
 146         } else {
 147                 return -ENODEV;
 148         }
 149
 150         reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
 151
 152         reg &= ~enable_mask;
 153         reg &= ~pipd_mask;
 154
 155         reg |= (lanes << enable_shift) & enable_mask;
 156         reg |= (lanes << pipd_shift) & pipd_mask;
 157
 158         omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY);
 159
 160         return 0;
 161 }
 162
 163 int __init omap_hdmi_init(enum omap_hdmi_flags flags)
 164 {
 165         if (cpu_is_omap44xx())
 166                 omap4_hdmi_mux_pads(flags);
 167
 168         return 0;
 169 }
 170
 171 static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
 172 {
 173         if (cpu_is_omap44xx())
 174                 return omap4_dsi_mux_pads(dsi_id, lane_mask);
 175
 176         return 0;
 177 }
 178
 179 static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
 180 {
 181         if (cpu_is_omap44xx())
 182                 omap4_dsi_mux_pads(dsi_id, 0);
 183 }
 184
 185 static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
 186 {
 187         return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
 188 }
 189
 190 static struct platform_device *create_dss_pdev(const char *pdev_name,
 191                 int pdev_id, const char *oh_name, void *pdata, int pdata_len,
 192                 struct platform_device *parent)
 193 {
 194         struct platform_device *pdev;
 195         struct omap_device *od;
 196         struct omap_hwmod *ohs[1];
 197         struct omap_hwmod *oh;
 198         int r;
 199
 200         oh = omap_hwmod_lookup(oh_name);
 201         if (!oh) {
 202                 pr_err("Could not look up %s\n", oh_name);
 203                 r = -ENODEV;
 204                 goto err;
 205         }
 206
 207         pdev = platform_device_alloc(pdev_name, pdev_id);
 208         if (!pdev) {
 209                 pr_err("Could not create pdev for %s\n", pdev_name);
 210                 r = -ENOMEM;
 211                 goto err;
 212         }
 213
 214         if (parent != NULL)
 215                 pdev->dev.parent = &parent->dev;
 216
 217         if (pdev->id != -1)
 218                 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
 219         else
 220                 dev_set_name(&pdev->dev, "%s", pdev->name);
 221
 222         ohs[0] = oh;
 223         od = omap_device_alloc(pdev, ohs, 1, NULL, 0);
 224         if (!od) {
 225                 pr_err("Could not alloc omap_device for %s\n", pdev_name);
 226                 r = -ENOMEM;
 227                 goto err;
 228         }
 229
 230         r = platform_device_add_data(pdev, pdata, pdata_len);
 231         if (r) {
 232                 pr_err("Could not set pdata for %s\n", pdev_name);
 233                 goto err;
 234         }
 235
 236         r = omap_device_register(pdev);
 237         if (r) {
 238                 pr_err("Could not register omap_device for %s\n", pdev_name);
 239                 goto err;
 240         }
 241
 242         return pdev;
 243
 244 err:
 245         return ERR_PTR(r);
 246 }
 247
 248 static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
 249                 int pdev_id, void *pdata, int pdata_len,
 250                 struct platform_device *parent)
 251 {
 252         struct platform_device *pdev;
 253         int r;
 254
 255         pdev = platform_device_alloc(pdev_name, pdev_id);
 256         if (!pdev) {
 257                 pr_err("Could not create pdev for %s\n", pdev_name);
 258                 r = -ENOMEM;
 259                 goto err;
 260         }
 261
 262         if (parent != NULL)
 263                 pdev->dev.parent = &parent->dev;
 264
 265         if (pdev->id != -1)
 266                 dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
 267         else
 268                 dev_set_name(&pdev->dev, "%s", pdev->name);
 269
 270         r = platform_device_add_data(pdev, pdata, pdata_len);
 271         if (r) {
 272                 pr_err("Could not set pdata for %s\n", pdev_name);
 273                 goto err;
 274         }
 275
 276         r = platform_device_add(pdev);
 277         if (r) {
 278                 pr_err("Could not register platform_device for %s\n", pdev_name);
 279                 goto err;
 280         }
 281
 282         return pdev;
 283
 284 err:
 285         return ERR_PTR(r);
 286 }
 287
 288 int __init omap_display_init(struct omap_dss_board_info *board_data)
 289 {
 290         int r = 0;
 291         struct platform_device *pdev;
 292         int i, oh_count;
 293         const struct omap_dss_hwmod_data *curr_dss_hwmod;
 294         struct platform_device *dss_pdev;
 295
 296         /* create omapdss device */
 297
 298         board_data->dsi_enable_pads = omap_dsi_enable_pads;
 299         board_data->dsi_disable_pads = omap_dsi_disable_pads;
 300         board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count;
 301         board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
 302
 303         omap_display_device.dev.platform_data = board_data;
 304
 305         r = platform_device_register(&omap_display_device);
 306         if (r < 0) {
 307                 pr_err("Unable to register omapdss device\n");
 308                 return r;
 309         }
 310
 311         /* create devices for dss hwmods */
 312
 313         if (cpu_is_omap24xx()) {
 314                 curr_dss_hwmod = omap2_dss_hwmod_data;
 315                 oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
 316         } else if (cpu_is_omap34xx()) {
 317                 curr_dss_hwmod = omap3_dss_hwmod_data;
 318                 oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
 319         } else {
 320                 curr_dss_hwmod = omap4_dss_hwmod_data;
 321                 oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
 322         }
 323
 324         /*
 325          * First create the pdev for dss_core, which is used as a parent device
 326          * by the other dss pdevs. Note: dss_core has to be the first item in
 327          * the hwmod list.
 328          */
 329         dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
 330                         curr_dss_hwmod[0].id,
 331                         curr_dss_hwmod[0].oh_name,
 332                         board_data, sizeof(*board_data),
 333                         NULL);
 334
 335         if (IS_ERR(dss_pdev)) {
 336                 pr_err("Could not build omap_device for %s\n",
 337                                 curr_dss_hwmod[0].oh_name);
 338
 339                 return PTR_ERR(dss_pdev);
 340         }
 341
 342         for (i = 1; i < oh_count; i++) {
 343                 pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
 344                                 curr_dss_hwmod[i].id,
 345                                 curr_dss_hwmod[i].oh_name,
 346                                 board_data, sizeof(*board_data),
 347                                 dss_pdev);
 348
 349                 if (IS_ERR(pdev)) {
 350                         pr_err("Could not build omap_device for %s\n",
 351                                         curr_dss_hwmod[i].oh_name);
 352
 353                         return PTR_ERR(pdev);
 354                 }
 355         }
 356
 357         /* Create devices for DPI and SDI */
 358
 359         pdev = create_simple_dss_pdev("omapdss_dpi", -1,
 360                         board_data, sizeof(*board_data), dss_pdev);
 361         if (IS_ERR(pdev)) {
 362                 pr_err("Could not build platform_device for omapdss_dpi\n");
 363                 return PTR_ERR(pdev);
 364         }
 365
 366         if (cpu_is_omap34xx()) {
 367                 pdev = create_simple_dss_pdev("omapdss_sdi", -1,
 368                                 board_data, sizeof(*board_data), dss_pdev);
 369                 if (IS_ERR(pdev)) {
 370                         pr_err("Could not build platform_device for omapdss_sdi\n");
 371                         return PTR_ERR(pdev);
 372                 }
 373         }
 374
 375         return 0;
 376 }
 377
 378 static void dispc_disable_outputs(void)
 379 {
 380         u32 v, irq_mask = 0;
 381         bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
 382         int i;
 383         struct omap_dss_dispc_dev_attr *da;
 384         struct omap_hwmod *oh;
 385
 386         oh = omap_hwmod_lookup("dss_dispc");
 387         if (!oh) {
 388                 WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
 389                 return;
 390         }
 391
 392         if (!oh->dev_attr) {
 393                 pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
 394                 return;
 395         }
 396
 397         da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
 398
 399         /* store value of LCDENABLE and DIGITENABLE bits */
 400         v = omap_hwmod_read(oh, DISPC_CONTROL);
 401         lcd_en = v & LCD_EN_MASK;
 402         digit_en = v & DIGIT_EN_MASK;
 403
 404         /* store value of LCDENABLE for LCD2 */
 405         if (da->manager_count > 2) {
 406                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
 407                 lcd2_en = v & LCD_EN_MASK;
 408         }
 409
 410         /* store value of LCDENABLE for LCD3 */
 411         if (da->manager_count > 3) {
 412                 v = omap_hwmod_read(oh, DISPC_CONTROL3);
 413                 lcd3_en = v & LCD_EN_MASK;
 414         }
 415
 416         if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
 417                 return; /* no managers currently enabled */
 418
 419         /*
 420          * If any manager was enabled, we need to disable it before
 421          * DSS clocks are disabled or DISPC module is reset
 422          */
 423         if (lcd_en)
 424                 irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;
 425
 426         if (digit_en) {
 427                 if (da->has_framedonetv_irq) {
 428                         irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
 429                 } else {
 430                         irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
 431                                 1 << EVSYNC_ODD_IRQ_SHIFT;
 432                 }
 433         }
 434
 435         if (lcd2_en)
 436                 irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
 437         if (lcd3_en)
 438                 irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;
 439
 440         /*
 441          * clear any previous FRAMEDONE, FRAMEDONETV,
 442          * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
 443          */
 444         omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
 445
 446         /* disable LCD and TV managers */
 447         v = omap_hwmod_read(oh, DISPC_CONTROL);
 448         v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
 449         omap_hwmod_write(v, oh, DISPC_CONTROL);
 450
 451         /* disable LCD2 manager */
 452         if (da->manager_count > 2) {
 453                 v = omap_hwmod_read(oh, DISPC_CONTROL2);
 454                 v &= ~LCD_EN_MASK;
 455                 omap_hwmod_write(v, oh, DISPC_CONTROL2);
 456         }
 457
 458         /* disable LCD3 manager */
 459         if (da->manager_count > 3) {
 460                 v = omap_hwmod_read(oh, DISPC_CONTROL3);
 461                 v &= ~LCD_EN_MASK;
 462                 omap_hwmod_write(v, oh, DISPC_CONTROL3);
 463         }
 464
 465         i = 0;
 466         while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
 467                irq_mask) {
 468                 i++;
 469                 if (i > FRAMEDONE_IRQ_TIMEOUT) {
 470                         pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
 471                         break;
 472                 }
 473                 mdelay(1);
 474         }
 475 }
 476
 477 #define MAX_MODULE_SOFTRESET_WAIT       10000
 478 int omap_dss_reset(struct omap_hwmod *oh)
 479 {
 480         struct omap_hwmod_opt_clk *oc;
 481         int c = 0;
 482         int i, r;
 483
 484         if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
 485                 pr_err("dss_core: hwmod data doesn't contain reset data\n");
 486                 return -EINVAL;
 487         }
 488
 489         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 490                 if (oc->_clk)
 491                         clk_prepare_enable(oc->_clk);
 492
 493         dispc_disable_outputs();
 494
 495         /* clear SDI registers */
 496         if (cpu_is_omap3430()) {
 497                 omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
 498                 omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
 499         }
 500
 501         /*
 502          * clear DSS_CONTROL register to switch DSS clock sources to
 503          * PRCM clock, if any
 504          */
 505         omap_hwmod_write(0x0, oh, DSS_CONTROL);
 506
 507         omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
 508                                 & SYSS_RESETDONE_MASK),
 509                         MAX_MODULE_SOFTRESET_WAIT, c);
 510
 511         if (c == MAX_MODULE_SOFTRESET_WAIT)
 512                 pr_warning("dss_core: waiting for reset to finish failed\n");
 513         else
 514                 pr_debug("dss_core: softreset done\n");
 515
 516         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
 517                 if (oc->_clk)
 518                         clk_disable_unprepare(oc->_clk);
 519
 520         r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
 521
 522         return r;
 523 }