arch/arm/mach-omap2/cpuidle44xx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * OMAP4+ CPU idle Routines
   4  *
   5  * Copyright (C) 2011-2013 Texas Instruments, Inc.
   6  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   7  * Rajendra Nayak <rnayak@ti.com>
   8  */
   9
  10 #include <linux/sched.h>
  11 #include <linux/cpuidle.h>
  12 #include <linux/cpu_pm.h>
  13 #include <linux/export.h>
  14 #include <linux/tick.h>
  15
  16 #include <asm/cpuidle.h>
  17
  18 #include "common.h"
  19 #include "pm.h"
  20 #include "prm.h"
  21 #include "soc.h"
  22 #include "clockdomain.h"
  23
  24 #define MAX_CPUS        2
  25
  26 /* Machine specific information */
  27 struct idle_statedata {
  28         u32 cpu_state;
  29         u32 mpu_logic_state;
  30         u32 mpu_state;
  31         u32 mpu_state_vote;
  32 };
  33
  34 static struct idle_statedata omap4_idle_data[] = {
  35         {
  36                 .cpu_state = PWRDM_POWER_ON,
  37                 .mpu_state = PWRDM_POWER_ON,
  38                 .mpu_logic_state = PWRDM_POWER_RET,
  39         },
  40         {
  41                 .cpu_state = PWRDM_POWER_OFF,
  42                 .mpu_state = PWRDM_POWER_RET,
  43                 .mpu_logic_state = PWRDM_POWER_RET,
  44         },
  45         {
  46                 .cpu_state = PWRDM_POWER_OFF,
  47                 .mpu_state = PWRDM_POWER_RET,
  48                 .mpu_logic_state = PWRDM_POWER_OFF,
  49         },
  50 };
  51
  52 static struct idle_statedata omap5_idle_data[] = {
  53         {
  54                 .cpu_state = PWRDM_POWER_ON,
  55                 .mpu_state = PWRDM_POWER_ON,
  56                 .mpu_logic_state = PWRDM_POWER_ON,
  57         },
  58         {
  59                 .cpu_state = PWRDM_POWER_RET,
  60                 .mpu_state = PWRDM_POWER_RET,
  61                 .mpu_logic_state = PWRDM_POWER_RET,
  62         },
  63 };
  64
  65 static struct powerdomain *mpu_pd, *cpu_pd[MAX_CPUS];
  66 static struct clockdomain *cpu_clkdm[MAX_CPUS];
  67
  68 static atomic_t abort_barrier;
  69 static bool cpu_done[MAX_CPUS];
  70 static struct idle_statedata *state_ptr = &omap4_idle_data[0];
  71 static DEFINE_RAW_SPINLOCK(mpu_lock);
  72
  73 /* Private functions */
  74
  75 /**
  76  * omap_enter_idle_[simple/coupled] - OMAP4PLUS cpuidle entry functions
  77  * @dev: cpuidle device
  78  * @drv: cpuidle driver
  79  * @index: the index of state to be entered
  80  *
  81  * Called from the CPUidle framework to program the device to the
  82  * specified low power state selected by the governor.
  83  * Returns the amount of time spent in the low power state.
  84  */
  85 static int omap_enter_idle_simple(struct cpuidle_device *dev,
  86                         struct cpuidle_driver *drv,
  87                         int index)
  88 {
  89         omap_do_wfi();
  90         return index;
  91 }
  92
  93 static int omap_enter_idle_smp(struct cpuidle_device *dev,
  94                                struct cpuidle_driver *drv,
  95                                int index)
  96 {
  97         struct idle_statedata *cx = state_ptr + index;
  98         unsigned long flag;
  99
 100         raw_spin_lock_irqsave(&mpu_lock, flag);
 101         cx->mpu_state_vote++;
 102         if (cx->mpu_state_vote == num_online_cpus()) {
 103                 pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
 104                 omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
 105         }
 106         raw_spin_unlock_irqrestore(&mpu_lock, flag);
 107
 108         omap4_enter_lowpower(dev->cpu, cx->cpu_state);
 109
 110         raw_spin_lock_irqsave(&mpu_lock, flag);
 111         if (cx->mpu_state_vote == num_online_cpus())
 112                 omap_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON);
 113         cx->mpu_state_vote--;
 114         raw_spin_unlock_irqrestore(&mpu_lock, flag);
 115
 116         return index;
 117 }
 118
 119 static int omap_enter_idle_coupled(struct cpuidle_device *dev,
 120                         struct cpuidle_driver *drv,
 121                         int index)
 122 {
 123         struct idle_statedata *cx = state_ptr + index;
 124         u32 mpuss_can_lose_context = 0;
 125         int error;
 126
 127         /*
 128          * CPU0 has to wait and stay ON until CPU1 is OFF state.
 129          * This is necessary to honour hardware recommondation
 130          * of triggeing all the possible low power modes once CPU1 is
 131          * out of coherency and in OFF mode.
 132          */
 133         if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
 134                 while (pwrdm_read_pwrst(cpu_pd[1]) != PWRDM_POWER_OFF) {
 135                         cpu_relax();
 136
 137                         /*
 138                          * CPU1 could have already entered & exited idle
 139                          * without hitting off because of a wakeup
 140                          * or a failed attempt to hit off mode.  Check for
 141                          * that here, otherwise we could spin forever
 142                          * waiting for CPU1 off.
 143                          */
 144                         if (cpu_done[1])
 145                             goto fail;
 146
 147                 }
 148         }
 149
 150         mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
 151                                  (cx->mpu_logic_state == PWRDM_POWER_OFF);
 152
 153         /* Enter broadcast mode for periodic timers */
 154         tick_broadcast_enable();
 155
 156         /* Enter broadcast mode for one-shot timers */
 157         tick_broadcast_enter();
 158
 159         /*
 160          * Call idle CPU PM enter notifier chain so that
 161          * VFP and per CPU interrupt context is saved.
 162          */
 163         error = cpu_pm_enter();
 164         if (error)
 165                 goto cpu_pm_out;
 166
 167         if (dev->cpu == 0) {
 168                 pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
 169                 omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
 170
 171                 /*
 172                  * Call idle CPU cluster PM enter notifier chain
 173                  * to save GIC and wakeupgen context.
 174                  */
 175                 if (mpuss_can_lose_context) {
 176                         error = cpu_cluster_pm_enter();
 177                         if (error)
 178                                 goto cpu_cluster_pm_out;
 179                 }
 180         }
 181
 182         omap4_enter_lowpower(dev->cpu, cx->cpu_state);
 183         cpu_done[dev->cpu] = true;
 184
 185 cpu_cluster_pm_out:
 186         /* Wakeup CPU1 only if it is not offlined */
 187         if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
 188
 189                 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
 190                     mpuss_can_lose_context)
 191                         gic_dist_disable();
 192
 193                 clkdm_deny_idle(cpu_clkdm[1]);
 194                 omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
 195                 clkdm_allow_idle(cpu_clkdm[1]);
 196
 197                 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) &&
 198                     mpuss_can_lose_context) {
 199                         while (gic_dist_disabled()) {
 200                                 udelay(1);
 201                                 cpu_relax();
 202                         }
 203                         gic_timer_retrigger();
 204                 }
 205         }
 206
 207         /*
 208          * Call idle CPU cluster PM exit notifier chain
 209          * to restore GIC and wakeupgen context.
 210          */
 211         if (dev->cpu == 0 && mpuss_can_lose_context)
 212                 cpu_cluster_pm_exit();
 213
 214         /*
 215          * Call idle CPU PM exit notifier chain to restore
 216          * VFP and per CPU IRQ context.
 217          */
 218         cpu_pm_exit();
 219
 220 cpu_pm_out:
 221         tick_broadcast_exit();
 222
 223 fail:
 224         cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
 225         cpu_done[dev->cpu] = false;
 226
 227         return index;
 228 }
 229
 230 static struct cpuidle_driver omap4_idle_driver = {
 231         .name                           = "omap4_idle",
 232         .owner                          = THIS_MODULE,
 233         .states = {
 234                 {
 235                         /* C1 - CPU0 ON + CPU1 ON + MPU ON */
 236                         .exit_latency = 2 + 2,
 237                         .target_residency = 5,
 238                         .enter = omap_enter_idle_simple,
 239                         .name = "C1",
 240                         .desc = "CPUx ON, MPUSS ON"
 241                 },
 242                 {
 243                         /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
 244                         .exit_latency = 328 + 440,
 245                         .target_residency = 960,
 246                         .flags = CPUIDLE_FLAG_COUPLED,
 247                         .enter = omap_enter_idle_coupled,
 248                         .name = "C2",
 249                         .desc = "CPUx OFF, MPUSS CSWR",
 250                 },
 251                 {
 252                         /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
 253                         .exit_latency = 460 + 518,
 254                         .target_residency = 1100,
 255                         .flags = CPUIDLE_FLAG_COUPLED,
 256                         .enter = omap_enter_idle_coupled,
 257                         .name = "C3",
 258                         .desc = "CPUx OFF, MPUSS OSWR",
 259                 },
 260         },
 261         .state_count = ARRAY_SIZE(omap4_idle_data),
 262         .safe_state_index = 0,
 263 };
 264
 265 static struct cpuidle_driver omap5_idle_driver = {
 266         .name                           = "omap5_idle",
 267         .owner                          = THIS_MODULE,
 268         .states = {
 269                 {
 270                         /* C1 - CPU0 ON + CPU1 ON + MPU ON */
 271                         .exit_latency = 2 + 2,
 272                         .target_residency = 5,
 273                         .enter = omap_enter_idle_simple,
 274                         .name = "C1",
 275                         .desc = "CPUx WFI, MPUSS ON"
 276                 },
 277                 {
 278                         /* C2 - CPU0 RET + CPU1 RET + MPU CSWR */
 279                         .exit_latency = 48 + 60,
 280                         .target_residency = 100,
 281                         .flags = CPUIDLE_FLAG_TIMER_STOP,
 282                         .enter = omap_enter_idle_smp,
 283                         .name = "C2",
 284                         .desc = "CPUx CSWR, MPUSS CSWR",
 285                 },
 286         },
 287         .state_count = ARRAY_SIZE(omap5_idle_data),
 288         .safe_state_index = 0,
 289 };
 290
 291 /* Public functions */
 292
 293 /**
 294  * omap4_idle_init - Init routine for OMAP4+ idle
 295  *
 296  * Registers the OMAP4+ specific cpuidle driver to the cpuidle
 297  * framework with the valid set of states.
 298  */
 299 int __init omap4_idle_init(void)
 300 {
 301         struct cpuidle_driver *idle_driver;
 302
 303         if (soc_is_omap54xx()) {
 304                 state_ptr = &omap5_idle_data[0];
 305                 idle_driver = &omap5_idle_driver;
 306         } else {
 307                 state_ptr = &omap4_idle_data[0];
 308                 idle_driver = &omap4_idle_driver;
 309         }
 310
 311         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 312         cpu_pd[0] = pwrdm_lookup("cpu0_pwrdm");
 313         cpu_pd[1] = pwrdm_lookup("cpu1_pwrdm");
 314         if ((!mpu_pd) || (!cpu_pd[0]) || (!cpu_pd[1]))
 315                 return -ENODEV;
 316
 317         cpu_clkdm[0] = clkdm_lookup("mpu0_clkdm");
 318         cpu_clkdm[1] = clkdm_lookup("mpu1_clkdm");
 319         if (!cpu_clkdm[0] || !cpu_clkdm[1])
 320                 return -ENODEV;
 321
 322         return cpuidle_register(idle_driver, cpu_online_mask);
 323 }