1 # SPDX-License-Identifier: GPL-2.0-only
2 menu "TI OMAP/AM/DM/DRA Family"
3 depends on ARCH_MULTI_V6 || ARCH_MULTI_V7
10 depends on ARCH_MULTI_V6
14 select SOC_HAS_OMAP2_SDRC
18 depends on ARCH_MULTI_V7
20 select ARM_CPU_SUSPEND
22 select OMAP_INTERCONNECT
24 select SOC_HAS_OMAP2_SDRC
25 select ARM_ERRATA_430973
29 depends on ARCH_MULTI_V7
31 select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
32 select ARM_CPU_SUSPEND
33 select ARM_ERRATA_720789
35 select HAVE_ARM_SCU if SMP
36 select HAVE_ARM_TWD if SMP
37 select OMAP_INTERCONNECT
38 select OMAP_INTERCONNECT_BARRIER
39 select PL310_ERRATA_588369 if CACHE_L2X0
40 select PL310_ERRATA_727915 if CACHE_L2X0
43 select ARM_ERRATA_754322
44 select ARM_ERRATA_775420
45 select OMAP_INTERCONNECT
49 depends on ARCH_MULTI_V7
51 select ARM_CPU_SUSPEND
53 select HAVE_ARM_SCU if SMP
54 select HAVE_ARM_ARCH_TIMER
55 select ARM_ERRATA_798181 if SMP
56 select OMAP_INTERCONNECT
57 select OMAP_INTERCONNECT_BARRIER
59 select ZONE_DMA if ARM_LPAE
63 depends on ARCH_MULTI_V7
65 select ARM_CPU_SUSPEND
69 depends on ARCH_MULTI_V7
72 select MACH_OMAP_GENERIC
74 select GENERIC_CLOCKEVENTS_BROADCAST
76 select ARM_ERRATA_754322
77 select ARM_ERRATA_775420
78 select OMAP_INTERCONNECT
79 select ARM_CPU_SUSPEND
83 depends on ARCH_MULTI_V7
85 select ARM_CPU_SUSPEND
87 select HAVE_ARM_SCU if SMP
88 select HAVE_ARM_ARCH_TIMER
90 select ARM_ERRATA_798181 if SMP
91 select OMAP_INTERCONNECT
92 select OMAP_INTERCONNECT_BARRIER
94 select ZONE_DMA if ARM_LPAE
95 select PINCTRL_TI_IODELAY if OF && PINCTRL
99 select ARCH_HAS_BANDGAP
100 select ARCH_HAS_RESET_CONTROLLER
103 select GENERIC_IRQ_CHIP
105 select MACH_OMAP_GENERIC
112 select PM_GENERIC_DOMAINS
113 select PM_GENERIC_DOMAINS_OF
114 select RESET_CONTROLLER
121 Systems based on OMAP2, OMAP3, OMAP4 or OMAP5
123 config OMAP_INTERCONNECT_BARRIER
130 menu "TI OMAP2/3/4 Specific Features"
132 config ARCH_OMAP2PLUS_TYPICAL
133 bool "Typical OMAP configuration"
139 select MENELAUS if ARCH_OMAP2
140 select NEON if CPU_V7
142 select REGULATOR_FIXED_VOLTAGE
143 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
144 select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
147 Compile a kernel suitable for booting most boards
149 config SOC_HAS_OMAP2_SDRC
150 bool "OMAP2 SDRAM Controller support"
152 config SOC_HAS_REALTIME_COUNTER
153 bool "Real time free running counter"
154 depends on SOC_OMAP5 || SOC_DRA7XX
157 comment "OMAP Core Type"
158 depends on ARCH_OMAP2
161 bool "OMAP2420 support"
162 depends on ARCH_OMAP2
165 select SOC_HAS_OMAP2_SDRC
168 bool "OMAP2430 support"
169 depends on ARCH_OMAP2
171 select SOC_HAS_OMAP2_SDRC
174 bool "OMAP3430 support"
175 depends on ARCH_OMAP3
177 select SOC_HAS_OMAP2_SDRC
180 bool "TI81XX support"
181 depends on ARCH_OMAP3
184 comment "OMAP Legacy Platform Data Board Type"
185 depends on ARCH_OMAP2PLUS
187 config MACH_OMAP_GENERIC
190 config MACH_OMAP2_TUSB6010
192 depends on ARCH_OMAP2 && SOC_OMAP2420
193 default y if MACH_NOKIA_N8X0
195 config MACH_NOKIA_N810
198 config MACH_NOKIA_N810_WIMAX
201 config MACH_NOKIA_N8X0
202 bool "Nokia N800/N810"
203 depends on SOC_OMAP2420
205 select MACH_NOKIA_N810
206 select MACH_NOKIA_N810_WIMAX
208 config OMAP3_SDRC_AC_TIMING
209 bool "Enable SDRC AC timing register changes"
210 depends on ARCH_OMAP3
212 If you know that none of your system initiators will attempt to
213 access SDRAM during CORE DVFS, select Y here. This should boost
214 SDRAM performance at lower CORE OPPs. There are relatively few
215 users who will wish to say yes at this point - almost everyone will
216 wish to say no. Selecting yes without understanding what is
217 going on could result in system crashes;
223 config OMAP5_ERRATA_801819
224 bool "Errata 801819: An eviction from L1 data cache might stall indefinitely"
225 depends on SOC_OMAP5 || SOC_DRA7XX
227 A livelock can occur in the L2 cache arbitration that might prevent
228 a snoop from completing. Under certain conditions this can cause the