2 * linux/arch/arm/mach-omap1/irq.c
4 * Interrupt handler for all OMAP boards
6 * Copyright (C) 2004 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
8 * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
10 * Completely re-written to support various OMAP chips with bank specific
13 * Some snippets of the code taken from the older OMAP interrupt handler
14 * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
16 * GPIO interrupt handler moved to gpio.c by Juha Yrjola
18 * This program is free software; you can redistribute it and/or modify it
19 * under the terms of the GNU General Public License as published by the
20 * Free Software Foundation; either version 2 of the License, or (at your
21 * option) any later version.
23 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * You should have received a copy of the GNU General Public License along
35 * with this program; if not, write to the Free Software Foundation, Inc.,
36 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 #include <linux/gpio.h>
39 #include <linux/init.h>
40 #include <linux/module.h>
41 #include <linux/sched.h>
42 #include <linux/interrupt.h>
46 #include <asm/mach/irq.h>
50 #include <mach/hardware.h>
54 #define IRQ_BANK(irq) ((irq) >> 5)
55 #define IRQ_BIT(irq) ((irq) & 0x1f)
57 struct omap_irq_bank {
58 unsigned long base_reg;
60 unsigned long trigger_map;
61 unsigned long wake_enable;
65 static unsigned int irq_bank_count;
66 static struct omap_irq_bank *irq_banks;
67 static struct irq_domain *domain;
69 static inline unsigned int irq_bank_readl(int bank, int offset)
71 return readl_relaxed(irq_banks[bank].va + offset);
73 static inline void irq_bank_writel(unsigned long value, int bank, int offset)
75 writel_relaxed(value, irq_banks[bank].va + offset);
78 static void omap_ack_irq(int irq)
81 writel_relaxed(0x1, irq_banks[1].va + IRQ_CONTROL_REG_OFFSET);
83 writel_relaxed(0x1, irq_banks[0].va + IRQ_CONTROL_REG_OFFSET);
86 static void omap_mask_ack_irq(struct irq_data *d)
88 struct irq_chip_type *ct = irq_data_get_chip_type(d);
95 * Allows tuning the IRQ type and priority
97 * NOTE: There is currently no OMAP fiq handler for Linux. Read the
98 * mailing list threads on FIQ handlers if you are planning to
99 * add a FIQ handler for OMAP.
101 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
104 unsigned long val, offset;
106 bank = IRQ_BANK(irq);
107 /* FIQ is only available on bank 0 interrupts */
108 fiq = bank ? 0 : (fiq & 0x1);
109 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
110 offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
111 irq_bank_writel(val, bank, offset);
114 #if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850)
115 static struct omap_irq_bank omap7xx_irq_banks[] = {
116 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f },
117 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 },
118 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 },
122 #ifdef CONFIG_ARCH_OMAP15XX
123 static struct omap_irq_bank omap1510_irq_banks[] = {
124 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff },
125 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed },
127 static struct omap_irq_bank omap310_irq_banks[] = {
128 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 },
129 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 },
133 #if defined(CONFIG_ARCH_OMAP16XX)
135 static struct omap_irq_bank omap1610_irq_banks[] = {
136 { .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f },
137 { .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd },
138 { .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff },
139 { .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff },
144 omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
146 struct irq_chip_generic *gc;
147 struct irq_chip_type *ct;
149 gc = irq_alloc_generic_chip("MPU", 1, irq_start, base,
152 ct->chip.irq_ack = omap_mask_ack_irq;
153 ct->chip.irq_mask = irq_gc_mask_set_bit;
154 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
155 ct->chip.irq_set_wake = irq_gc_set_wake;
156 ct->regs.mask = IRQ_MIR_REG_OFFSET;
157 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
158 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
161 void __init omap1_init_irq(void)
163 struct irq_chip_type *ct;
164 struct irq_data *d = NULL;
166 unsigned long nr_irqs;
168 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
169 if (cpu_is_omap7xx()) {
170 omap_irq_flags = INT_7XX_IH2_IRQ;
171 irq_banks = omap7xx_irq_banks;
172 irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks);
175 #ifdef CONFIG_ARCH_OMAP15XX
176 if (cpu_is_omap1510()) {
177 omap_irq_flags = INT_1510_IH2_IRQ;
178 irq_banks = omap1510_irq_banks;
179 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
181 if (cpu_is_omap310()) {
182 omap_irq_flags = INT_1510_IH2_IRQ;
183 irq_banks = omap310_irq_banks;
184 irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
187 #if defined(CONFIG_ARCH_OMAP16XX)
188 if (cpu_is_omap16xx()) {
189 omap_irq_flags = INT_1510_IH2_IRQ;
190 irq_banks = omap1610_irq_banks;
191 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
195 for (i = 0; i < irq_bank_count; i++) {
196 irq_banks[i].va = ioremap(irq_banks[i].base_reg, 0xff);
197 if (WARN_ON(!irq_banks[i].va))
201 nr_irqs = irq_bank_count * 32;
203 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
205 pr_warn("Couldn't allocate IRQ numbers\n");
209 domain = irq_domain_add_legacy(NULL, nr_irqs, irq_base, 0,
210 &irq_domain_simple_ops, NULL);
212 pr_info("Total of %lu interrupts in %i interrupt banks\n",
213 nr_irqs, irq_bank_count);
215 /* Mask and clear all interrupts */
216 for (i = 0; i < irq_bank_count; i++) {
217 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
218 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
221 /* Clear any pending interrupts */
222 irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
223 irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
225 /* Enable interrupts in global mask */
226 if (cpu_is_omap7xx())
227 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
229 /* Install the interrupt handlers for each bank */
230 for (i = 0; i < irq_bank_count; i++) {
231 for (j = i * 32; j < (i + 1) * 32; j++) {
234 irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
235 omap_irq_set_cfg(j, 0, 0, irq_trigger);
236 set_irq_flags(j, IRQF_VALID);
238 omap_alloc_gc(irq_banks[i].va, irq_base + i * 32, 32);
241 /* Unmask level 2 handler */
242 d = irq_get_irq_data(omap_irq_flags);
244 ct = irq_data_get_chip_type(d);
245 ct->chip.irq_unmask(d);