1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-omap1/clock.c
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
6 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
8 * Modified to use omap shared clock framework by
9 * Tony Lindgren <tony@atomide.com>
11 #include <linux/kernel.h>
12 #include <linux/export.h>
13 #include <linux/list.h>
14 #include <linux/errno.h>
15 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/clkdev.h>
20 #include <asm/mach-types.h>
22 #include <mach/hardware.h>
30 __u32 arm_idlect1_mask;
31 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
33 static LIST_HEAD(clocks);
34 static DEFINE_MUTEX(clocks_mutex);
35 static DEFINE_SPINLOCK(clockfw_lock);
38 * Omap1 specific clock functions
41 unsigned long omap1_uart_recalc(struct clk *clk)
43 unsigned int val = __raw_readl(clk->enable_reg);
44 return val & clk->enable_bit ? 48000000 : 12000000;
47 unsigned long omap1_sossi_recalc(struct clk *clk)
49 u32 div = omap_readl(MOD_CONF_CTRL_1);
51 div = (div >> 17) & 0x7;
54 return clk->parent->rate / div;
57 static void omap1_clk_allow_idle(struct clk *clk)
59 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
61 if (!(clk->flags & CLOCK_IDLE_CONTROL))
64 if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count))
65 arm_idlect1_mask |= 1 << iclk->idlect_shift;
68 static void omap1_clk_deny_idle(struct clk *clk)
70 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk;
72 if (!(clk->flags & CLOCK_IDLE_CONTROL))
75 if (iclk->no_idle_count++ == 0)
76 arm_idlect1_mask &= ~(1 << iclk->idlect_shift);
79 static __u16 verify_ckctl_value(__u16 newval)
81 /* This function checks for following limitations set
82 * by the hardware (all conditions must be true):
83 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
88 * In addition following rules are enforced:
92 * However, maximum frequencies are not checked for!
101 per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3;
102 lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3;
103 arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3;
104 dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3;
105 tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3;
106 dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3;
108 if (dspmmu_exp < dsp_exp)
109 dspmmu_exp = dsp_exp;
110 if (dspmmu_exp > dsp_exp+1)
111 dspmmu_exp = dsp_exp+1;
112 if (tc_exp < arm_exp)
114 if (tc_exp < dspmmu_exp)
116 if (tc_exp > lcd_exp)
118 if (tc_exp > per_exp)
122 newval |= per_exp << CKCTL_PERDIV_OFFSET;
123 newval |= lcd_exp << CKCTL_LCDDIV_OFFSET;
124 newval |= arm_exp << CKCTL_ARMDIV_OFFSET;
125 newval |= dsp_exp << CKCTL_DSPDIV_OFFSET;
126 newval |= tc_exp << CKCTL_TCDIV_OFFSET;
127 newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET;
132 static int calc_dsor_exp(struct clk *clk, unsigned long rate)
134 /* Note: If target frequency is too low, this function will return 4,
135 * which is invalid value. Caller must check for this value and act
138 * Note: This function does not check for following limitations set
139 * by the hardware (all conditions must be true):
140 * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2
145 unsigned long realrate;
149 parent = clk->parent;
150 if (unlikely(parent == NULL))
153 realrate = parent->rate;
154 for (dsor_exp=0; dsor_exp<4; dsor_exp++) {
155 if (realrate <= rate)
164 unsigned long omap1_ckctl_recalc(struct clk *clk)
166 /* Calculate divisor encoded as 2-bit exponent */
167 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset));
169 return clk->parent->rate / dsor;
172 unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk)
176 /* Calculate divisor encoded as 2-bit exponent
178 * The clock control bits are in DSP domain,
179 * so api_ck is needed for access.
180 * Note that DSP_CKCTL virt addr = phys addr, so
181 * we must use __raw_readw() instead of omap_readw().
183 omap1_clk_enable(api_ck_p);
184 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset));
185 omap1_clk_disable(api_ck_p);
187 return clk->parent->rate / dsor;
190 /* MPU virtual clock functions */
191 int omap1_select_table_rate(struct clk *clk, unsigned long rate)
193 /* Find the highest supported frequency <= rate and switch to it */
194 struct mpu_rate * ptr;
195 unsigned long ref_rate;
197 ref_rate = ck_ref_p->rate;
199 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
200 if (!(ptr->flags & cpu_mask))
203 if (ptr->xtal != ref_rate)
206 /* Can check only after xtal frequency check */
207 if (ptr->rate <= rate)
215 * In most cases we should not need to reprogram DPLL.
216 * Reprogramming the DPLL is tricky, it must be done from SRAM.
218 omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
220 /* XXX Do we need to recalculate the tree below DPLL1 at this point? */
221 ck_dpll1_p->rate = ptr->pll_rate;
226 int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate)
231 dsor_exp = calc_dsor_exp(clk, rate);
237 regval = __raw_readw(DSP_CKCTL);
238 regval &= ~(3 << clk->rate_offset);
239 regval |= dsor_exp << clk->rate_offset;
240 __raw_writew(regval, DSP_CKCTL);
241 clk->rate = clk->parent->rate / (1 << dsor_exp);
246 long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate)
248 int dsor_exp = calc_dsor_exp(clk, rate);
253 return clk->parent->rate / (1 << dsor_exp);
256 int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate)
261 dsor_exp = calc_dsor_exp(clk, rate);
267 regval = omap_readw(ARM_CKCTL);
268 regval &= ~(3 << clk->rate_offset);
269 regval |= dsor_exp << clk->rate_offset;
270 regval = verify_ckctl_value(regval);
271 omap_writew(regval, ARM_CKCTL);
272 clk->rate = clk->parent->rate / (1 << dsor_exp);
276 long omap1_round_to_table_rate(struct clk *clk, unsigned long rate)
278 /* Find the highest supported frequency <= rate */
279 struct mpu_rate * ptr;
281 unsigned long ref_rate;
283 ref_rate = ck_ref_p->rate;
285 highest_rate = -EINVAL;
287 for (ptr = omap1_rate_table; ptr->rate; ptr++) {
288 if (!(ptr->flags & cpu_mask))
291 if (ptr->xtal != ref_rate)
294 highest_rate = ptr->rate;
296 /* Can check only after xtal frequency check */
297 if (ptr->rate <= rate)
304 static unsigned calc_ext_dsor(unsigned long rate)
308 /* MCLK and BCLK divisor selection is not linear:
309 * freq = 96MHz / dsor
311 * RATIO_SEL range: dsor <-> RATIO_SEL
312 * 0..6: (RATIO_SEL+2) <-> (dsor-2)
313 * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6)
314 * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9
317 for (dsor = 2; dsor < 96; ++dsor) {
318 if ((dsor & 1) && dsor > 8)
320 if (rate >= 96000000 / dsor)
326 /* XXX Only needed on 1510 */
327 int omap1_set_uart_rate(struct clk *clk, unsigned long rate)
331 val = __raw_readl(clk->enable_reg);
332 if (rate == 12000000)
333 val &= ~(1 << clk->enable_bit);
334 else if (rate == 48000000)
335 val |= (1 << clk->enable_bit);
338 __raw_writel(val, clk->enable_reg);
344 /* External clock (MCLK & BCLK) functions */
345 int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate)
350 dsor = calc_ext_dsor(rate);
351 clk->rate = 96000000 / dsor;
353 ratio_bits = ((dsor - 8) / 2 + 6) << 2;
355 ratio_bits = (dsor - 2) << 2;
357 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd;
358 __raw_writew(ratio_bits, clk->enable_reg);
363 int omap1_set_sossi_rate(struct clk *clk, unsigned long rate)
367 unsigned long p_rate;
369 p_rate = clk->parent->rate;
370 /* Round towards slower frequency */
371 div = (p_rate + rate - 1) / rate;
373 if (div < 0 || div > 7)
376 l = omap_readl(MOD_CONF_CTRL_1);
379 omap_writel(l, MOD_CONF_CTRL_1);
381 clk->rate = p_rate / (div + 1);
386 long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate)
388 return 96000000 / calc_ext_dsor(rate);
391 void omap1_init_ext_clk(struct clk *clk)
396 /* Determine current rate and ensure clock is based on 96MHz APLL */
397 ratio_bits = __raw_readw(clk->enable_reg) & ~1;
398 __raw_writew(ratio_bits, clk->enable_reg);
400 ratio_bits = (ratio_bits & 0xfc) >> 2;
402 dsor = (ratio_bits - 6) * 2 + 8;
404 dsor = ratio_bits + 2;
406 clk-> rate = 96000000 / dsor;
409 int omap1_clk_enable(struct clk *clk)
413 if (clk->usecount++ == 0) {
415 ret = omap1_clk_enable(clk->parent);
419 if (clk->flags & CLOCK_NO_IDLE_PARENT)
420 omap1_clk_deny_idle(clk->parent);
423 ret = clk->ops->enable(clk);
426 omap1_clk_disable(clk->parent);
437 void omap1_clk_disable(struct clk *clk)
439 if (clk->usecount > 0 && !(--clk->usecount)) {
440 clk->ops->disable(clk);
441 if (likely(clk->parent)) {
442 omap1_clk_disable(clk->parent);
443 if (clk->flags & CLOCK_NO_IDLE_PARENT)
444 omap1_clk_allow_idle(clk->parent);
449 static int omap1_clk_enable_generic(struct clk *clk)
454 if (unlikely(clk->enable_reg == NULL)) {
455 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
460 if (clk->flags & ENABLE_REG_32BIT) {
461 regval32 = __raw_readl(clk->enable_reg);
462 regval32 |= (1 << clk->enable_bit);
463 __raw_writel(regval32, clk->enable_reg);
465 regval16 = __raw_readw(clk->enable_reg);
466 regval16 |= (1 << clk->enable_bit);
467 __raw_writew(regval16, clk->enable_reg);
473 static void omap1_clk_disable_generic(struct clk *clk)
478 if (clk->enable_reg == NULL)
481 if (clk->flags & ENABLE_REG_32BIT) {
482 regval32 = __raw_readl(clk->enable_reg);
483 regval32 &= ~(1 << clk->enable_bit);
484 __raw_writel(regval32, clk->enable_reg);
486 regval16 = __raw_readw(clk->enable_reg);
487 regval16 &= ~(1 << clk->enable_bit);
488 __raw_writew(regval16, clk->enable_reg);
492 const struct clkops clkops_generic = {
493 .enable = omap1_clk_enable_generic,
494 .disable = omap1_clk_disable_generic,
497 static int omap1_clk_enable_dsp_domain(struct clk *clk)
501 retval = omap1_clk_enable(api_ck_p);
503 retval = omap1_clk_enable_generic(clk);
504 omap1_clk_disable(api_ck_p);
510 static void omap1_clk_disable_dsp_domain(struct clk *clk)
512 if (omap1_clk_enable(api_ck_p) == 0) {
513 omap1_clk_disable_generic(clk);
514 omap1_clk_disable(api_ck_p);
518 const struct clkops clkops_dspck = {
519 .enable = omap1_clk_enable_dsp_domain,
520 .disable = omap1_clk_disable_dsp_domain,
523 /* XXX SYSC register handling does not belong in the clock framework */
524 static int omap1_clk_enable_uart_functional_16xx(struct clk *clk)
527 struct uart_clk *uclk;
529 ret = omap1_clk_enable_generic(clk);
531 /* Set smart idle acknowledgement mode */
532 uclk = (struct uart_clk *)clk;
533 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8,
540 /* XXX SYSC register handling does not belong in the clock framework */
541 static void omap1_clk_disable_uart_functional_16xx(struct clk *clk)
543 struct uart_clk *uclk;
545 /* Set force idle acknowledgement mode */
546 uclk = (struct uart_clk *)clk;
547 omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr);
549 omap1_clk_disable_generic(clk);
552 /* XXX SYSC register handling does not belong in the clock framework */
553 const struct clkops clkops_uart_16xx = {
554 .enable = omap1_clk_enable_uart_functional_16xx,
555 .disable = omap1_clk_disable_uart_functional_16xx,
558 long omap1_clk_round_rate(struct clk *clk, unsigned long rate)
560 if (clk->round_rate != NULL)
561 return clk->round_rate(clk, rate);
566 int omap1_clk_set_rate(struct clk *clk, unsigned long rate)
571 ret = clk->set_rate(clk, rate);
576 * Omap1 clock reset and init functions
579 #ifdef CONFIG_OMAP_RESET_CLOCKS
581 void omap1_clk_disable_unused(struct clk *clk)
585 /* Clocks in the DSP domain need api_ck. Just assume bootloader
586 * has not enabled any DSP clocks */
587 if (clk->enable_reg == DSP_IDLECT2) {
588 pr_info("Skipping reset check for DSP domain clock \"%s\"\n",
593 /* Is the clock already disabled? */
594 if (clk->flags & ENABLE_REG_32BIT)
595 regval32 = __raw_readl(clk->enable_reg);
597 regval32 = __raw_readw(clk->enable_reg);
599 if ((regval32 & (1 << clk->enable_bit)) == 0)
602 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name);
603 clk->ops->disable(clk);
610 int clk_enable(struct clk *clk)
615 if (IS_ERR_OR_NULL(clk))
618 spin_lock_irqsave(&clockfw_lock, flags);
619 ret = omap1_clk_enable(clk);
620 spin_unlock_irqrestore(&clockfw_lock, flags);
624 EXPORT_SYMBOL(clk_enable);
626 void clk_disable(struct clk *clk)
630 if (IS_ERR_OR_NULL(clk))
633 spin_lock_irqsave(&clockfw_lock, flags);
634 if (clk->usecount == 0) {
635 pr_err("Trying disable clock %s with 0 usecount\n",
641 omap1_clk_disable(clk);
644 spin_unlock_irqrestore(&clockfw_lock, flags);
646 EXPORT_SYMBOL(clk_disable);
648 unsigned long clk_get_rate(struct clk *clk)
653 if (IS_ERR_OR_NULL(clk))
656 spin_lock_irqsave(&clockfw_lock, flags);
658 spin_unlock_irqrestore(&clockfw_lock, flags);
662 EXPORT_SYMBOL(clk_get_rate);
665 * Optional clock functions defined in include/linux/clk.h
668 long clk_round_rate(struct clk *clk, unsigned long rate)
673 if (IS_ERR_OR_NULL(clk))
676 spin_lock_irqsave(&clockfw_lock, flags);
677 ret = omap1_clk_round_rate(clk, rate);
678 spin_unlock_irqrestore(&clockfw_lock, flags);
682 EXPORT_SYMBOL(clk_round_rate);
684 int clk_set_rate(struct clk *clk, unsigned long rate)
689 if (IS_ERR_OR_NULL(clk))
692 spin_lock_irqsave(&clockfw_lock, flags);
693 ret = omap1_clk_set_rate(clk, rate);
696 spin_unlock_irqrestore(&clockfw_lock, flags);
700 EXPORT_SYMBOL(clk_set_rate);
702 int clk_set_parent(struct clk *clk, struct clk *parent)
704 WARN_ONCE(1, "clk_set_parent() not implemented for OMAP1\n");
708 EXPORT_SYMBOL(clk_set_parent);
710 struct clk *clk_get_parent(struct clk *clk)
714 EXPORT_SYMBOL(clk_get_parent);
717 * OMAP specific clock functions shared between omap1 and omap2
720 /* Used for clocks that always have same value as the parent clock */
721 unsigned long followparent_recalc(struct clk *clk)
723 return clk->parent->rate;
727 * Used for clocks that have the same value as the parent clock,
728 * divided by some factor
730 unsigned long omap_fixed_divisor_recalc(struct clk *clk)
732 WARN_ON(!clk->fixed_div);
734 return clk->parent->rate / clk->fixed_div;
737 void clk_reparent(struct clk *child, struct clk *parent)
739 list_del_init(&child->sibling);
741 list_add(&child->sibling, &parent->children);
742 child->parent = parent;
744 /* now do the debugfs renaming to reattach the child
745 to the proper parent */
748 /* Propagate rate to children */
749 void propagate_rate(struct clk *tclk)
753 list_for_each_entry(clkp, &tclk->children, sibling) {
755 clkp->rate = clkp->recalc(clkp);
756 propagate_rate(clkp);
760 static LIST_HEAD(root_clks);
763 * recalculate_root_clocks - recalculate and propagate all root clocks
765 * Recalculates all root clocks (clocks with no parent), which if the
766 * clock's .recalc is set correctly, should also propagate their rates.
769 void recalculate_root_clocks(void)
773 list_for_each_entry(clkp, &root_clks, sibling) {
775 clkp->rate = clkp->recalc(clkp);
776 propagate_rate(clkp);
781 * clk_preinit - initialize any fields in the struct clk before clk init
782 * @clk: struct clk * to initialize
784 * Initialize any struct clk fields needed before normal clk initialization
785 * can run. No return value.
787 void clk_preinit(struct clk *clk)
789 INIT_LIST_HEAD(&clk->children);
792 int clk_register(struct clk *clk)
794 if (IS_ERR_OR_NULL(clk))
798 * trap out already registered clocks
800 if (clk->node.next || clk->node.prev)
803 mutex_lock(&clocks_mutex);
805 list_add(&clk->sibling, &clk->parent->children);
807 list_add(&clk->sibling, &root_clks);
809 list_add(&clk->node, &clocks);
812 mutex_unlock(&clocks_mutex);
816 EXPORT_SYMBOL(clk_register);
818 void clk_unregister(struct clk *clk)
820 if (IS_ERR_OR_NULL(clk))
823 mutex_lock(&clocks_mutex);
824 list_del(&clk->sibling);
825 list_del(&clk->node);
826 mutex_unlock(&clocks_mutex);
828 EXPORT_SYMBOL(clk_unregister);
830 void clk_enable_init_clocks(void)
834 list_for_each_entry(clkp, &clocks, node)
835 if (clkp->flags & ENABLE_ON_INIT)
840 * omap_clk_get_by_name - locate OMAP struct clk by its name
841 * @name: name of the struct clk to locate
843 * Locate an OMAP struct clk by its name. Assumes that struct clk
844 * names are unique. Returns NULL if not found or a pointer to the
845 * struct clk if found.
847 struct clk *omap_clk_get_by_name(const char *name)
850 struct clk *ret = NULL;
852 mutex_lock(&clocks_mutex);
854 list_for_each_entry(c, &clocks, node) {
855 if (!strcmp(c->name, name)) {
861 mutex_unlock(&clocks_mutex);
866 int omap_clk_enable_autoidle_all(void)
871 spin_lock_irqsave(&clockfw_lock, flags);
873 list_for_each_entry(c, &clocks, node)
874 if (c->ops->allow_idle)
875 c->ops->allow_idle(c);
877 spin_unlock_irqrestore(&clockfw_lock, flags);
882 int omap_clk_disable_autoidle_all(void)
887 spin_lock_irqsave(&clockfw_lock, flags);
889 list_for_each_entry(c, &clocks, node)
890 if (c->ops->deny_idle)
891 c->ops->deny_idle(c);
893 spin_unlock_irqrestore(&clockfw_lock, flags);
901 static int clkll_enable_null(struct clk *clk)
906 static void clkll_disable_null(struct clk *clk)
910 const struct clkops clkops_null = {
911 .enable = clkll_enable_null,
912 .disable = clkll_disable_null,
918 * Used for clock aliases that are needed on some OMAPs, but not others
920 struct clk dummy_ck = {
929 #ifdef CONFIG_OMAP_RESET_CLOCKS
931 * Disable any unused clocks left on by the bootloader
933 static int __init clk_disable_unused(void)
938 pr_info("clock: disabling unused clocks to save power\n");
940 spin_lock_irqsave(&clockfw_lock, flags);
941 list_for_each_entry(ck, &clocks, node) {
942 if (ck->ops == &clkops_null)
945 if (ck->usecount > 0 || !ck->enable_reg)
948 omap1_clk_disable_unused(ck);
950 spin_unlock_irqrestore(&clockfw_lock, flags);
954 late_initcall(clk_disable_unused);
955 late_initcall(omap_clk_enable_autoidle_all);
958 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
960 * debugfs support to trace clock tree hierarchy and attributes
963 #include <linux/debugfs.h>
964 #include <linux/seq_file.h>
966 static struct dentry *clk_debugfs_root;
968 static int debug_clock_show(struct seq_file *s, void *unused)
973 mutex_lock(&clocks_mutex);
974 seq_printf(s, "%-30s %-30s %-10s %s\n",
975 "clock-name", "parent-name", "rate", "use-count");
977 list_for_each_entry(c, &clocks, node) {
979 seq_printf(s, "%-30s %-30s %-10lu %d\n",
980 c->name, pa ? pa->name : "none", c->rate,
983 mutex_unlock(&clocks_mutex);
988 DEFINE_SHOW_ATTRIBUTE(debug_clock);
990 static void clk_debugfs_register_one(struct clk *c)
993 struct clk *pa = c->parent;
995 d = debugfs_create_dir(c->name, pa ? pa->dent : clk_debugfs_root);
998 debugfs_create_u8("usecount", S_IRUGO, c->dent, &c->usecount);
999 debugfs_create_ulong("rate", S_IRUGO, c->dent, &c->rate);
1000 debugfs_create_x8("flags", S_IRUGO, c->dent, &c->flags);
1003 static void clk_debugfs_register(struct clk *c)
1005 struct clk *pa = c->parent;
1007 if (pa && !pa->dent)
1008 clk_debugfs_register(pa);
1011 clk_debugfs_register_one(c);
1014 static int __init clk_debugfs_init(void)
1019 d = debugfs_create_dir("clock", NULL);
1020 clk_debugfs_root = d;
1022 list_for_each_entry(c, &clocks, node)
1023 clk_debugfs_register(c);
1025 debugfs_create_file("summary", S_IRUGO, d, NULL, &debug_clock_fops);
1029 late_initcall(clk_debugfs_init);
1031 #endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */