2 * linux/arch/arm/mach-integrator/integrator_cp.c
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/string.h>
17 #include <linux/device.h>
18 #include <linux/amba/bus.h>
19 #include <linux/amba/kmi.h>
20 #include <linux/amba/clcd.h>
21 #include <linux/platform_data/video-clcd-versatile.h>
22 #include <linux/amba/mmci.h>
24 #include <linux/irqchip.h>
25 #include <linux/gfp.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <linux/sched_clock.h>
31 #include <asm/setup.h>
32 #include <asm/mach-types.h>
33 #include <asm/mach/arch.h>
34 #include <asm/mach/irq.h>
35 #include <asm/mach/map.h>
36 #include <asm/mach/time.h>
42 /* Base address to the CP controller */
43 static void __iomem *intcp_con_base;
45 #define INTCP_PA_CLCD_BASE 0xc0000000
49 * f1000000 10000000 Core module registers
50 * f1300000 13000000 Counter/Timer
51 * f1400000 14000000 Interrupt controller
52 * f1600000 16000000 UART 0
53 * f1700000 17000000 UART 1
54 * f1a00000 1a000000 Debug LEDs
55 * fc900000 c9000000 GPIO
56 * fca00000 ca000000 SIC
59 static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
61 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
62 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
66 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
67 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
71 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
72 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
76 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
77 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
81 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
82 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
86 .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
87 .pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
91 .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
92 .pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
98 static void __init intcp_map_io(void)
100 iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
104 * It seems that the card insertion interrupt remains active after
105 * we've acknowledged it. We therefore ignore the interrupt, and
106 * rely on reading it from the SIC. This also means that we must
107 * clear the latched interrupt.
109 static unsigned int mmc_status(struct device *dev)
111 unsigned int status = readl(__io_address(0xca000000 + 4));
112 writel(8, intcp_con_base + 8);
117 static struct mmci_platform_data mmc_data = {
118 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
119 .status = mmc_status,
128 * Ensure VGA is selected.
130 static void cp_clcd_enable(struct clcd_fb *fb)
132 struct fb_var_screeninfo *var = &fb->fb.var;
133 u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
134 | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;
136 if (var->bits_per_pixel <= 8 ||
137 (var->bits_per_pixel == 16 && var->green.length == 5))
138 /* Pseudocolor, RGB555, BGR555 */
139 val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
140 else if (fb->fb.var.bits_per_pixel <= 16)
141 /* truecolor RGB565 */
142 val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
144 val = 0; /* no idea for this, don't trust the docs */
146 cm_control(CM_CTRL_LCDMUXSEL_MASK|
152 CM_CTRL_n24BITEN, val);
155 static int cp_clcd_setup(struct clcd_fb *fb)
157 fb->panel = versatile_clcd_get_panel("VGA");
161 return versatile_clcd_setup_dma(fb, SZ_1M);
164 static struct clcd_board clcd_data = {
165 .name = "Integrator/CP",
166 .caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
167 .check = clcdfb_check,
168 .decode = clcdfb_decode,
169 .enable = cp_clcd_enable,
170 .setup = cp_clcd_setup,
171 .mmap = versatile_clcd_mmap_dma,
172 .remove = versatile_clcd_remove_dma,
175 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
177 static u64 notrace intcp_read_sched_clock(void)
179 return readl(REFCOUNTER);
182 static void __init intcp_init_early(void)
184 sched_clock_register(intcp_read_sched_clock, 32, 24000000);
187 static void __init intcp_init_irq_of(void)
194 * For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
195 * and enforce the bus names since these are used for clock lookups.
197 static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
198 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
200 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
202 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
204 OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
206 OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
208 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
210 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
212 OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
217 static const struct of_device_id intcp_syscon_match[] = {
218 { .compatible = "arm,integrator-cp-syscon"},
222 static void __init intcp_init_of(void)
224 struct device_node *cpcon;
226 cpcon = of_find_matching_node(NULL, intcp_syscon_match);
230 intcp_con_base = of_iomap(cpcon, 0);
234 of_platform_default_populate(NULL, intcp_auxdata_lookup, NULL);
237 static const char * intcp_dt_board_compat[] = {
242 DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
243 .reserve = integrator_reserve,
244 .map_io = intcp_map_io,
245 .init_early = intcp_init_early,
246 .init_irq = intcp_init_irq_of,
247 .init_machine = intcp_init_of,
248 .dt_compat = intcp_dt_board_compat,