1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * linux/arch/arm/mach-integrator/integrator_ap.c
5 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
7 #include <linux/kernel.h>
8 #include <linux/init.h>
9 #include <linux/syscore_ops.h>
10 #include <linux/amba/bus.h>
12 #include <linux/irqchip.h>
13 #include <linux/of_irq.h>
14 #include <linux/of_address.h>
15 #include <linux/of_platform.h>
16 #include <linux/termios.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/regmap.h>
20 #include <asm/mach/arch.h>
21 #include <asm/mach/map.h>
27 /* Regmap to the AP system controller */
28 static struct regmap *ap_syscon_map;
31 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
34 * Setup a VA for the Integrator interrupt controller (for header #0,
37 #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
41 * f1400000 14000000 Interrupt controller
42 * f1600000 16000000 UART 0
45 static struct map_desc ap_io_desc[] __initdata __maybe_unused = {
47 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
48 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
52 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
53 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
59 static void __init ap_map_io(void)
61 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
65 static unsigned long ic_irq_enable;
67 static int irq_suspend(void)
69 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
73 static void irq_resume(void)
75 /* disable all irq sources */
77 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
78 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
80 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
83 #define irq_suspend NULL
84 #define irq_resume NULL
87 static struct syscore_ops irq_syscore_ops = {
88 .suspend = irq_suspend,
92 static int __init irq_syscore_init(void)
94 register_syscore_ops(&irq_syscore_ops);
99 device_initcall(irq_syscore_init);
102 * For the PL010 found in the Integrator/AP some of the UART control is
103 * implemented in the system controller and accessed using a callback
106 static void integrator_uart_set_mctrl(struct amba_device *dev,
107 void __iomem *base, unsigned int mctrl)
109 unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
110 u32 phybase = dev->res.start;
113 if (phybase == INTEGRATOR_UART0_BASE) {
123 if (mctrl & TIOCM_RTS)
128 if (mctrl & TIOCM_DTR)
133 ret = regmap_write(ap_syscon_map,
134 INTEGRATOR_SC_CTRLS_OFFSET,
137 pr_err("MODEM: unable to write PL010 UART CTRLS\n");
139 ret = regmap_write(ap_syscon_map,
140 INTEGRATOR_SC_CTRLC_OFFSET,
143 pr_err("MODEM: unable to write PL010 UART CRTLC\n");
146 struct amba_pl010_data ap_uart_data = {
147 .set_mctrl = integrator_uart_set_mctrl,
150 void __init ap_init_early(void)
154 static void __init ap_init_irq_of(void)
160 /* For the Device Tree, add in the UART callbacks as AUXDATA */
161 static struct of_dev_auxdata ap_auxdata_lookup[] __initdata = {
162 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
163 "uart0", &ap_uart_data),
164 OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
165 "uart1", &ap_uart_data),
169 static const struct of_device_id ap_syscon_match[] = {
170 { .compatible = "arm,integrator-ap-syscon"},
174 static void __init ap_init_of(void)
176 struct device_node *syscon;
178 of_platform_default_populate(NULL, ap_auxdata_lookup, NULL);
180 syscon = of_find_matching_node(NULL, ap_syscon_match);
183 ap_syscon_map = syscon_node_to_regmap(syscon);
184 if (IS_ERR(ap_syscon_map)) {
185 pr_crit("could not find Integrator/AP system controller\n");
190 static const char * ap_dt_board_compat[] = {
195 DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
196 .reserve = integrator_reserve,
198 .init_early = ap_init_early,
199 .init_irq = ap_init_irq_of,
200 .init_machine = ap_init_of,
201 .dt_compat = ap_dt_board_compat,