arch/arm/mach-imx/mach-imx6sx.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright 2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <linux/irqchip.h>
   7 #include <linux/of_platform.h>
   8 #include <linux/phy.h>
   9 #include <linux/regmap.h>
  10 #include <linux/mfd/syscon.h>
  11 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  12 #include <asm/mach/arch.h>
  13 #include <asm/mach/map.h>
  14
  15 #include "common.h"
  16 #include "cpuidle.h"
  17
  18 static int ar8031_phy_fixup(struct phy_device *dev)
  19 {
  20         u16 val;
  21
  22         /* Set RGMII IO voltage to 1.8V */
  23         phy_write(dev, 0x1d, 0x1f);
  24         phy_write(dev, 0x1e, 0x8);
  25
  26         /* introduce tx clock delay */
  27         phy_write(dev, 0x1d, 0x5);
  28         val = phy_read(dev, 0x1e);
  29         val |= 0x0100;
  30         phy_write(dev, 0x1e, val);
  31
  32         return 0;
  33 }
  34
  35 #define PHY_ID_AR8031   0x004dd074
  36 static void __init imx6sx_enet_phy_init(void)
  37 {
  38         if (IS_BUILTIN(CONFIG_PHYLIB))
  39                 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
  40                                            ar8031_phy_fixup);
  41 }
  42
  43 static void __init imx6sx_enet_clk_sel(void)
  44 {
  45         struct regmap *gpr;
  46
  47         gpr = syscon_regmap_lookup_by_compatible("fsl,imx6sx-iomuxc-gpr");
  48         if (!IS_ERR(gpr)) {
  49                 regmap_update_bits(gpr, IOMUXC_GPR1,
  50                                    IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK, 0);
  51                 regmap_update_bits(gpr, IOMUXC_GPR1,
  52                                    IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK, 0);
  53         } else {
  54                 pr_err("failed to find fsl,imx6sx-iomux-gpr regmap\n");
  55         }
  56 }
  57
  58 static inline void imx6sx_enet_init(void)
  59 {
  60         imx6sx_enet_phy_init();
  61         imx6sx_enet_clk_sel();
  62 }
  63
  64 static void __init imx6sx_init_machine(void)
  65 {
  66         of_platform_default_populate(NULL, NULL, NULL);
  67
  68         imx6sx_enet_init();
  69         imx_anatop_init();
  70         imx6sx_pm_init();
  71 }
  72
  73 static void __init imx6sx_init_irq(void)
  74 {
  75         imx_gpc_check_dt();
  76         imx_init_revision_from_anatop();
  77         imx_init_l2cache();
  78         imx_src_init();
  79         irqchip_init();
  80         imx6_pm_ccm_init("fsl,imx6sx-ccm");
  81 }
  82
  83 static void __init imx6sx_init_late(void)
  84 {
  85         imx6sx_cpuidle_init();
  86
  87         if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
  88                 platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
  89 }
  90
  91 static const char * const imx6sx_dt_compat[] __initconst = {
  92         "fsl,imx6sx",
  93         NULL,
  94 };
  95
  96 DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
  97         .l2c_aux_val    = 0,
  98         .l2c_aux_mask   = ~0,
  99         .init_irq       = imx6sx_init_irq,
 100         .init_machine   = imx6sx_init_machine,
 101         .dt_compat      = imx6sx_dt_compat,
 102         .init_late      = imx6sx_init_late,
 103 MACHINE_END