1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013 Linaro Ltd.
4 * Copyright (c) 2013 Hisilicon Limited.
8 #include <linux/delay.h>
10 #include <linux/of_address.h>
11 #include <linux/of_platform.h>
12 #include <asm/cacheflush.h>
13 #include <asm/smp_plat.h>
16 /* Sysctrl registers in Hi3620 SoC */
19 #define SCPERPWREN 0xd0
20 #define SCPERPWRDIS 0xd4
21 #define SCCPUCOREEN 0xf4
22 #define SCCPUCOREDIS 0xf8
23 #define SCPERCTRL0 0x200
24 #define SCCPURSTEN 0x410
25 #define SCCPURSTDIS 0x414
28 * bit definition in SCISOEN/SCPERPWREN/...
30 * CPU2_ISO_CTRL (1 << 5)
31 * CPU3_ISO_CTRL (1 << 6)
34 #define CPU2_ISO_CTRL (1 << 5)
37 * bit definition in SCPERCTRL0
39 * CPU0_WFI_MASK_CFG (1 << 28)
40 * CPU1_WFI_MASK_CFG (1 << 29)
43 #define CPU0_WFI_MASK_CFG (1 << 28)
46 * bit definition in SCCPURSTEN/...
48 * CPU0_SRST_REQ_EN (1 << 0)
49 * CPU1_SRST_REQ_EN (1 << 1)
52 #define CPU0_HPM_SRST_REQ_EN (1 << 22)
53 #define CPU0_DBG_SRST_REQ_EN (1 << 12)
54 #define CPU0_NEON_SRST_REQ_EN (1 << 4)
55 #define CPU0_SRST_REQ_EN (1 << 0)
57 #define HIX5HD2_PERI_CRG20 0x50
58 #define CRG20_CPU1_RESET (1 << 17)
60 #define HIX5HD2_PERI_PMC0 0x1000
61 #define PMC0_CPU1_WAIT_MTCOMS_ACK (1 << 8)
62 #define PMC0_CPU1_PMC_ENABLE (1 << 7)
63 #define PMC0_CPU1_POWERDOWN (1 << 3)
65 #define HIP01_PERI9 0x50
66 #define PERI9_CPU1_RESET (1 << 1)
73 static void __iomem *ctrl_base;
76 static void set_cpu_hi3620(int cpu, bool enable)
82 if ((cpu == 2) || (cpu == 3))
83 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
84 ctrl_base + SCPERPWREN);
88 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN);
91 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
93 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
95 val |= CPU0_HPM_SRST_REQ_EN;
96 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
99 if ((cpu == 2) || (cpu == 3))
100 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
101 ctrl_base + SCISODIS);
105 val = readl_relaxed(ctrl_base + SCPERCTRL0);
106 val &= ~(CPU0_WFI_MASK_CFG << cpu);
107 writel_relaxed(val, ctrl_base + SCPERCTRL0);
110 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
111 | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
112 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS);
115 val = readl_relaxed(ctrl_base + SCPERCTRL0);
116 val |= (CPU0_WFI_MASK_CFG << cpu);
117 writel_relaxed(val, ctrl_base + SCPERCTRL0);
120 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS);
122 if ((cpu == 2) || (cpu == 3)) {
124 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
125 ctrl_base + SCISOEN);
130 val = CPU0_DBG_SRST_REQ_EN | CPU0_NEON_SRST_REQ_EN
131 | CPU0_SRST_REQ_EN | CPU0_HPM_SRST_REQ_EN;
132 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN);
134 if ((cpu == 2) || (cpu == 3)) {
136 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2),
137 ctrl_base + SCPERPWRDIS);
143 static int hi3xxx_hotplug_init(void)
145 struct device_node *node;
147 node = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl");
153 ctrl_base = of_iomap(node, 0);
164 void hi3xxx_set_cpu(int cpu, bool enable)
167 if (hi3xxx_hotplug_init() < 0)
171 if (id == HI3620_CTRL)
172 set_cpu_hi3620(cpu, enable);
175 static bool hix5hd2_hotplug_init(void)
177 struct device_node *np;
179 np = of_find_compatible_node(NULL, NULL, "hisilicon,cpuctrl");
183 ctrl_base = of_iomap(np, 0);
191 void hix5hd2_set_cpu(int cpu, bool enable)
196 if (!hix5hd2_hotplug_init())
201 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
202 val &= ~(PMC0_CPU1_WAIT_MTCOMS_ACK | PMC0_CPU1_POWERDOWN);
203 val |= PMC0_CPU1_PMC_ENABLE;
204 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
206 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
207 val &= ~CRG20_CPU1_RESET;
208 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
210 /* power down cpu1 */
211 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_PMC0);
212 val |= PMC0_CPU1_PMC_ENABLE | PMC0_CPU1_POWERDOWN;
213 val &= ~PMC0_CPU1_WAIT_MTCOMS_ACK;
214 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_PMC0);
217 val = readl_relaxed(ctrl_base + HIX5HD2_PERI_CRG20);
218 val |= CRG20_CPU1_RESET;
219 writel_relaxed(val, ctrl_base + HIX5HD2_PERI_CRG20);
223 void hip01_set_cpu(int cpu, bool enable)
226 struct device_node *np;
229 np = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
231 ctrl_base = of_iomap(np, 0);
238 temp = readl_relaxed(ctrl_base + HIP01_PERI9);
239 temp |= PERI9_CPU1_RESET;
240 writel_relaxed(temp, ctrl_base + HIP01_PERI9);
244 /* unreset on CPU1 */
245 temp = readl_relaxed(ctrl_base + HIP01_PERI9);
246 temp &= ~PERI9_CPU1_RESET;
247 writel_relaxed(temp, ctrl_base + HIP01_PERI9);
251 static inline void cpu_enter_lowpower(void)
258 * Turn off coherency and L1 D-cache
261 " mrc p15, 0, %0, c1, c0, 1\n"
262 " bic %0, %0, #0x40\n"
263 " mcr p15, 0, %0, c1, c0, 1\n"
264 " mrc p15, 0, %0, c1, c0, 0\n"
265 " bic %0, %0, #0x04\n"
266 " mcr p15, 0, %0, c1, c0, 0\n"
272 #ifdef CONFIG_HOTPLUG_CPU
273 void hi3xxx_cpu_die(unsigned int cpu)
275 cpu_enter_lowpower();
276 hi3xxx_set_cpu_jump(cpu, phys_to_virt(0));
279 /* We should have never returned from idle */
280 panic("cpu %d unexpectedly exit from shutdown\n", cpu);
283 int hi3xxx_cpu_kill(unsigned int cpu)
285 unsigned long timeout = jiffies + msecs_to_jiffies(50);
287 while (hi3xxx_get_cpu_jump(cpu))
288 if (time_after(jiffies, timeout))
290 hi3xxx_set_cpu(cpu, false);
294 void hix5hd2_cpu_die(unsigned int cpu)
297 hix5hd2_set_cpu(cpu, false);