1 /* linux/arch/arm/mach-exynos4/clock.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * EXYNOS4 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/err.h>
16 #include <linux/syscore_ops.h>
18 #include <plat/cpu-freq.h>
19 #include <plat/clock.h>
22 #include <plat/s5p-clock.h>
23 #include <plat/clock-clksrc.h>
27 #include <mach/regs-clock.h>
28 #include <mach/sysmmu.h>
29 #include <mach/exynos4-clock.h>
33 static struct sleep_save exynos4_clock_save[] = {
34 SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
35 SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
36 SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
37 SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
38 SAVE_ITEM(S5P_CLKSRC_TOP0),
39 SAVE_ITEM(S5P_CLKSRC_TOP1),
40 SAVE_ITEM(S5P_CLKSRC_CAM),
41 SAVE_ITEM(S5P_CLKSRC_TV),
42 SAVE_ITEM(S5P_CLKSRC_MFC),
43 SAVE_ITEM(S5P_CLKSRC_G3D),
44 SAVE_ITEM(S5P_CLKSRC_LCD0),
45 SAVE_ITEM(S5P_CLKSRC_MAUDIO),
46 SAVE_ITEM(S5P_CLKSRC_FSYS),
47 SAVE_ITEM(S5P_CLKSRC_PERIL0),
48 SAVE_ITEM(S5P_CLKSRC_PERIL1),
49 SAVE_ITEM(S5P_CLKDIV_CAM),
50 SAVE_ITEM(S5P_CLKDIV_TV),
51 SAVE_ITEM(S5P_CLKDIV_MFC),
52 SAVE_ITEM(S5P_CLKDIV_G3D),
53 SAVE_ITEM(S5P_CLKDIV_LCD0),
54 SAVE_ITEM(S5P_CLKDIV_MAUDIO),
55 SAVE_ITEM(S5P_CLKDIV_FSYS0),
56 SAVE_ITEM(S5P_CLKDIV_FSYS1),
57 SAVE_ITEM(S5P_CLKDIV_FSYS2),
58 SAVE_ITEM(S5P_CLKDIV_FSYS3),
59 SAVE_ITEM(S5P_CLKDIV_PERIL0),
60 SAVE_ITEM(S5P_CLKDIV_PERIL1),
61 SAVE_ITEM(S5P_CLKDIV_PERIL2),
62 SAVE_ITEM(S5P_CLKDIV_PERIL3),
63 SAVE_ITEM(S5P_CLKDIV_PERIL4),
64 SAVE_ITEM(S5P_CLKDIV_PERIL5),
65 SAVE_ITEM(S5P_CLKDIV_TOP),
66 SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
67 SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
68 SAVE_ITEM(S5P_CLKSRC_MASK_TV),
69 SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
70 SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
71 SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
72 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
73 SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
74 SAVE_ITEM(S5P_CLKDIV2_RATIO),
75 SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
76 SAVE_ITEM(S5P_CLKGATE_IP_CAM),
77 SAVE_ITEM(S5P_CLKGATE_IP_TV),
78 SAVE_ITEM(S5P_CLKGATE_IP_MFC),
79 SAVE_ITEM(S5P_CLKGATE_IP_G3D),
80 SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
81 SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
82 SAVE_ITEM(S5P_CLKGATE_IP_GPS),
83 SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
84 SAVE_ITEM(S5P_CLKGATE_BLOCK),
85 SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
86 SAVE_ITEM(S5P_CLKSRC_DMC),
87 SAVE_ITEM(S5P_CLKDIV_DMC0),
88 SAVE_ITEM(S5P_CLKDIV_DMC1),
89 SAVE_ITEM(S5P_CLKGATE_IP_DMC),
90 SAVE_ITEM(S5P_CLKSRC_CPU),
91 SAVE_ITEM(S5P_CLKDIV_CPU),
92 SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
93 SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
94 SAVE_ITEM(S5P_CLKGATE_IP_CPU),
97 struct clk clk_sclk_hdmi27m = {
98 .name = "sclk_hdmi27m",
102 struct clk clk_sclk_hdmiphy = {
103 .name = "sclk_hdmiphy",
106 struct clk clk_sclk_usbphy0 = {
107 .name = "sclk_usbphy0",
111 struct clk clk_sclk_usbphy1 = {
112 .name = "sclk_usbphy1",
115 static struct clk dummy_apb_pclk = {
120 static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
122 return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
125 static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
127 return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
130 static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
132 return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
135 int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
137 return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
140 static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
142 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
145 static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
147 return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
150 static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
152 return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
155 static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
157 return s5p_gatectrl(S5P_CLKSRC_MASK_TV, clk, enable);
160 static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
162 return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
165 static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
167 return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
170 static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
172 return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
175 static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
177 return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
180 int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
182 return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
185 int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
187 return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
190 static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
192 return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
195 static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
197 return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
200 static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
202 return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
205 static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
207 return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
210 /* Core list of CMU_CPU side */
212 static struct clksrc_clk clk_mout_apll = {
216 .sources = &clk_src_apll,
217 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
220 struct clksrc_clk clk_sclk_apll = {
223 .parent = &clk_mout_apll.clk,
225 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
228 struct clksrc_clk clk_mout_epll = {
232 .sources = &clk_src_epll,
233 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
236 struct clksrc_clk clk_mout_mpll = {
240 .sources = &clk_src_mpll,
242 /* reg_src will be added in each SoCs' clock */
245 static struct clk *clkset_moutcore_list[] = {
246 [0] = &clk_mout_apll.clk,
247 [1] = &clk_mout_mpll.clk,
250 static struct clksrc_sources clkset_moutcore = {
251 .sources = clkset_moutcore_list,
252 .nr_sources = ARRAY_SIZE(clkset_moutcore_list),
255 static struct clksrc_clk clk_moutcore = {
259 .sources = &clkset_moutcore,
260 .reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
263 static struct clksrc_clk clk_coreclk = {
266 .parent = &clk_moutcore.clk,
268 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
271 static struct clksrc_clk clk_armclk = {
274 .parent = &clk_coreclk.clk,
278 static struct clksrc_clk clk_aclk_corem0 = {
280 .name = "aclk_corem0",
281 .parent = &clk_coreclk.clk,
283 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
286 static struct clksrc_clk clk_aclk_cores = {
288 .name = "aclk_cores",
289 .parent = &clk_coreclk.clk,
291 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
294 static struct clksrc_clk clk_aclk_corem1 = {
296 .name = "aclk_corem1",
297 .parent = &clk_coreclk.clk,
299 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
302 static struct clksrc_clk clk_periphclk = {
305 .parent = &clk_coreclk.clk,
307 .reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
310 /* Core list of CMU_CORE side */
312 struct clk *clkset_corebus_list[] = {
313 [0] = &clk_mout_mpll.clk,
314 [1] = &clk_sclk_apll.clk,
317 struct clksrc_sources clkset_mout_corebus = {
318 .sources = clkset_corebus_list,
319 .nr_sources = ARRAY_SIZE(clkset_corebus_list),
322 static struct clksrc_clk clk_mout_corebus = {
324 .name = "mout_corebus",
326 .sources = &clkset_mout_corebus,
327 .reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
330 static struct clksrc_clk clk_sclk_dmc = {
333 .parent = &clk_mout_corebus.clk,
335 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
338 static struct clksrc_clk clk_aclk_cored = {
340 .name = "aclk_cored",
341 .parent = &clk_sclk_dmc.clk,
343 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
346 static struct clksrc_clk clk_aclk_corep = {
348 .name = "aclk_corep",
349 .parent = &clk_aclk_cored.clk,
351 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
354 static struct clksrc_clk clk_aclk_acp = {
357 .parent = &clk_mout_corebus.clk,
359 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
362 static struct clksrc_clk clk_pclk_acp = {
365 .parent = &clk_aclk_acp.clk,
367 .reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
370 /* Core list of CMU_TOP side */
372 struct clk *clkset_aclk_top_list[] = {
373 [0] = &clk_mout_mpll.clk,
374 [1] = &clk_sclk_apll.clk,
377 struct clksrc_sources clkset_aclk = {
378 .sources = clkset_aclk_top_list,
379 .nr_sources = ARRAY_SIZE(clkset_aclk_top_list),
382 static struct clksrc_clk clk_aclk_200 = {
386 .sources = &clkset_aclk,
387 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
388 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
391 static struct clksrc_clk clk_aclk_100 = {
395 .sources = &clkset_aclk,
396 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
397 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
400 static struct clksrc_clk clk_aclk_160 = {
404 .sources = &clkset_aclk,
405 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
406 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
409 struct clksrc_clk clk_aclk_133 = {
413 .sources = &clkset_aclk,
414 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
415 .reg_div = { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
418 static struct clk *clkset_vpllsrc_list[] = {
420 [1] = &clk_sclk_hdmi27m,
423 static struct clksrc_sources clkset_vpllsrc = {
424 .sources = clkset_vpllsrc_list,
425 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
428 static struct clksrc_clk clk_vpllsrc = {
431 .enable = exynos4_clksrc_mask_top_ctrl,
434 .sources = &clkset_vpllsrc,
435 .reg_src = { .reg = S5P_CLKSRC_TOP1, .shift = 0, .size = 1 },
438 static struct clk *clkset_sclk_vpll_list[] = {
439 [0] = &clk_vpllsrc.clk,
440 [1] = &clk_fout_vpll,
443 static struct clksrc_sources clkset_sclk_vpll = {
444 .sources = clkset_sclk_vpll_list,
445 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
448 struct clksrc_clk clk_sclk_vpll = {
452 .sources = &clkset_sclk_vpll,
453 .reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
456 static struct clk init_clocks_off[] = {
459 .parent = &clk_aclk_100.clk,
460 .enable = exynos4_clk_ip_peril_ctrl,
464 .devname = "s5p-mipi-csis.0",
465 .enable = exynos4_clk_ip_cam_ctrl,
469 .devname = "s5p-mipi-csis.1",
470 .enable = exynos4_clk_ip_cam_ctrl,
474 .devname = "exynos4-fimc.0",
475 .enable = exynos4_clk_ip_cam_ctrl,
479 .devname = "exynos4-fimc.1",
480 .enable = exynos4_clk_ip_cam_ctrl,
484 .devname = "exynos4-fimc.2",
485 .enable = exynos4_clk_ip_cam_ctrl,
489 .devname = "exynos4-fimc.3",
490 .enable = exynos4_clk_ip_cam_ctrl,
494 .devname = "exynos4-fb.0",
495 .enable = exynos4_clk_ip_lcd0_ctrl,
499 .devname = "s3c-sdhci.0",
500 .parent = &clk_aclk_133.clk,
501 .enable = exynos4_clk_ip_fsys_ctrl,
505 .devname = "s3c-sdhci.1",
506 .parent = &clk_aclk_133.clk,
507 .enable = exynos4_clk_ip_fsys_ctrl,
511 .devname = "s3c-sdhci.2",
512 .parent = &clk_aclk_133.clk,
513 .enable = exynos4_clk_ip_fsys_ctrl,
517 .devname = "s3c-sdhci.3",
518 .parent = &clk_aclk_133.clk,
519 .enable = exynos4_clk_ip_fsys_ctrl,
523 .parent = &clk_aclk_133.clk,
524 .enable = exynos4_clk_ip_fsys_ctrl,
528 .devname = "s5p-sdo",
529 .enable = exynos4_clk_ip_tv_ctrl,
533 .devname = "s5p-mixer",
534 .enable = exynos4_clk_ip_tv_ctrl,
538 .devname = "s5p-mixer",
539 .enable = exynos4_clk_ip_tv_ctrl,
543 .devname = "exynos4-hdmi",
544 .enable = exynos4_clk_ip_tv_ctrl,
548 .devname = "exynos4-hdmi",
549 .enable = exynos4_clk_hdmiphy_ctrl,
553 .devname = "s5p-sdo",
554 .enable = exynos4_clk_dac_ctrl,
558 .enable = exynos4_clk_ip_peril_ctrl,
559 .ctrlbit = (1 << 15),
562 .enable = exynos4_clk_ip_perir_ctrl,
563 .ctrlbit = (1 << 16),
566 .enable = exynos4_clk_ip_perir_ctrl,
567 .ctrlbit = (1 << 15),
570 .parent = &clk_aclk_100.clk,
571 .enable = exynos4_clk_ip_perir_ctrl,
572 .ctrlbit = (1 << 14),
575 .enable = exynos4_clk_ip_fsys_ctrl ,
576 .ctrlbit = (1 << 12),
579 .enable = exynos4_clk_ip_fsys_ctrl,
580 .ctrlbit = (1 << 13),
583 .devname = "s3c64xx-spi.0",
584 .enable = exynos4_clk_ip_peril_ctrl,
585 .ctrlbit = (1 << 16),
588 .devname = "s3c64xx-spi.1",
589 .enable = exynos4_clk_ip_peril_ctrl,
590 .ctrlbit = (1 << 17),
593 .devname = "s3c64xx-spi.2",
594 .enable = exynos4_clk_ip_peril_ctrl,
595 .ctrlbit = (1 << 18),
598 .devname = "samsung-i2s.0",
599 .enable = exynos4_clk_ip_peril_ctrl,
600 .ctrlbit = (1 << 19),
603 .devname = "samsung-i2s.1",
604 .enable = exynos4_clk_ip_peril_ctrl,
605 .ctrlbit = (1 << 20),
608 .devname = "samsung-i2s.2",
609 .enable = exynos4_clk_ip_peril_ctrl,
610 .ctrlbit = (1 << 21),
613 .devname = "samsung-ac97",
614 .enable = exynos4_clk_ip_peril_ctrl,
615 .ctrlbit = (1 << 27),
618 .enable = exynos4_clk_ip_image_ctrl,
622 .devname = "s5p-mfc",
623 .enable = exynos4_clk_ip_mfc_ctrl,
627 .devname = "s3c2440-i2c.0",
628 .parent = &clk_aclk_100.clk,
629 .enable = exynos4_clk_ip_peril_ctrl,
633 .devname = "s3c2440-i2c.1",
634 .parent = &clk_aclk_100.clk,
635 .enable = exynos4_clk_ip_peril_ctrl,
639 .devname = "s3c2440-i2c.2",
640 .parent = &clk_aclk_100.clk,
641 .enable = exynos4_clk_ip_peril_ctrl,
645 .devname = "s3c2440-i2c.3",
646 .parent = &clk_aclk_100.clk,
647 .enable = exynos4_clk_ip_peril_ctrl,
651 .devname = "s3c2440-i2c.4",
652 .parent = &clk_aclk_100.clk,
653 .enable = exynos4_clk_ip_peril_ctrl,
654 .ctrlbit = (1 << 10),
657 .devname = "s3c2440-i2c.5",
658 .parent = &clk_aclk_100.clk,
659 .enable = exynos4_clk_ip_peril_ctrl,
660 .ctrlbit = (1 << 11),
663 .devname = "s3c2440-i2c.6",
664 .parent = &clk_aclk_100.clk,
665 .enable = exynos4_clk_ip_peril_ctrl,
666 .ctrlbit = (1 << 12),
669 .devname = "s3c2440-i2c.7",
670 .parent = &clk_aclk_100.clk,
671 .enable = exynos4_clk_ip_peril_ctrl,
672 .ctrlbit = (1 << 13),
675 .devname = "s3c2440-hdmiphy-i2c",
676 .parent = &clk_aclk_100.clk,
677 .enable = exynos4_clk_ip_peril_ctrl,
678 .ctrlbit = (1 << 14),
680 .name = "SYSMMU_MDMA",
681 .enable = exynos4_clk_ip_image_ctrl,
684 .name = "SYSMMU_FIMC0",
685 .enable = exynos4_clk_ip_cam_ctrl,
688 .name = "SYSMMU_FIMC1",
689 .enable = exynos4_clk_ip_cam_ctrl,
692 .name = "SYSMMU_FIMC2",
693 .enable = exynos4_clk_ip_cam_ctrl,
696 .name = "SYSMMU_FIMC3",
697 .enable = exynos4_clk_ip_cam_ctrl,
698 .ctrlbit = (1 << 10),
700 .name = "SYSMMU_JPEG",
701 .enable = exynos4_clk_ip_cam_ctrl,
702 .ctrlbit = (1 << 11),
704 .name = "SYSMMU_FIMD0",
705 .enable = exynos4_clk_ip_lcd0_ctrl,
708 .name = "SYSMMU_FIMD1",
709 .enable = exynos4_clk_ip_lcd1_ctrl,
712 .name = "SYSMMU_PCIe",
713 .enable = exynos4_clk_ip_fsys_ctrl,
714 .ctrlbit = (1 << 18),
716 .name = "SYSMMU_G2D",
717 .enable = exynos4_clk_ip_image_ctrl,
720 .name = "SYSMMU_ROTATOR",
721 .enable = exynos4_clk_ip_image_ctrl,
725 .enable = exynos4_clk_ip_tv_ctrl,
728 .name = "SYSMMU_MFC_L",
729 .enable = exynos4_clk_ip_mfc_ctrl,
732 .name = "SYSMMU_MFC_R",
733 .enable = exynos4_clk_ip_mfc_ctrl,
738 static struct clk init_clocks[] = {
741 .devname = "s5pv210-uart.0",
742 .enable = exynos4_clk_ip_peril_ctrl,
746 .devname = "s5pv210-uart.1",
747 .enable = exynos4_clk_ip_peril_ctrl,
751 .devname = "s5pv210-uart.2",
752 .enable = exynos4_clk_ip_peril_ctrl,
756 .devname = "s5pv210-uart.3",
757 .enable = exynos4_clk_ip_peril_ctrl,
761 .devname = "s5pv210-uart.4",
762 .enable = exynos4_clk_ip_peril_ctrl,
766 .devname = "s5pv210-uart.5",
767 .enable = exynos4_clk_ip_peril_ctrl,
772 static struct clk clk_pdma0 = {
774 .devname = "dma-pl330.0",
775 .enable = exynos4_clk_ip_fsys_ctrl,
779 static struct clk clk_pdma1 = {
781 .devname = "dma-pl330.1",
782 .enable = exynos4_clk_ip_fsys_ctrl,
786 struct clk *clkset_group_list[] = {
787 [0] = &clk_ext_xtal_mux,
789 [2] = &clk_sclk_hdmi27m,
790 [3] = &clk_sclk_usbphy0,
791 [4] = &clk_sclk_usbphy1,
792 [5] = &clk_sclk_hdmiphy,
793 [6] = &clk_mout_mpll.clk,
794 [7] = &clk_mout_epll.clk,
795 [8] = &clk_sclk_vpll.clk,
798 struct clksrc_sources clkset_group = {
799 .sources = clkset_group_list,
800 .nr_sources = ARRAY_SIZE(clkset_group_list),
803 static struct clk *clkset_mout_g2d0_list[] = {
804 [0] = &clk_mout_mpll.clk,
805 [1] = &clk_sclk_apll.clk,
808 static struct clksrc_sources clkset_mout_g2d0 = {
809 .sources = clkset_mout_g2d0_list,
810 .nr_sources = ARRAY_SIZE(clkset_mout_g2d0_list),
813 static struct clksrc_clk clk_mout_g2d0 = {
817 .sources = &clkset_mout_g2d0,
818 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
821 static struct clk *clkset_mout_g2d1_list[] = {
822 [0] = &clk_mout_epll.clk,
823 [1] = &clk_sclk_vpll.clk,
826 static struct clksrc_sources clkset_mout_g2d1 = {
827 .sources = clkset_mout_g2d1_list,
828 .nr_sources = ARRAY_SIZE(clkset_mout_g2d1_list),
831 static struct clksrc_clk clk_mout_g2d1 = {
835 .sources = &clkset_mout_g2d1,
836 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
839 static struct clk *clkset_mout_g2d_list[] = {
840 [0] = &clk_mout_g2d0.clk,
841 [1] = &clk_mout_g2d1.clk,
844 static struct clksrc_sources clkset_mout_g2d = {
845 .sources = clkset_mout_g2d_list,
846 .nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
849 static struct clk *clkset_mout_mfc0_list[] = {
850 [0] = &clk_mout_mpll.clk,
851 [1] = &clk_sclk_apll.clk,
854 static struct clksrc_sources clkset_mout_mfc0 = {
855 .sources = clkset_mout_mfc0_list,
856 .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
859 static struct clksrc_clk clk_mout_mfc0 = {
863 .sources = &clkset_mout_mfc0,
864 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
867 static struct clk *clkset_mout_mfc1_list[] = {
868 [0] = &clk_mout_epll.clk,
869 [1] = &clk_sclk_vpll.clk,
872 static struct clksrc_sources clkset_mout_mfc1 = {
873 .sources = clkset_mout_mfc1_list,
874 .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
877 static struct clksrc_clk clk_mout_mfc1 = {
881 .sources = &clkset_mout_mfc1,
882 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
885 static struct clk *clkset_mout_mfc_list[] = {
886 [0] = &clk_mout_mfc0.clk,
887 [1] = &clk_mout_mfc1.clk,
890 static struct clksrc_sources clkset_mout_mfc = {
891 .sources = clkset_mout_mfc_list,
892 .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
895 static struct clk *clkset_sclk_dac_list[] = {
896 [0] = &clk_sclk_vpll.clk,
897 [1] = &clk_sclk_hdmiphy,
900 static struct clksrc_sources clkset_sclk_dac = {
901 .sources = clkset_sclk_dac_list,
902 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
905 static struct clksrc_clk clk_sclk_dac = {
908 .enable = exynos4_clksrc_mask_tv_ctrl,
911 .sources = &clkset_sclk_dac,
912 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 8, .size = 1 },
915 static struct clksrc_clk clk_sclk_pixel = {
917 .name = "sclk_pixel",
918 .parent = &clk_sclk_vpll.clk,
920 .reg_div = { .reg = S5P_CLKDIV_TV, .shift = 0, .size = 4 },
923 static struct clk *clkset_sclk_hdmi_list[] = {
924 [0] = &clk_sclk_pixel.clk,
925 [1] = &clk_sclk_hdmiphy,
928 static struct clksrc_sources clkset_sclk_hdmi = {
929 .sources = clkset_sclk_hdmi_list,
930 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
933 static struct clksrc_clk clk_sclk_hdmi = {
936 .enable = exynos4_clksrc_mask_tv_ctrl,
939 .sources = &clkset_sclk_hdmi,
940 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 0, .size = 1 },
943 static struct clk *clkset_sclk_mixer_list[] = {
944 [0] = &clk_sclk_dac.clk,
945 [1] = &clk_sclk_hdmi.clk,
948 static struct clksrc_sources clkset_sclk_mixer = {
949 .sources = clkset_sclk_mixer_list,
950 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
953 static struct clksrc_clk clk_sclk_mixer = {
955 .name = "sclk_mixer",
956 .enable = exynos4_clksrc_mask_tv_ctrl,
959 .sources = &clkset_sclk_mixer,
960 .reg_src = { .reg = S5P_CLKSRC_TV, .shift = 4, .size = 1 },
963 static struct clksrc_clk *sclk_tv[] = {
970 static struct clksrc_clk clk_dout_mmc0 = {
974 .sources = &clkset_group,
975 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
976 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 0, .size = 4 },
979 static struct clksrc_clk clk_dout_mmc1 = {
983 .sources = &clkset_group,
984 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
985 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 16, .size = 4 },
988 static struct clksrc_clk clk_dout_mmc2 = {
992 .sources = &clkset_group,
993 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
994 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 0, .size = 4 },
997 static struct clksrc_clk clk_dout_mmc3 = {
1001 .sources = &clkset_group,
1002 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
1003 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 16, .size = 4 },
1006 static struct clksrc_clk clk_dout_mmc4 = {
1008 .name = "dout_mmc4",
1010 .sources = &clkset_group,
1011 .reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
1012 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 0, .size = 4 },
1015 static struct clksrc_clk clksrcs[] = {
1019 .enable = exynos4_clksrc_mask_peril0_ctrl,
1020 .ctrlbit = (1 << 24),
1022 .sources = &clkset_group,
1023 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
1024 .reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
1027 .name = "sclk_csis",
1028 .devname = "s5p-mipi-csis.0",
1029 .enable = exynos4_clksrc_mask_cam_ctrl,
1030 .ctrlbit = (1 << 24),
1032 .sources = &clkset_group,
1033 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 24, .size = 4 },
1034 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 24, .size = 4 },
1037 .name = "sclk_csis",
1038 .devname = "s5p-mipi-csis.1",
1039 .enable = exynos4_clksrc_mask_cam_ctrl,
1040 .ctrlbit = (1 << 28),
1042 .sources = &clkset_group,
1043 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 28, .size = 4 },
1044 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 28, .size = 4 },
1047 .name = "sclk_cam0",
1048 .enable = exynos4_clksrc_mask_cam_ctrl,
1049 .ctrlbit = (1 << 16),
1051 .sources = &clkset_group,
1052 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 16, .size = 4 },
1053 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 16, .size = 4 },
1056 .name = "sclk_cam1",
1057 .enable = exynos4_clksrc_mask_cam_ctrl,
1058 .ctrlbit = (1 << 20),
1060 .sources = &clkset_group,
1061 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 20, .size = 4 },
1062 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 20, .size = 4 },
1065 .name = "sclk_fimc",
1066 .devname = "exynos4-fimc.0",
1067 .enable = exynos4_clksrc_mask_cam_ctrl,
1068 .ctrlbit = (1 << 0),
1070 .sources = &clkset_group,
1071 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 0, .size = 4 },
1072 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 0, .size = 4 },
1075 .name = "sclk_fimc",
1076 .devname = "exynos4-fimc.1",
1077 .enable = exynos4_clksrc_mask_cam_ctrl,
1078 .ctrlbit = (1 << 4),
1080 .sources = &clkset_group,
1081 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 4, .size = 4 },
1082 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 4, .size = 4 },
1085 .name = "sclk_fimc",
1086 .devname = "exynos4-fimc.2",
1087 .enable = exynos4_clksrc_mask_cam_ctrl,
1088 .ctrlbit = (1 << 8),
1090 .sources = &clkset_group,
1091 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 8, .size = 4 },
1092 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 8, .size = 4 },
1095 .name = "sclk_fimc",
1096 .devname = "exynos4-fimc.3",
1097 .enable = exynos4_clksrc_mask_cam_ctrl,
1098 .ctrlbit = (1 << 12),
1100 .sources = &clkset_group,
1101 .reg_src = { .reg = S5P_CLKSRC_CAM, .shift = 12, .size = 4 },
1102 .reg_div = { .reg = S5P_CLKDIV_CAM, .shift = 12, .size = 4 },
1105 .name = "sclk_fimd",
1106 .devname = "exynos4-fb.0",
1107 .enable = exynos4_clksrc_mask_lcd0_ctrl,
1108 .ctrlbit = (1 << 0),
1110 .sources = &clkset_group,
1111 .reg_src = { .reg = S5P_CLKSRC_LCD0, .shift = 0, .size = 4 },
1112 .reg_div = { .reg = S5P_CLKDIV_LCD0, .shift = 0, .size = 4 },
1115 .name = "sclk_fimg2d",
1117 .sources = &clkset_mout_g2d,
1118 .reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
1119 .reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
1123 .devname = "s5p-mfc",
1125 .sources = &clkset_mout_mfc,
1126 .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
1127 .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
1130 .name = "sclk_dwmmc",
1131 .parent = &clk_dout_mmc4.clk,
1132 .enable = exynos4_clksrc_mask_fsys_ctrl,
1133 .ctrlbit = (1 << 16),
1135 .reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
1139 static struct clksrc_clk clk_sclk_uart0 = {
1142 .devname = "exynos4210-uart.0",
1143 .enable = exynos4_clksrc_mask_peril0_ctrl,
1144 .ctrlbit = (1 << 0),
1146 .sources = &clkset_group,
1147 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
1148 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
1151 static struct clksrc_clk clk_sclk_uart1 = {
1154 .devname = "exynos4210-uart.1",
1155 .enable = exynos4_clksrc_mask_peril0_ctrl,
1156 .ctrlbit = (1 << 4),
1158 .sources = &clkset_group,
1159 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
1160 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
1163 static struct clksrc_clk clk_sclk_uart2 = {
1166 .devname = "exynos4210-uart.2",
1167 .enable = exynos4_clksrc_mask_peril0_ctrl,
1168 .ctrlbit = (1 << 8),
1170 .sources = &clkset_group,
1171 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
1172 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
1175 static struct clksrc_clk clk_sclk_uart3 = {
1178 .devname = "exynos4210-uart.3",
1179 .enable = exynos4_clksrc_mask_peril0_ctrl,
1180 .ctrlbit = (1 << 12),
1182 .sources = &clkset_group,
1183 .reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
1184 .reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
1187 static struct clksrc_clk clk_sclk_mmc0 = {
1190 .devname = "s3c-sdhci.0",
1191 .parent = &clk_dout_mmc0.clk,
1192 .enable = exynos4_clksrc_mask_fsys_ctrl,
1193 .ctrlbit = (1 << 0),
1195 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
1198 static struct clksrc_clk clk_sclk_mmc1 = {
1201 .devname = "s3c-sdhci.1",
1202 .parent = &clk_dout_mmc1.clk,
1203 .enable = exynos4_clksrc_mask_fsys_ctrl,
1204 .ctrlbit = (1 << 4),
1206 .reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
1209 static struct clksrc_clk clk_sclk_mmc2 = {
1212 .devname = "s3c-sdhci.2",
1213 .parent = &clk_dout_mmc2.clk,
1214 .enable = exynos4_clksrc_mask_fsys_ctrl,
1215 .ctrlbit = (1 << 8),
1217 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
1220 static struct clksrc_clk clk_sclk_mmc3 = {
1223 .devname = "s3c-sdhci.3",
1224 .parent = &clk_dout_mmc3.clk,
1225 .enable = exynos4_clksrc_mask_fsys_ctrl,
1226 .ctrlbit = (1 << 12),
1228 .reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
1231 static struct clksrc_clk clk_sclk_spi0 = {
1234 .devname = "s3c64xx-spi.0",
1235 .enable = exynos4_clksrc_mask_peril1_ctrl,
1236 .ctrlbit = (1 << 16),
1238 .sources = &clkset_group,
1239 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 16, .size = 4 },
1240 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 0, .size = 4 },
1243 static struct clksrc_clk clk_sclk_spi1 = {
1246 .devname = "s3c64xx-spi.1",
1247 .enable = exynos4_clksrc_mask_peril1_ctrl,
1248 .ctrlbit = (1 << 20),
1250 .sources = &clkset_group,
1251 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 20, .size = 4 },
1252 .reg_div = { .reg = S5P_CLKDIV_PERIL1, .shift = 16, .size = 4 },
1255 static struct clksrc_clk clk_sclk_spi2 = {
1258 .devname = "s3c64xx-spi.2",
1259 .enable = exynos4_clksrc_mask_peril1_ctrl,
1260 .ctrlbit = (1 << 24),
1262 .sources = &clkset_group,
1263 .reg_src = { .reg = S5P_CLKSRC_PERIL1, .shift = 24, .size = 4 },
1264 .reg_div = { .reg = S5P_CLKDIV_PERIL2, .shift = 0, .size = 4 },
1267 /* Clock initialization code */
1268 static struct clksrc_clk *sysclks[] = {
1301 static struct clk *clk_cdev[] = {
1306 static struct clksrc_clk *clksrc_cdev[] = {
1321 static struct clk_lookup exynos4_clk_lookup[] = {
1322 CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &clk_sclk_uart0.clk),
1323 CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &clk_sclk_uart1.clk),
1324 CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &clk_sclk_uart2.clk),
1325 CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &clk_sclk_uart3.clk),
1326 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1327 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1328 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1329 CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
1330 CLKDEV_INIT("dma-pl330.0", "apb_pclk", &clk_pdma0),
1331 CLKDEV_INIT("dma-pl330.1", "apb_pclk", &clk_pdma1),
1332 CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &clk_sclk_spi0.clk),
1333 CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &clk_sclk_spi1.clk),
1334 CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &clk_sclk_spi2.clk),
1337 static int xtal_rate;
1339 static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
1341 if (soc_is_exynos4210())
1342 return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0),
1344 else if (soc_is_exynos4212() || soc_is_exynos4412())
1345 return s5p_get_pll35xx(xtal_rate, __raw_readl(S5P_APLL_CON0));
1350 static struct clk_ops exynos4_fout_apll_ops = {
1351 .get_rate = exynos4_fout_apll_get_rate,
1354 static u32 vpll_div[][8] = {
1355 { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
1356 { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
1359 static unsigned long exynos4_vpll_get_rate(struct clk *clk)
1364 static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
1366 unsigned int vpll_con0, vpll_con1 = 0;
1369 /* Return if nothing changed */
1370 if (clk->rate == rate)
1373 vpll_con0 = __raw_readl(S5P_VPLL_CON0);
1374 vpll_con0 &= ~(0x1 << 27 | \
1375 PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
1376 PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
1377 PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1379 vpll_con1 = __raw_readl(S5P_VPLL_CON1);
1380 vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
1381 PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
1382 PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
1384 for (i = 0; i < ARRAY_SIZE(vpll_div); i++) {
1385 if (vpll_div[i][0] == rate) {
1386 vpll_con0 |= vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
1387 vpll_con0 |= vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
1388 vpll_con0 |= vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
1389 vpll_con1 |= vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
1390 vpll_con1 |= vpll_div[i][5] << PLL46XX_MFR_SHIFT;
1391 vpll_con1 |= vpll_div[i][6] << PLL46XX_MRR_SHIFT;
1392 vpll_con0 |= vpll_div[i][7] << 27;
1397 if (i == ARRAY_SIZE(vpll_div)) {
1398 printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
1403 __raw_writel(vpll_con0, S5P_VPLL_CON0);
1404 __raw_writel(vpll_con1, S5P_VPLL_CON1);
1406 /* Wait for VPLL lock */
1407 while (!(__raw_readl(S5P_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
1414 static struct clk_ops exynos4_vpll_ops = {
1415 .get_rate = exynos4_vpll_get_rate,
1416 .set_rate = exynos4_vpll_set_rate,
1419 void __init_or_cpufreq exynos4_setup_clocks(void)
1421 struct clk *xtal_clk;
1422 unsigned long apll = 0;
1423 unsigned long mpll = 0;
1424 unsigned long epll = 0;
1425 unsigned long vpll = 0;
1426 unsigned long vpllsrc;
1428 unsigned long armclk;
1429 unsigned long sclk_dmc;
1430 unsigned long aclk_200;
1431 unsigned long aclk_100;
1432 unsigned long aclk_160;
1433 unsigned long aclk_133;
1436 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1438 xtal_clk = clk_get(NULL, "xtal");
1439 BUG_ON(IS_ERR(xtal_clk));
1441 xtal = clk_get_rate(xtal_clk);
1447 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1449 if (soc_is_exynos4210()) {
1450 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0),
1452 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0),
1454 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
1455 __raw_readl(S5P_EPLL_CON1), pll_4600);
1457 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1458 vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1459 __raw_readl(S5P_VPLL_CON1), pll_4650c);
1460 } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
1461 apll = s5p_get_pll35xx(xtal, __raw_readl(S5P_APLL_CON0));
1462 mpll = s5p_get_pll35xx(xtal, __raw_readl(S5P_MPLL_CON0));
1463 epll = s5p_get_pll36xx(xtal, __raw_readl(S5P_EPLL_CON0),
1464 __raw_readl(S5P_EPLL_CON1));
1466 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1467 vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
1468 __raw_readl(S5P_VPLL_CON1));
1473 clk_fout_apll.ops = &exynos4_fout_apll_ops;
1474 clk_fout_mpll.rate = mpll;
1475 clk_fout_epll.rate = epll;
1476 clk_fout_vpll.ops = &exynos4_vpll_ops;
1477 clk_fout_vpll.rate = vpll;
1479 printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1480 apll, mpll, epll, vpll);
1482 armclk = clk_get_rate(&clk_armclk.clk);
1483 sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
1485 aclk_200 = clk_get_rate(&clk_aclk_200.clk);
1486 aclk_100 = clk_get_rate(&clk_aclk_100.clk);
1487 aclk_160 = clk_get_rate(&clk_aclk_160.clk);
1488 aclk_133 = clk_get_rate(&clk_aclk_133.clk);
1490 printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
1491 "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
1492 armclk, sclk_dmc, aclk_200,
1493 aclk_100, aclk_160, aclk_133);
1495 clk_f.rate = armclk;
1496 clk_h.rate = sclk_dmc;
1497 clk_p.rate = aclk_100;
1499 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1500 s3c_set_clksrc(&clksrcs[ptr], true);
1503 static struct clk *clks[] __initdata = {
1510 #ifdef CONFIG_PM_SLEEP
1511 static int exynos4_clock_suspend(void)
1513 s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1517 static void exynos4_clock_resume(void)
1519 s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
1523 #define exynos4_clock_suspend NULL
1524 #define exynos4_clock_resume NULL
1527 static struct syscore_ops exynos4_clock_syscore_ops = {
1528 .suspend = exynos4_clock_suspend,
1529 .resume = exynos4_clock_resume,
1532 void __init exynos4_register_clocks(void)
1536 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1538 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1539 s3c_register_clksrc(sysclks[ptr], 1);
1541 for (ptr = 0; ptr < ARRAY_SIZE(sclk_tv); ptr++)
1542 s3c_register_clksrc(sclk_tv[ptr], 1);
1544 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1545 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1547 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1548 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1550 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1551 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1552 s3c_disable_clocks(clk_cdev[ptr], 1);
1554 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1555 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1556 clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
1558 register_syscore_ops(&exynos4_clock_syscore_ops);
1559 s3c24xx_register_clock(&dummy_apb_pclk);