2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/clk-provider.h>
13 #include <linux/clk/davinci.h>
14 #include <linux/clkdev.h>
15 #include <linux/dmaengine.h>
16 #include <linux/init.h>
18 #include <linux/irqchip/irq-davinci-aintc.h>
19 #include <linux/platform_data/edma.h>
20 #include <linux/platform_data/gpio-davinci.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial_8250.h>
24 #include <asm/mach/map.h>
26 #include <mach/common.h>
27 #include <mach/cputype.h>
29 #include <mach/serial.h>
31 #include <clocksource/timer-davinci.h>
39 * Device specific clocks
41 #define DM644X_REF_FREQ 27000000
43 #define DM644X_EMAC_BASE 0x01c80000
44 #define DM644X_EMAC_MDIO_BASE (DM644X_EMAC_BASE + 0x4000)
45 #define DM644X_EMAC_CNTRL_OFFSET 0x0000
46 #define DM644X_EMAC_CNTRL_MOD_OFFSET 0x1000
47 #define DM644X_EMAC_CNTRL_RAM_OFFSET 0x2000
48 #define DM644X_EMAC_CNTRL_RAM_SIZE 0x2000
50 static struct emac_platform_data dm644x_emac_pdata = {
51 .ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
52 .ctrl_mod_reg_offset = DM644X_EMAC_CNTRL_MOD_OFFSET,
53 .ctrl_ram_offset = DM644X_EMAC_CNTRL_RAM_OFFSET,
54 .ctrl_ram_size = DM644X_EMAC_CNTRL_RAM_SIZE,
55 .version = EMAC_VERSION_1,
58 static struct resource dm644x_emac_resources[] = {
60 .start = DM644X_EMAC_BASE,
61 .end = DM644X_EMAC_BASE + SZ_16K - 1,
62 .flags = IORESOURCE_MEM,
65 .start = DAVINCI_INTC_IRQ(IRQ_EMACINT),
66 .end = DAVINCI_INTC_IRQ(IRQ_EMACINT),
67 .flags = IORESOURCE_IRQ,
71 static struct platform_device dm644x_emac_device = {
72 .name = "davinci_emac",
75 .platform_data = &dm644x_emac_pdata,
77 .num_resources = ARRAY_SIZE(dm644x_emac_resources),
78 .resource = dm644x_emac_resources,
81 static struct resource dm644x_mdio_resources[] = {
83 .start = DM644X_EMAC_MDIO_BASE,
84 .end = DM644X_EMAC_MDIO_BASE + SZ_4K - 1,
85 .flags = IORESOURCE_MEM,
89 static struct platform_device dm644x_mdio_device = {
90 .name = "davinci_mdio",
92 .num_resources = ARRAY_SIZE(dm644x_mdio_resources),
93 .resource = dm644x_mdio_resources,
97 * Device specific mux setup
99 * soc description mux mode mode mux dbg
100 * reg offset mask mode
102 static const struct mux_config dm644x_pins[] = {
103 #ifdef CONFIG_DAVINCI_MUX
104 MUX_CFG(DM644X, HDIREN, 0, 16, 1, 1, true)
105 MUX_CFG(DM644X, ATAEN, 0, 17, 1, 1, true)
106 MUX_CFG(DM644X, ATAEN_DISABLE, 0, 17, 1, 0, true)
108 MUX_CFG(DM644X, HPIEN_DISABLE, 0, 29, 1, 0, true)
110 MUX_CFG(DM644X, AEAW, 0, 0, 31, 31, true)
111 MUX_CFG(DM644X, AEAW0, 0, 0, 1, 0, true)
112 MUX_CFG(DM644X, AEAW1, 0, 1, 1, 0, true)
113 MUX_CFG(DM644X, AEAW2, 0, 2, 1, 0, true)
114 MUX_CFG(DM644X, AEAW3, 0, 3, 1, 0, true)
115 MUX_CFG(DM644X, AEAW4, 0, 4, 1, 0, true)
117 MUX_CFG(DM644X, MSTK, 1, 9, 1, 0, false)
119 MUX_CFG(DM644X, I2C, 1, 7, 1, 1, false)
121 MUX_CFG(DM644X, MCBSP, 1, 10, 1, 1, false)
123 MUX_CFG(DM644X, UART1, 1, 1, 1, 1, true)
124 MUX_CFG(DM644X, UART2, 1, 2, 1, 1, true)
126 MUX_CFG(DM644X, PWM0, 1, 4, 1, 1, false)
128 MUX_CFG(DM644X, PWM1, 1, 5, 1, 1, false)
130 MUX_CFG(DM644X, PWM2, 1, 6, 1, 1, false)
132 MUX_CFG(DM644X, VLYNQEN, 0, 15, 1, 1, false)
133 MUX_CFG(DM644X, VLSCREN, 0, 14, 1, 1, false)
134 MUX_CFG(DM644X, VLYNQWD, 0, 12, 3, 3, false)
136 MUX_CFG(DM644X, EMACEN, 0, 31, 1, 1, true)
138 MUX_CFG(DM644X, GPIO3V, 0, 31, 1, 0, true)
140 MUX_CFG(DM644X, GPIO0, 0, 24, 1, 0, true)
141 MUX_CFG(DM644X, GPIO3, 0, 25, 1, 0, false)
142 MUX_CFG(DM644X, GPIO43_44, 1, 7, 1, 0, false)
143 MUX_CFG(DM644X, GPIO46_47, 0, 22, 1, 0, true)
145 MUX_CFG(DM644X, RGB666, 0, 22, 1, 1, true)
147 MUX_CFG(DM644X, LOEEN, 0, 24, 1, 1, true)
148 MUX_CFG(DM644X, LFLDEN, 0, 25, 1, 1, false)
152 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
153 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
170 [IRQ_CCINT0] = 5, /* dma */
171 [IRQ_CCERRINT] = 5, /* dma */
172 [IRQ_TCERRINT0] = 5, /* dma */
173 [IRQ_TCERRINT] = 5, /* dma */
186 [IRQ_TINT0_TINT12] = 2, /* clockevent */
187 [IRQ_TINT0_TINT34] = 2, /* clocksource */
188 [IRQ_TINT1_TINT12] = 7, /* DSP timer */
189 [IRQ_TINT1_TINT34] = 7, /* system tick */
220 /*----------------------------------------------------------------------*/
222 static s8 queue_priority_mapping[][2] = {
223 /* {event queue no, Priority} */
229 static const struct dma_slave_map dm644x_edma_map[] = {
230 { "davinci-mcbsp", "tx", EDMA_FILTER_PARAM(0, 2) },
231 { "davinci-mcbsp", "rx", EDMA_FILTER_PARAM(0, 3) },
232 { "spi_davinci", "tx", EDMA_FILTER_PARAM(0, 16) },
233 { "spi_davinci", "rx", EDMA_FILTER_PARAM(0, 17) },
234 { "dm6441-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
235 { "dm6441-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
238 static struct edma_soc_info dm644x_edma_pdata = {
239 .queue_priority_mapping = queue_priority_mapping,
240 .default_queue = EVENTQ_1,
241 .slave_map = dm644x_edma_map,
242 .slavecnt = ARRAY_SIZE(dm644x_edma_map),
245 static struct resource edma_resources[] = {
249 .end = 0x01c00000 + SZ_64K - 1,
250 .flags = IORESOURCE_MEM,
255 .end = 0x01c10000 + SZ_1K - 1,
256 .flags = IORESOURCE_MEM,
261 .end = 0x01c10400 + SZ_1K - 1,
262 .flags = IORESOURCE_MEM,
265 .name = "edma3_ccint",
266 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
267 .flags = IORESOURCE_IRQ,
270 .name = "edma3_ccerrint",
271 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
272 .flags = IORESOURCE_IRQ,
274 /* not using TC*_ERR */
277 static const struct platform_device_info dm644x_edma_device __initconst = {
280 .dma_mask = DMA_BIT_MASK(32),
281 .res = edma_resources,
282 .num_res = ARRAY_SIZE(edma_resources),
283 .data = &dm644x_edma_pdata,
284 .size_data = sizeof(dm644x_edma_pdata),
287 /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
288 static struct resource dm644x_asp_resources[] = {
291 .start = DAVINCI_ASP0_BASE,
292 .end = DAVINCI_ASP0_BASE + SZ_8K - 1,
293 .flags = IORESOURCE_MEM,
296 .start = DAVINCI_DMA_ASP0_TX,
297 .end = DAVINCI_DMA_ASP0_TX,
298 .flags = IORESOURCE_DMA,
301 .start = DAVINCI_DMA_ASP0_RX,
302 .end = DAVINCI_DMA_ASP0_RX,
303 .flags = IORESOURCE_DMA,
307 static struct platform_device dm644x_asp_device = {
308 .name = "davinci-mcbsp",
310 .num_resources = ARRAY_SIZE(dm644x_asp_resources),
311 .resource = dm644x_asp_resources,
314 #define DM644X_VPSS_BASE 0x01c73400
316 static struct resource dm644x_vpss_resources[] = {
318 /* VPSS Base address */
320 .start = DM644X_VPSS_BASE,
321 .end = DM644X_VPSS_BASE + 0xff,
322 .flags = IORESOURCE_MEM,
326 static struct platform_device dm644x_vpss_device = {
329 .dev.platform_data = "dm644x_vpss",
330 .num_resources = ARRAY_SIZE(dm644x_vpss_resources),
331 .resource = dm644x_vpss_resources,
334 static struct resource dm644x_vpfe_resources[] = {
336 .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
337 .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
338 .flags = IORESOURCE_IRQ,
341 .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
342 .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
343 .flags = IORESOURCE_IRQ,
347 static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
348 static struct resource dm644x_ccdc_resource[] = {
349 /* CCDC Base address */
352 .end = 0x01c70400 + 0xff,
353 .flags = IORESOURCE_MEM,
357 static struct platform_device dm644x_ccdc_dev = {
358 .name = "dm644x_ccdc",
360 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
361 .resource = dm644x_ccdc_resource,
363 .dma_mask = &dm644x_video_dma_mask,
364 .coherent_dma_mask = DMA_BIT_MASK(32),
368 static struct platform_device dm644x_vpfe_dev = {
369 .name = CAPTURE_DRV_NAME,
371 .num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
372 .resource = dm644x_vpfe_resources,
374 .dma_mask = &dm644x_video_dma_mask,
375 .coherent_dma_mask = DMA_BIT_MASK(32),
379 #define DM644X_OSD_BASE 0x01c72600
381 static struct resource dm644x_osd_resources[] = {
383 .start = DM644X_OSD_BASE,
384 .end = DM644X_OSD_BASE + 0x1ff,
385 .flags = IORESOURCE_MEM,
389 static struct platform_device dm644x_osd_dev = {
390 .name = DM644X_VPBE_OSD_SUBDEV_NAME,
392 .num_resources = ARRAY_SIZE(dm644x_osd_resources),
393 .resource = dm644x_osd_resources,
395 .dma_mask = &dm644x_video_dma_mask,
396 .coherent_dma_mask = DMA_BIT_MASK(32),
400 #define DM644X_VENC_BASE 0x01c72400
402 static struct resource dm644x_venc_resources[] = {
404 .start = DM644X_VENC_BASE,
405 .end = DM644X_VENC_BASE + 0x17f,
406 .flags = IORESOURCE_MEM,
410 #define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
411 #define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
412 #define DM644X_VPSS_VENCLKEN BIT(3)
413 #define DM644X_VPSS_DACCLKEN BIT(4)
415 static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
419 u32 v = DM644X_VPSS_VENCLKEN;
423 v |= DM644X_VPSS_DACCLKEN;
424 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
426 case VPBE_ENC_DV_TIMINGS:
427 if (pclock <= 27000000) {
428 v |= DM644X_VPSS_DACCLKEN;
429 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
432 * For HD, use external clock source since
433 * HD requires higher clock rate
435 v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
436 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
446 static struct resource dm644x_v4l2_disp_resources[] = {
448 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
449 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
450 .flags = IORESOURCE_IRQ,
454 static struct platform_device dm644x_vpbe_display = {
457 .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
458 .resource = dm644x_v4l2_disp_resources,
460 .dma_mask = &dm644x_video_dma_mask,
461 .coherent_dma_mask = DMA_BIT_MASK(32),
465 static struct venc_platform_data dm644x_venc_pdata = {
466 .setup_clock = dm644x_venc_setup_clock,
469 static struct platform_device dm644x_venc_dev = {
470 .name = DM644X_VPBE_VENC_SUBDEV_NAME,
472 .num_resources = ARRAY_SIZE(dm644x_venc_resources),
473 .resource = dm644x_venc_resources,
475 .dma_mask = &dm644x_video_dma_mask,
476 .coherent_dma_mask = DMA_BIT_MASK(32),
477 .platform_data = &dm644x_venc_pdata,
481 static struct platform_device dm644x_vpbe_dev = {
482 .name = "vpbe_controller",
485 .dma_mask = &dm644x_video_dma_mask,
486 .coherent_dma_mask = DMA_BIT_MASK(32),
490 static struct resource dm644_gpio_resources[] = {
492 .start = DAVINCI_GPIO_BASE,
493 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
494 .flags = IORESOURCE_MEM,
497 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
498 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK0),
499 .flags = IORESOURCE_IRQ,
502 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
503 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK1),
504 .flags = IORESOURCE_IRQ,
507 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
508 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK2),
509 .flags = IORESOURCE_IRQ,
512 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
513 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK3),
514 .flags = IORESOURCE_IRQ,
517 .start = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
518 .end = DAVINCI_INTC_IRQ(IRQ_GPIOBNK4),
519 .flags = IORESOURCE_IRQ,
523 static struct davinci_gpio_platform_data dm644_gpio_platform_data = {
524 .no_auto_base = true,
529 int __init dm644x_gpio_register(void)
531 return davinci_gpio_register(dm644_gpio_resources,
532 ARRAY_SIZE(dm644_gpio_resources),
533 &dm644_gpio_platform_data);
535 /*----------------------------------------------------------------------*/
537 static struct map_desc dm644x_io_desc[] = {
540 .pfn = __phys_to_pfn(IO_PHYS),
546 /* Contents of JTAG ID register used to identify exact cpu type */
547 static struct davinci_id dm644x_ids[] = {
551 .manufacturer = 0x017,
552 .cpu_id = DAVINCI_CPU_ID_DM6446,
558 .manufacturer = 0x017,
559 .cpu_id = DAVINCI_CPU_ID_DM6446,
565 * Bottom half of timer0 is used for clockevent, top half is used for
568 static const struct davinci_timer_cfg dm644x_timer_cfg = {
569 .reg = DEFINE_RES_IO(DAVINCI_TIMER0_BASE, SZ_4K),
571 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT12)),
572 DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_TINT0_TINT34)),
576 static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
578 .mapbase = DAVINCI_UART0_BASE,
579 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
580 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
589 static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
591 .mapbase = DAVINCI_UART1_BASE,
592 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
593 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
602 static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
604 .mapbase = DAVINCI_UART2_BASE,
605 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT2),
606 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
616 struct platform_device dm644x_serial_device[] = {
618 .name = "serial8250",
619 .id = PLAT8250_DEV_PLATFORM,
621 .platform_data = dm644x_serial0_platform_data,
625 .name = "serial8250",
626 .id = PLAT8250_DEV_PLATFORM1,
628 .platform_data = dm644x_serial1_platform_data,
632 .name = "serial8250",
633 .id = PLAT8250_DEV_PLATFORM2,
635 .platform_data = dm644x_serial2_platform_data,
642 static const struct davinci_soc_info davinci_soc_info_dm644x = {
643 .io_desc = dm644x_io_desc,
644 .io_desc_num = ARRAY_SIZE(dm644x_io_desc),
645 .jtag_id_reg = 0x01c40028,
647 .ids_num = ARRAY_SIZE(dm644x_ids),
648 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
649 .pinmux_pins = dm644x_pins,
650 .pinmux_pins_num = ARRAY_SIZE(dm644x_pins),
651 .emac_pdata = &dm644x_emac_pdata,
652 .sram_dma = 0x00008000,
656 void __init dm644x_init_asp(void)
658 davinci_cfg_reg(DM644X_MCBSP);
659 platform_device_register(&dm644x_asp_device);
662 void __init dm644x_init(void)
664 davinci_common_init(&davinci_soc_info_dm644x);
665 davinci_map_sysmod();
668 void __init dm644x_init_time(void)
670 void __iomem *pll1, *psc;
674 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM644X_REF_FREQ);
676 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
677 dm644x_pll1_init(NULL, pll1, NULL);
679 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
680 dm644x_psc_init(NULL, psc);
682 clk = clk_get(NULL, "timer0");
683 if (WARN_ON(IS_ERR(clk))) {
684 pr_err("Unable to get the timer clock\n");
688 rv = davinci_timer_register(clk, &dm644x_timer_cfg);
689 WARN(rv, "Unable to register the timer: %d\n", rv);
692 static struct resource dm644x_pll2_resources[] = {
694 .start = DAVINCI_PLL2_BASE,
695 .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
696 .flags = IORESOURCE_MEM,
700 static struct platform_device dm644x_pll2_device = {
701 .name = "dm644x-pll2",
703 .resource = dm644x_pll2_resources,
704 .num_resources = ARRAY_SIZE(dm644x_pll2_resources),
707 void __init dm644x_register_clocks(void)
709 /* PLL1 and PSC are registered in dm644x_init_time() */
710 platform_device_register(&dm644x_pll2_device);
713 int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
714 struct vpbe_config *vpbe_cfg)
716 if (vpfe_cfg || vpbe_cfg)
717 platform_device_register(&dm644x_vpss_device);
720 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
721 platform_device_register(&dm644x_ccdc_dev);
722 platform_device_register(&dm644x_vpfe_dev);
726 dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
727 platform_device_register(&dm644x_osd_dev);
728 platform_device_register(&dm644x_venc_dev);
729 platform_device_register(&dm644x_vpbe_dev);
730 platform_device_register(&dm644x_vpbe_display);
736 static const struct davinci_aintc_config dm644x_aintc_config = {
738 .start = DAVINCI_ARM_INTC_BASE,
739 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
740 .flags = IORESOURCE_MEM,
743 .prios = dm644x_default_priorities,
746 void __init dm644x_init_irq(void)
748 davinci_aintc_init(&dm644x_aintc_config);
751 void __init dm644x_init_devices(void)
753 struct platform_device *edma_pdev;
756 edma_pdev = platform_device_register_full(&dm644x_edma_device);
757 if (IS_ERR(edma_pdev))
758 pr_warn("%s: Failed to register eDMA\n", __func__);
760 platform_device_register(&dm644x_mdio_device);
761 platform_device_register(&dm644x_emac_device);
763 ret = davinci_init_wdt();
765 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);