2 * TI DaVinci clock definitions
4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #ifndef __ARCH_ARM_DAVINCI_CLOCK_H
13 #define __ARCH_ARM_DAVINCI_CLOCK_H
15 /* PLL/Reset register offsets */
17 #define PLLCTL_PLLEN BIT(0)
18 #define PLLCTL_PLLPWRDN BIT(1)
19 #define PLLCTL_PLLRST BIT(3)
20 #define PLLCTL_PLLDIS BIT(4)
21 #define PLLCTL_PLLENSRC BIT(5)
22 #define PLLCTL_CLKMODE BIT(8)
25 #define PLLM_PLLM_MASK 0xff
35 #define PLLALNCTL 0x140
36 #define PLLDCHANGE 0x144
38 #define PLLCKSTAT 0x14c
39 #define PLLSYSTAT 0x150
46 #define PLLDIV_EN BIT(15)
47 #define PLLDIV_RATIO_MASK 0x1f
50 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
51 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
52 * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
53 * is ~25MHz. Units are micro seconds.
55 #define PLL_BYPASS_TIME 1
56 /* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
57 #define PLL_RESET_TIME 1
59 * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
60 * Units are micro seconds.
62 #define PLL_LOCK_TIME 20