arch/arm/mach-davinci/board-mityomapl138.c

   1 /*
   2  * Critical Link MityOMAP-L138 SoM
   3  *
   4  * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of
   8  * any kind, whether express or implied.
   9  */
  10
  11 #define pr_fmt(fmt) "MityOMAPL138: " fmt
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/console.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/property.h>
  18 #include <linux/mtd/partitions.h>
  19 #include <linux/notifier.h>
  20 #include <linux/nvmem-consumer.h>
  21 #include <linux/nvmem-provider.h>
  22 #include <linux/regulator/machine.h>
  23 #include <linux/i2c.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/spi/flash.h>
  27
  28 #include <asm/io.h>
  29 #include <asm/mach-types.h>
  30 #include <asm/mach/arch.h>
  31 #include <mach/common.h>
  32 #include <mach/da8xx.h>
  33 #include <linux/platform_data/mtd-davinci.h>
  34 #include <linux/platform_data/mtd-davinci-aemif.h>
  35 #include <linux/platform_data/ti-aemif.h>
  36 #include <mach/mux.h>
  37 #include <linux/platform_data/spi-davinci.h>
  38
  39 #define MITYOMAPL138_PHY_ID             ""
  40
  41 #define FACTORY_CONFIG_MAGIC    0x012C0138
  42 #define FACTORY_CONFIG_VERSION  0x00010001
  43
  44 /* Data Held in On-Board I2C device */
  45 struct factory_config {
  46         u32     magic;
  47         u32     version;
  48         u8      mac[6];
  49         u32     fpga_type;
  50         u32     spare;
  51         u32     serialnumber;
  52         char    partnum[32];
  53 };
  54
  55 static struct factory_config factory_config;
  56
  57 #ifdef CONFIG_CPU_FREQ
  58 struct part_no_info {
  59         const char      *part_no;       /* part number string of interest */
  60         int             max_freq;       /* khz */
  61 };
  62
  63 static struct part_no_info mityomapl138_pn_info[] = {
  64         {
  65                 .part_no        = "L138-C",
  66                 .max_freq       = 300000,
  67         },
  68         {
  69                 .part_no        = "L138-D",
  70                 .max_freq       = 375000,
  71         },
  72         {
  73                 .part_no        = "L138-F",
  74                 .max_freq       = 456000,
  75         },
  76         {
  77                 .part_no        = "1808-C",
  78                 .max_freq       = 300000,
  79         },
  80         {
  81                 .part_no        = "1808-D",
  82                 .max_freq       = 375000,
  83         },
  84         {
  85                 .part_no        = "1808-F",
  86                 .max_freq       = 456000,
  87         },
  88         {
  89                 .part_no        = "1810-D",
  90                 .max_freq       = 375000,
  91         },
  92 };
  93
  94 static void mityomapl138_cpufreq_init(const char *partnum)
  95 {
  96         int i, ret;
  97
  98         for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) {
  99                 /*
 100                  * the part number has additional characters beyond what is
 101                  * stored in the table.  This information is not needed for
 102                  * determining the speed grade, and would require several
 103                  * more table entries.  Only check the first N characters
 104                  * for a match.
 105                  */
 106                 if (!strncmp(partnum, mityomapl138_pn_info[i].part_no,
 107                              strlen(mityomapl138_pn_info[i].part_no))) {
 108                         da850_max_speed = mityomapl138_pn_info[i].max_freq;
 109                         break;
 110                 }
 111         }
 112
 113         ret = da850_register_cpufreq("pll0_sysclk3");
 114         if (ret)
 115                 pr_warn("cpufreq registration failed: %d\n", ret);
 116 }
 117 #else
 118 static void mityomapl138_cpufreq_init(const char *partnum) { }
 119 #endif
 120
 121 static int read_factory_config(struct notifier_block *nb,
 122                                unsigned long event, void *data)
 123 {
 124         int ret;
 125         const char *partnum = NULL;
 126         struct nvmem_device *nvmem = data;
 127
 128         if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0)
 129                 return NOTIFY_DONE;
 130
 131         if (!IS_BUILTIN(CONFIG_NVMEM)) {
 132                 pr_warn("Factory Config not available without CONFIG_NVMEM\n");
 133                 goto bad_config;
 134         }
 135
 136         ret = nvmem_device_read(nvmem, 0, sizeof(factory_config),
 137                                 &factory_config);
 138         if (ret != sizeof(struct factory_config)) {
 139                 pr_warn("Read Factory Config Failed: %d\n", ret);
 140                 goto bad_config;
 141         }
 142
 143         if (factory_config.magic != FACTORY_CONFIG_MAGIC) {
 144                 pr_warn("Factory Config Magic Wrong (%X)\n",
 145                         factory_config.magic);
 146                 goto bad_config;
 147         }
 148
 149         if (factory_config.version != FACTORY_CONFIG_VERSION) {
 150                 pr_warn("Factory Config Version Wrong (%X)\n",
 151                         factory_config.version);
 152                 goto bad_config;
 153         }
 154
 155         partnum = factory_config.partnum;
 156         pr_info("Part Number = %s\n", partnum);
 157
 158 bad_config:
 159         /* default maximum speed is valid for all platforms */
 160         mityomapl138_cpufreq_init(partnum);
 161
 162         return NOTIFY_STOP;
 163 }
 164
 165 static struct notifier_block mityomapl138_nvmem_notifier = {
 166         .notifier_call = read_factory_config,
 167 };
 168
 169 /*
 170  * We don't define a cell for factory config as it will be accessed from the
 171  * board file using the nvmem notifier chain.
 172  */
 173 static struct nvmem_cell_info mityomapl138_nvmem_cells[] = {
 174         {
 175                 .name           = "macaddr",
 176                 .offset         = 0x64,
 177                 .bytes          = ETH_ALEN,
 178         }
 179 };
 180
 181 static struct nvmem_cell_table mityomapl138_nvmem_cell_table = {
 182         .nvmem_name     = "1-00500",
 183         .cells          = mityomapl138_nvmem_cells,
 184         .ncells         = ARRAY_SIZE(mityomapl138_nvmem_cells),
 185 };
 186
 187 static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = {
 188         .nvmem_name     = "1-00500",
 189         .cell_name      = "macaddr",
 190         .dev_id         = "davinci_emac.1",
 191         .con_id         = "mac-address",
 192 };
 193
 194 static const struct property_entry mityomapl138_fd_chip_properties[] = {
 195         PROPERTY_ENTRY_U32("pagesize", 8),
 196         PROPERTY_ENTRY_BOOL("read-only"),
 197         { }
 198 };
 199
 200 static const struct software_node mityomapl138_fd_chip_node = {
 201         .properties = mityomapl138_fd_chip_properties,
 202 };
 203
 204 static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = {
 205         .bus_freq       = 100,  /* kHz */
 206         .bus_delay      = 0,    /* usec */
 207 };
 208
 209 /* TPS65023 voltage regulator support */
 210 /* 1.2V Core */
 211 static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = {
 212         {
 213                 .supply = "cvdd",
 214         },
 215 };
 216
 217 /* 1.8V */
 218 static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = {
 219         {
 220                 .supply = "usb0_vdda18",
 221         },
 222         {
 223                 .supply = "usb1_vdda18",
 224         },
 225         {
 226                 .supply = "ddr_dvdd18",
 227         },
 228         {
 229                 .supply = "sata_vddr",
 230         },
 231 };
 232
 233 /* 1.2V */
 234 static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = {
 235         {
 236                 .supply = "sata_vdd",
 237         },
 238         {
 239                 .supply = "usb_cvdd",
 240         },
 241         {
 242                 .supply = "pll0_vdda",
 243         },
 244         {
 245                 .supply = "pll1_vdda",
 246         },
 247 };
 248
 249 /* 1.8V Aux LDO, not used */
 250 static struct regulator_consumer_supply tps65023_ldo1_consumers[] = {
 251         {
 252                 .supply = "1.8v_aux",
 253         },
 254 };
 255
 256 /* FPGA VCC Aux (2.5 or 3.3) LDO */
 257 static struct regulator_consumer_supply tps65023_ldo2_consumers[] = {
 258         {
 259                 .supply = "vccaux",
 260         },
 261 };
 262
 263 static struct regulator_init_data tps65023_regulator_data[] = {
 264         /* dcdc1 */
 265         {
 266                 .constraints = {
 267                         .min_uV = 1150000,
 268                         .max_uV = 1350000,
 269                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 270                                           REGULATOR_CHANGE_STATUS,
 271                         .boot_on = 1,
 272                 },
 273                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers),
 274                 .consumer_supplies = tps65023_dcdc1_consumers,
 275         },
 276         /* dcdc2 */
 277         {
 278                 .constraints = {
 279                         .min_uV = 1800000,
 280                         .max_uV = 1800000,
 281                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 282                         .boot_on = 1,
 283                 },
 284                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers),
 285                 .consumer_supplies = tps65023_dcdc2_consumers,
 286         },
 287         /* dcdc3 */
 288         {
 289                 .constraints = {
 290                         .min_uV = 1200000,
 291                         .max_uV = 1200000,
 292                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 293                         .boot_on = 1,
 294                 },
 295                 .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers),
 296                 .consumer_supplies = tps65023_dcdc3_consumers,
 297         },
 298         /* ldo1 */
 299         {
 300                 .constraints = {
 301                         .min_uV = 1800000,
 302                         .max_uV = 1800000,
 303                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
 304                         .boot_on = 1,
 305                 },
 306                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers),
 307                 .consumer_supplies = tps65023_ldo1_consumers,
 308         },
 309         /* ldo2 */
 310         {
 311                 .constraints = {
 312                         .min_uV = 2500000,
 313                         .max_uV = 3300000,
 314                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 315                                           REGULATOR_CHANGE_STATUS,
 316                         .boot_on = 1,
 317                 },
 318                 .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers),
 319                 .consumer_supplies = tps65023_ldo2_consumers,
 320         },
 321 };
 322
 323 static struct i2c_board_info __initdata mityomap_tps65023_info[] = {
 324         {
 325                 I2C_BOARD_INFO("tps65023", 0x48),
 326                 .platform_data = &tps65023_regulator_data[0],
 327         },
 328         {
 329                 I2C_BOARD_INFO("24c02", 0x50),
 330                 .swnode = &mityomapl138_fd_chip_node,
 331         },
 332 };
 333
 334 static int __init pmic_tps65023_init(void)
 335 {
 336         return i2c_register_board_info(1, mityomap_tps65023_info,
 337                                         ARRAY_SIZE(mityomap_tps65023_info));
 338 }
 339
 340 /*
 341  * SPI Devices:
 342  *      SPI1_CS0: 8M Flash ST-M25P64-VME6G
 343  */
 344 static struct mtd_partition spi_flash_partitions[] = {
 345         [0] = {
 346                 .name           = "ubl",
 347                 .offset         = 0,
 348                 .size           = SZ_64K,
 349                 .mask_flags     = MTD_WRITEABLE,
 350         },
 351         [1] = {
 352                 .name           = "u-boot",
 353                 .offset         = MTDPART_OFS_APPEND,
 354                 .size           = SZ_512K,
 355                 .mask_flags     = MTD_WRITEABLE,
 356         },
 357         [2] = {
 358                 .name           = "u-boot-env",
 359                 .offset         = MTDPART_OFS_APPEND,
 360                 .size           = SZ_64K,
 361                 .mask_flags     = MTD_WRITEABLE,
 362         },
 363         [3] = {
 364                 .name           = "periph-config",
 365                 .offset         = MTDPART_OFS_APPEND,
 366                 .size           = SZ_64K,
 367                 .mask_flags     = MTD_WRITEABLE,
 368         },
 369         [4] = {
 370                 .name           = "reserved",
 371                 .offset         = MTDPART_OFS_APPEND,
 372                 .size           = SZ_256K + SZ_64K,
 373         },
 374         [5] = {
 375                 .name           = "kernel",
 376                 .offset         = MTDPART_OFS_APPEND,
 377                 .size           = SZ_2M + SZ_1M,
 378         },
 379         [6] = {
 380                 .name           = "fpga",
 381                 .offset         = MTDPART_OFS_APPEND,
 382                 .size           = SZ_2M,
 383         },
 384         [7] = {
 385                 .name           = "spare",
 386                 .offset         = MTDPART_OFS_APPEND,
 387                 .size           = MTDPART_SIZ_FULL,
 388         },
 389 };
 390
 391 static struct flash_platform_data mityomapl138_spi_flash_data = {
 392         .name           = "m25p80",
 393         .parts          = spi_flash_partitions,
 394         .nr_parts       = ARRAY_SIZE(spi_flash_partitions),
 395         .type           = "m24p64",
 396 };
 397
 398 static struct davinci_spi_config spi_eprom_config = {
 399         .io_type        = SPI_IO_TYPE_DMA,
 400         .c2tdelay       = 8,
 401         .t2cdelay       = 8,
 402 };
 403
 404 static struct spi_board_info mityomapl138_spi_flash_info[] = {
 405         {
 406                 .modalias               = "m25p80",
 407                 .platform_data          = &mityomapl138_spi_flash_data,
 408                 .controller_data        = &spi_eprom_config,
 409                 .mode                   = SPI_MODE_0,
 410                 .max_speed_hz           = 30000000,
 411                 .bus_num                = 1,
 412                 .chip_select            = 0,
 413         },
 414 };
 415
 416 /*
 417  * MityDSP-L138 includes a 256 MByte large-page NAND flash
 418  * (128K blocks).
 419  */
 420 static struct mtd_partition mityomapl138_nandflash_partition[] = {
 421         {
 422                 .name           = "rootfs",
 423                 .offset         = 0,
 424                 .size           = SZ_128M,
 425                 .mask_flags     = 0, /* MTD_WRITEABLE, */
 426         },
 427         {
 428                 .name           = "homefs",
 429                 .offset         = MTDPART_OFS_APPEND,
 430                 .size           = MTDPART_SIZ_FULL,
 431                 .mask_flags     = 0,
 432         },
 433 };
 434
 435 static struct davinci_nand_pdata mityomapl138_nandflash_data = {
 436         .core_chipsel   = 1,
 437         .parts          = mityomapl138_nandflash_partition,
 438         .nr_parts       = ARRAY_SIZE(mityomapl138_nandflash_partition),
 439         .engine_type    = NAND_ECC_ENGINE_TYPE_ON_HOST,
 440         .bbt_options    = NAND_BBT_USE_FLASH,
 441         .options        = NAND_BUSWIDTH_16,
 442         .ecc_bits       = 1, /* 4 bit mode is not supported with 16 bit NAND */
 443 };
 444
 445 static struct resource mityomapl138_nandflash_resource[] = {
 446         {
 447                 .start  = DA8XX_AEMIF_CS3_BASE,
 448                 .end    = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1,
 449                 .flags  = IORESOURCE_MEM,
 450         },
 451         {
 452                 .start  = DA8XX_AEMIF_CTL_BASE,
 453                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
 454                 .flags  = IORESOURCE_MEM,
 455         },
 456 };
 457
 458 static struct platform_device mityomapl138_aemif_devices[] = {
 459         {
 460                 .name           = "davinci_nand",
 461                 .id             = 1,
 462                 .dev            = {
 463                         .platform_data  = &mityomapl138_nandflash_data,
 464                 },
 465                 .num_resources  = ARRAY_SIZE(mityomapl138_nandflash_resource),
 466                 .resource       = mityomapl138_nandflash_resource,
 467         },
 468 };
 469
 470 static struct resource mityomapl138_aemif_resources[] = {
 471         {
 472                 .start  = DA8XX_AEMIF_CTL_BASE,
 473                 .end    = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1,
 474                 .flags  = IORESOURCE_MEM,
 475         },
 476 };
 477
 478 static struct aemif_abus_data mityomapl138_aemif_abus_data[] = {
 479         {
 480                 .cs     = 1,
 481         },
 482 };
 483
 484 static struct aemif_platform_data mityomapl138_aemif_pdata = {
 485         .abus_data              = mityomapl138_aemif_abus_data,
 486         .num_abus_data          = ARRAY_SIZE(mityomapl138_aemif_abus_data),
 487         .sub_devices            = mityomapl138_aemif_devices,
 488         .num_sub_devices        = ARRAY_SIZE(mityomapl138_aemif_devices),
 489 };
 490
 491 static struct platform_device mityomapl138_aemif_device = {
 492         .name           = "ti-aemif",
 493         .id             = -1,
 494         .dev = {
 495                 .platform_data  = &mityomapl138_aemif_pdata,
 496         },
 497         .resource       = mityomapl138_aemif_resources,
 498         .num_resources  = ARRAY_SIZE(mityomapl138_aemif_resources),
 499 };
 500
 501 static void __init mityomapl138_setup_nand(void)
 502 {
 503         if (platform_device_register(&mityomapl138_aemif_device))
 504                 pr_warn("%s: Cannot register AEMIF device\n", __func__);
 505 }
 506
 507 static const short mityomap_mii_pins[] = {
 508         DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
 509         DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
 510         DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
 511         DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
 512         DA850_MDIO_D,
 513         -1
 514 };
 515
 516 static const short mityomap_rmii_pins[] = {
 517         DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN,
 518         DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1,
 519         DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK,
 520         DA850_MDIO_D,
 521         -1
 522 };
 523
 524 static void __init mityomapl138_config_emac(void)
 525 {
 526         void __iomem *cfg_chip3_base;
 527         int ret;
 528         u32 val;
 529         struct davinci_soc_info *soc_info = &davinci_soc_info;
 530
 531         soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */
 532
 533         cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG);
 534         val = __raw_readl(cfg_chip3_base);
 535
 536         if (soc_info->emac_pdata->rmii_en) {
 537                 val |= BIT(8);
 538                 ret = davinci_cfg_reg_list(mityomap_rmii_pins);
 539                 pr_info("RMII PHY configured\n");
 540         } else {
 541                 val &= ~BIT(8);
 542                 ret = davinci_cfg_reg_list(mityomap_mii_pins);
 543                 pr_info("MII PHY configured\n");
 544         }
 545
 546         if (ret) {
 547                 pr_warn("mii/rmii mux setup failed: %d\n", ret);
 548                 return;
 549         }
 550
 551         /* configure the CFGCHIP3 register for RMII or MII */
 552         __raw_writel(val, cfg_chip3_base);
 553
 554         soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID;
 555
 556         ret = da8xx_register_emac();
 557         if (ret)
 558                 pr_warn("emac registration failed: %d\n", ret);
 559 }
 560
 561 static void __init mityomapl138_init(void)
 562 {
 563         int ret;
 564
 565         da850_register_clocks();
 566
 567         /* for now, no special EDMA channels are reserved */
 568         ret = da850_register_edma(NULL);
 569         if (ret)
 570                 pr_warn("edma registration failed: %d\n", ret);
 571
 572         ret = da8xx_register_watchdog();
 573         if (ret)
 574                 pr_warn("watchdog registration failed: %d\n", ret);
 575
 576         davinci_serial_init(da8xx_serial_device);
 577
 578         nvmem_register_notifier(&mityomapl138_nvmem_notifier);
 579         nvmem_add_cell_table(&mityomapl138_nvmem_cell_table);
 580         nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1);
 581
 582         ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
 583         if (ret)
 584                 pr_warn("i2c0 registration failed: %d\n", ret);
 585
 586         ret = pmic_tps65023_init();
 587         if (ret)
 588                 pr_warn("TPS65023 PMIC init failed: %d\n", ret);
 589
 590         mityomapl138_setup_nand();
 591
 592         ret = spi_register_board_info(mityomapl138_spi_flash_info,
 593                                       ARRAY_SIZE(mityomapl138_spi_flash_info));
 594         if (ret)
 595                 pr_warn("spi info registration failed: %d\n", ret);
 596
 597         ret = da8xx_register_spi_bus(1,
 598                                      ARRAY_SIZE(mityomapl138_spi_flash_info));
 599         if (ret)
 600                 pr_warn("spi 1 registration failed: %d\n", ret);
 601
 602         mityomapl138_config_emac();
 603
 604         ret = da8xx_register_rtc();
 605         if (ret)
 606                 pr_warn("rtc setup failed: %d\n", ret);
 607
 608         ret = da8xx_register_cpuidle();
 609         if (ret)
 610                 pr_warn("cpuidle registration failed: %d\n", ret);
 611
 612         davinci_pm_init();
 613 }
 614
 615 #ifdef CONFIG_SERIAL_8250_CONSOLE
 616 static int __init mityomapl138_console_init(void)
 617 {
 618         if (!machine_is_mityomapl138())
 619                 return 0;
 620
 621         return add_preferred_console("ttyS", 1, "115200");
 622 }
 623 console_initcall(mityomapl138_console_init);
 624 #endif
 625
 626 static void __init mityomapl138_map_io(void)
 627 {
 628         da850_init();
 629 }
 630
 631 MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
 632         .atag_offset    = 0x100,
 633         .map_io         = mityomapl138_map_io,
 634         .init_irq       = da850_init_irq,
 635         .init_time      = da850_init_time,
 636         .init_machine   = mityomapl138_init,
 637         .init_late      = davinci_init_late,
 638         .dma_zone_size  = SZ_128M,
 639 MACHINE_END