arch/arm/mach-davinci/board-dm365-evm.c

   1 /*
   2  * TI DaVinci DM365 EVM board support
   3  *
   4  * Copyright (C) 2009 Texas Instruments Incorporated
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/err.h>
  18 #include <linux/i2c.h>
  19 #include <linux/io.h>
  20 #include <linux/clk.h>
  21 #include <linux/property.h>
  22 #include <linux/leds.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/partitions.h>
  25 #include <linux/slab.h>
  26 #include <linux/mtd/rawnand.h>
  27 #include <linux/nvmem-provider.h>
  28 #include <linux/input.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/spi/eeprom.h>
  31 #include <linux/v4l2-dv-timings.h>
  32 #include <linux/platform_data/ti-aemif.h>
  33 #include <linux/regulator/fixed.h>
  34 #include <linux/regulator/machine.h>
  35
  36 #include <asm/mach-types.h>
  37 #include <asm/mach/arch.h>
  38
  39 #include <mach/mux.h>
  40 #include <mach/common.h>
  41 #include <linux/platform_data/i2c-davinci.h>
  42 #include <mach/serial.h>
  43 #include <linux/platform_data/mmc-davinci.h>
  44 #include <linux/platform_data/mtd-davinci.h>
  45 #include <linux/platform_data/keyscan-davinci.h>
  46
  47 #include <media/i2c/ths7303.h>
  48 #include <media/i2c/tvp514x.h>
  49
  50 #include "davinci.h"
  51
  52 static inline int have_imager(void)
  53 {
  54         /* REVISIT when it's supported, trigger via Kconfig */
  55         return 0;
  56 }
  57
  58 static inline int have_tvp7002(void)
  59 {
  60         /* REVISIT when it's supported, trigger via Kconfig */
  61         return 0;
  62 }
  63
  64 #define DM365_EVM_PHY_ID                "davinci_mdio-0:01"
  65 /*
  66  * A MAX-II CPLD is used for various board control functions.
  67  */
  68 #define CPLD_OFFSET(a13a8,a2a1)         (((a13a8) << 10) + ((a2a1) << 3))
  69
  70 #define CPLD_VERSION    CPLD_OFFSET(0,0)        /* r/o */
  71 #define CPLD_TEST       CPLD_OFFSET(0,1)
  72 #define CPLD_LEDS       CPLD_OFFSET(0,2)
  73 #define CPLD_MUX        CPLD_OFFSET(0,3)
  74 #define CPLD_SWITCH     CPLD_OFFSET(1,0)        /* r/o */
  75 #define CPLD_POWER      CPLD_OFFSET(1,1)
  76 #define CPLD_VIDEO      CPLD_OFFSET(1,2)
  77 #define CPLD_CARDSTAT   CPLD_OFFSET(1,3)        /* r/o */
  78
  79 #define CPLD_DILC_OUT   CPLD_OFFSET(2,0)
  80 #define CPLD_DILC_IN    CPLD_OFFSET(2,1)        /* r/o */
  81
  82 #define CPLD_IMG_DIR0   CPLD_OFFSET(2,2)
  83 #define CPLD_IMG_MUX0   CPLD_OFFSET(2,3)
  84 #define CPLD_IMG_MUX1   CPLD_OFFSET(3,0)
  85 #define CPLD_IMG_DIR1   CPLD_OFFSET(3,1)
  86 #define CPLD_IMG_MUX2   CPLD_OFFSET(3,2)
  87 #define CPLD_IMG_MUX3   CPLD_OFFSET(3,3)
  88 #define CPLD_IMG_DIR2   CPLD_OFFSET(4,0)
  89 #define CPLD_IMG_MUX4   CPLD_OFFSET(4,1)
  90 #define CPLD_IMG_MUX5   CPLD_OFFSET(4,2)
  91
  92 #define CPLD_RESETS     CPLD_OFFSET(4,3)
  93
  94 #define CPLD_CCD_DIR1   CPLD_OFFSET(0x3e,0)
  95 #define CPLD_CCD_IO1    CPLD_OFFSET(0x3e,1)
  96 #define CPLD_CCD_DIR2   CPLD_OFFSET(0x3e,2)
  97 #define CPLD_CCD_IO2    CPLD_OFFSET(0x3e,3)
  98 #define CPLD_CCD_DIR3   CPLD_OFFSET(0x3f,0)
  99 #define CPLD_CCD_IO3    CPLD_OFFSET(0x3f,1)
 100
 101 static void __iomem *cpld;
 102
 103
 104 /* NOTE:  this is geared for the standard config, with a socketed
 105  * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors.  If you
 106  * swap chips with a different block size, partitioning will
 107  * need to be changed. This NAND chip MT29F16G08FAA is the default
 108  * NAND shipped with the Spectrum Digital DM365 EVM
 109  */
 110 #define NAND_BLOCK_SIZE         SZ_128K
 111
 112 static struct mtd_partition davinci_nand_partitions[] = {
 113         {
 114                 /* UBL (a few copies) plus U-Boot */
 115                 .name           = "bootloader",
 116                 .offset         = 0,
 117                 .size           = 30 * NAND_BLOCK_SIZE,
 118                 .mask_flags     = MTD_WRITEABLE, /* force read-only */
 119         }, {
 120                 /* U-Boot environment */
 121                 .name           = "params",
 122                 .offset         = MTDPART_OFS_APPEND,
 123                 .size           = 2 * NAND_BLOCK_SIZE,
 124                 .mask_flags     = 0,
 125         }, {
 126                 .name           = "kernel",
 127                 .offset         = MTDPART_OFS_APPEND,
 128                 .size           = SZ_4M,
 129                 .mask_flags     = 0,
 130         }, {
 131                 .name           = "filesystem1",
 132                 .offset         = MTDPART_OFS_APPEND,
 133                 .size           = SZ_512M,
 134                 .mask_flags     = 0,
 135         }, {
 136                 .name           = "filesystem2",
 137                 .offset         = MTDPART_OFS_APPEND,
 138                 .size           = MTDPART_SIZ_FULL,
 139                 .mask_flags     = 0,
 140         }
 141         /* two blocks with bad block table (and mirror) at the end */
 142 };
 143
 144 static struct davinci_nand_pdata davinci_nand_data = {
 145         .core_chipsel           = 0,
 146         .mask_chipsel           = BIT(14),
 147         .parts                  = davinci_nand_partitions,
 148         .nr_parts               = ARRAY_SIZE(davinci_nand_partitions),
 149         .engine_type            = NAND_ECC_ENGINE_TYPE_ON_HOST,
 150         .bbt_options            = NAND_BBT_USE_FLASH,
 151         .ecc_bits               = 4,
 152 };
 153
 154 static struct resource davinci_nand_resources[] = {
 155         {
 156                 .start          = DM365_ASYNC_EMIF_DATA_CE0_BASE,
 157                 .end            = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1,
 158                 .flags          = IORESOURCE_MEM,
 159         }, {
 160                 .start          = DM365_ASYNC_EMIF_CONTROL_BASE,
 161                 .end            = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 162                 .flags          = IORESOURCE_MEM,
 163         },
 164 };
 165
 166 static struct platform_device davinci_aemif_devices[] = {
 167         {
 168                 .name           = "davinci_nand",
 169                 .id             = 0,
 170                 .num_resources  = ARRAY_SIZE(davinci_nand_resources),
 171                 .resource       = davinci_nand_resources,
 172                 .dev            = {
 173                         .platform_data  = &davinci_nand_data,
 174                 },
 175         }
 176 };
 177
 178 static struct resource davinci_aemif_resources[] = {
 179         {
 180                 .start          = DM365_ASYNC_EMIF_CONTROL_BASE,
 181                 .end            = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
 182                 .flags          = IORESOURCE_MEM,
 183         },
 184 };
 185
 186 static struct aemif_abus_data da850_evm_aemif_abus_data[] = {
 187         {
 188                 .cs             = 1,
 189         },
 190 };
 191
 192 static struct aemif_platform_data davinci_aemif_pdata = {
 193         .abus_data              = da850_evm_aemif_abus_data,
 194         .num_abus_data          = ARRAY_SIZE(da850_evm_aemif_abus_data),
 195         .sub_devices            = davinci_aemif_devices,
 196         .num_sub_devices        = ARRAY_SIZE(davinci_aemif_devices),
 197 };
 198
 199 static struct platform_device davinci_aemif_device = {
 200         .name                   = "ti-aemif",
 201         .id                     = -1,
 202         .dev = {
 203                 .platform_data  = &davinci_aemif_pdata,
 204         },
 205         .resource               = davinci_aemif_resources,
 206         .num_resources          = ARRAY_SIZE(davinci_aemif_resources),
 207 };
 208
 209 static struct nvmem_cell_info davinci_nvmem_cells[] = {
 210         {
 211                 .name           = "macaddr",
 212                 .offset         = 0x7f00,
 213                 .bytes          = ETH_ALEN,
 214         }
 215 };
 216
 217 static struct nvmem_cell_table davinci_nvmem_cell_table = {
 218         .nvmem_name     = "1-00500",
 219         .cells          = davinci_nvmem_cells,
 220         .ncells         = ARRAY_SIZE(davinci_nvmem_cells),
 221 };
 222
 223 static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = {
 224         .nvmem_name     = "1-00500",
 225         .cell_name      = "macaddr",
 226         .dev_id         = "davinci_emac.1",
 227         .con_id         = "mac-address",
 228 };
 229
 230 static const struct property_entry eeprom_properties[] = {
 231         PROPERTY_ENTRY_U32("pagesize", 64),
 232         { }
 233 };
 234
 235 static const struct software_node eeprom_node = {
 236         .properties = eeprom_properties,
 237 };
 238
 239 static struct i2c_board_info i2c_info[] = {
 240         {
 241                 I2C_BOARD_INFO("24c256", 0x50),
 242                 .swnode = &eeprom_node,
 243         },
 244         {
 245                 I2C_BOARD_INFO("tlv320aic3x", 0x18),
 246         },
 247 };
 248
 249 static struct davinci_i2c_platform_data i2c_pdata = {
 250         .bus_freq       = 400   /* kHz */,
 251         .bus_delay      = 0     /* usec */,
 252 };
 253
 254 /* Fixed regulator support */
 255 static struct regulator_consumer_supply fixed_supplies_3_3v[] = {
 256         /* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */
 257         REGULATOR_SUPPLY("AVDD", "1-0018"),
 258         REGULATOR_SUPPLY("DRVDD", "1-0018"),
 259         REGULATOR_SUPPLY("IOVDD", "1-0018"),
 260 };
 261
 262 static struct regulator_consumer_supply fixed_supplies_1_8v[] = {
 263         /* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */
 264         REGULATOR_SUPPLY("DVDD", "1-0018"),
 265 };
 266
 267 static int dm365evm_keyscan_enable(struct device *dev)
 268 {
 269         return davinci_cfg_reg(DM365_KEYSCAN);
 270 }
 271
 272 static unsigned short dm365evm_keymap[] = {
 273         KEY_KP2,
 274         KEY_LEFT,
 275         KEY_EXIT,
 276         KEY_DOWN,
 277         KEY_ENTER,
 278         KEY_UP,
 279         KEY_KP1,
 280         KEY_RIGHT,
 281         KEY_MENU,
 282         KEY_RECORD,
 283         KEY_REWIND,
 284         KEY_KPMINUS,
 285         KEY_STOP,
 286         KEY_FASTFORWARD,
 287         KEY_KPPLUS,
 288         KEY_PLAYPAUSE,
 289         0
 290 };
 291
 292 static struct davinci_ks_platform_data dm365evm_ks_data = {
 293         .device_enable  = dm365evm_keyscan_enable,
 294         .keymap         = dm365evm_keymap,
 295         .keymapsize     = ARRAY_SIZE(dm365evm_keymap),
 296         .rep            = 1,
 297         /* Scan period = strobe + interval */
 298         .strobe         = 0x5,
 299         .interval       = 0x2,
 300         .matrix_type    = DAVINCI_KEYSCAN_MATRIX_4X4,
 301 };
 302
 303 static int cpld_mmc_get_cd(int module)
 304 {
 305         if (!cpld)
 306                 return -ENXIO;
 307
 308         /* low == card present */
 309         return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0));
 310 }
 311
 312 static int cpld_mmc_get_ro(int module)
 313 {
 314         if (!cpld)
 315                 return -ENXIO;
 316
 317         /* high == card's write protect switch active */
 318         return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1));
 319 }
 320
 321 static struct davinci_mmc_config dm365evm_mmc_config = {
 322         .get_cd         = cpld_mmc_get_cd,
 323         .get_ro         = cpld_mmc_get_ro,
 324         .wires          = 4,
 325         .max_freq       = 50000000,
 326         .caps           = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
 327 };
 328
 329 static void dm365evm_emac_configure(void)
 330 {
 331         /*
 332          * EMAC pins are multiplexed with GPIO and UART
 333          * Further details are available at the DM365 ARM
 334          * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127
 335          */
 336         davinci_cfg_reg(DM365_EMAC_TX_EN);
 337         davinci_cfg_reg(DM365_EMAC_TX_CLK);
 338         davinci_cfg_reg(DM365_EMAC_COL);
 339         davinci_cfg_reg(DM365_EMAC_TXD3);
 340         davinci_cfg_reg(DM365_EMAC_TXD2);
 341         davinci_cfg_reg(DM365_EMAC_TXD1);
 342         davinci_cfg_reg(DM365_EMAC_TXD0);
 343         davinci_cfg_reg(DM365_EMAC_RXD3);
 344         davinci_cfg_reg(DM365_EMAC_RXD2);
 345         davinci_cfg_reg(DM365_EMAC_RXD1);
 346         davinci_cfg_reg(DM365_EMAC_RXD0);
 347         davinci_cfg_reg(DM365_EMAC_RX_CLK);
 348         davinci_cfg_reg(DM365_EMAC_RX_DV);
 349         davinci_cfg_reg(DM365_EMAC_RX_ER);
 350         davinci_cfg_reg(DM365_EMAC_CRS);
 351         davinci_cfg_reg(DM365_EMAC_MDIO);
 352         davinci_cfg_reg(DM365_EMAC_MDCLK);
 353
 354         /*
 355          * EMAC interrupts are multiplexed with GPIO interrupts
 356          * Details are available at the DM365 ARM
 357          * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
 358          */
 359         davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH);
 360         davinci_cfg_reg(DM365_INT_EMAC_RXPULSE);
 361         davinci_cfg_reg(DM365_INT_EMAC_TXPULSE);
 362         davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE);
 363 }
 364
 365 static void dm365evm_mmc_configure(void)
 366 {
 367         /*
 368          * MMC/SD pins are multiplexed with GPIO and EMIF
 369          * Further details are available at the DM365 ARM
 370          * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131
 371          */
 372         davinci_cfg_reg(DM365_SD1_CLK);
 373         davinci_cfg_reg(DM365_SD1_CMD);
 374         davinci_cfg_reg(DM365_SD1_DATA3);
 375         davinci_cfg_reg(DM365_SD1_DATA2);
 376         davinci_cfg_reg(DM365_SD1_DATA1);
 377         davinci_cfg_reg(DM365_SD1_DATA0);
 378 }
 379
 380 static struct tvp514x_platform_data tvp5146_pdata = {
 381         .clk_polarity = 0,
 382         .hs_polarity = 1,
 383         .vs_polarity = 1
 384 };
 385
 386 #define TVP514X_STD_ALL        (V4L2_STD_NTSC | V4L2_STD_PAL)
 387 /* Inputs available at the TVP5146 */
 388 static struct v4l2_input tvp5146_inputs[] = {
 389         {
 390                 .index = 0,
 391                 .name = "Composite",
 392                 .type = V4L2_INPUT_TYPE_CAMERA,
 393                 .std = TVP514X_STD_ALL,
 394         },
 395         {
 396                 .index = 1,
 397                 .name = "S-Video",
 398                 .type = V4L2_INPUT_TYPE_CAMERA,
 399                 .std = TVP514X_STD_ALL,
 400         },
 401 };
 402
 403 /*
 404  * this is the route info for connecting each input to decoder
 405  * ouput that goes to vpfe. There is a one to one correspondence
 406  * with tvp5146_inputs
 407  */
 408 static struct vpfe_route tvp5146_routes[] = {
 409         {
 410                 .input = INPUT_CVBS_VI2B,
 411                 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
 412         },
 413 {
 414                 .input = INPUT_SVIDEO_VI2C_VI1C,
 415                 .output = OUTPUT_10BIT_422_EMBEDDED_SYNC,
 416         },
 417 };
 418
 419 static struct vpfe_subdev_info vpfe_sub_devs[] = {
 420         {
 421                 .name = "tvp5146",
 422                 .grp_id = 0,
 423                 .num_inputs = ARRAY_SIZE(tvp5146_inputs),
 424                 .inputs = tvp5146_inputs,
 425                 .routes = tvp5146_routes,
 426                 .can_route = 1,
 427                 .ccdc_if_params = {
 428                         .if_type = VPFE_BT656,
 429                         .hdpol = VPFE_PINPOL_POSITIVE,
 430                         .vdpol = VPFE_PINPOL_POSITIVE,
 431                 },
 432                 .board_info = {
 433                         I2C_BOARD_INFO("tvp5146", 0x5d),
 434                         .platform_data = &tvp5146_pdata,
 435                 },
 436         },
 437 };
 438
 439 static struct vpfe_config vpfe_cfg = {
 440         .num_subdevs = ARRAY_SIZE(vpfe_sub_devs),
 441         .sub_devs = vpfe_sub_devs,
 442         .i2c_adapter_id = 1,
 443         .card_name = "DM365 EVM",
 444         .ccdc = "ISIF",
 445 };
 446
 447 /* venc standards timings */
 448 static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = {
 449         {
 450                 .name           = "ntsc",
 451                 .timings_type   = VPBE_ENC_STD,
 452                 .std_id         = V4L2_STD_NTSC,
 453                 .interlaced     = 1,
 454                 .xres           = 720,
 455                 .yres           = 480,
 456                 .aspect         = {11, 10},
 457                 .fps            = {30000, 1001},
 458                 .left_margin    = 0x79,
 459                 .upper_margin   = 0x10,
 460         },
 461         {
 462                 .name           = "pal",
 463                 .timings_type   = VPBE_ENC_STD,
 464                 .std_id         = V4L2_STD_PAL,
 465                 .interlaced     = 1,
 466                 .xres           = 720,
 467                 .yres           = 576,
 468                 .aspect         = {54, 59},
 469                 .fps            = {25, 1},
 470                 .left_margin    = 0x7E,
 471                 .upper_margin   = 0x16,
 472         },
 473 };
 474
 475 /* venc dv timings */
 476 static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = {
 477         {
 478                 .name           = "480p59_94",
 479                 .timings_type   = VPBE_ENC_DV_TIMINGS,
 480                 .dv_timings     = V4L2_DV_BT_CEA_720X480P59_94,
 481                 .interlaced     = 0,
 482                 .xres           = 720,
 483                 .yres           = 480,
 484                 .aspect         = {1, 1},
 485                 .fps            = {5994, 100},
 486                 .left_margin    = 0x8F,
 487                 .upper_margin   = 0x2D,
 488         },
 489         {
 490                 .name           = "576p50",
 491                 .timings_type   = VPBE_ENC_DV_TIMINGS,
 492                 .dv_timings     = V4L2_DV_BT_CEA_720X576P50,
 493                 .interlaced     = 0,
 494                 .xres           = 720,
 495                 .yres           = 576,
 496                 .aspect         = {1, 1},
 497                 .fps            = {50, 1},
 498                 .left_margin    = 0x8C,
 499                 .upper_margin   = 0x36,
 500         },
 501         {
 502                 .name           = "720p60",
 503                 .timings_type   = VPBE_ENC_DV_TIMINGS,
 504                 .dv_timings     = V4L2_DV_BT_CEA_1280X720P60,
 505                 .interlaced     = 0,
 506                 .xres           = 1280,
 507                 .yres           = 720,
 508                 .aspect         = {1, 1},
 509                 .fps            = {60, 1},
 510                 .left_margin    = 0x117,
 511                 .right_margin   = 70,
 512                 .upper_margin   = 38,
 513                 .lower_margin   = 3,
 514                 .hsync_len      = 80,
 515                 .vsync_len      = 5,
 516         },
 517         {
 518                 .name           = "1080i60",
 519                 .timings_type   = VPBE_ENC_DV_TIMINGS,
 520                 .dv_timings     = V4L2_DV_BT_CEA_1920X1080I60,
 521                 .interlaced     = 1,
 522                 .xres           = 1920,
 523                 .yres           = 1080,
 524                 .aspect         = {1, 1},
 525                 .fps            = {30, 1},
 526                 .left_margin    = 0xc9,
 527                 .right_margin   = 80,
 528                 .upper_margin   = 30,
 529                 .lower_margin   = 3,
 530                 .hsync_len      = 88,
 531                 .vsync_len      = 5,
 532         },
 533 };
 534
 535 #define VENC_STD_ALL    (V4L2_STD_NTSC | V4L2_STD_PAL)
 536
 537 /*
 538  * The outputs available from VPBE + ecnoders. Keep the
 539  * the order same as that of encoders. First those from venc followed by that
 540  * from encoders. Index in the output refers to index on a particular
 541  * encoder.Driver uses this index to pass it to encoder when it supports more
 542  * than one output. Application uses index of the array to set an output.
 543  */
 544 static struct vpbe_output dm365evm_vpbe_outputs[] = {
 545         {
 546                 .output         = {
 547                         .index          = 0,
 548                         .name           = "Composite",
 549                         .type           = V4L2_OUTPUT_TYPE_ANALOG,
 550                         .std            = VENC_STD_ALL,
 551                         .capabilities   = V4L2_OUT_CAP_STD,
 552                 },
 553                 .subdev_name    = DM365_VPBE_VENC_SUBDEV_NAME,
 554                 .default_mode   = "ntsc",
 555                 .num_modes      = ARRAY_SIZE(dm365evm_enc_std_timing),
 556                 .modes          = dm365evm_enc_std_timing,
 557                 .if_params      = MEDIA_BUS_FMT_FIXED,
 558         },
 559         {
 560                 .output         = {
 561                         .index          = 1,
 562                         .name           = "Component",
 563                         .type           = V4L2_OUTPUT_TYPE_ANALOG,
 564                         .capabilities   = V4L2_OUT_CAP_DV_TIMINGS,
 565                 },
 566                 .subdev_name    = DM365_VPBE_VENC_SUBDEV_NAME,
 567                 .default_mode   = "480p59_94",
 568                 .num_modes      = ARRAY_SIZE(dm365evm_enc_preset_timing),
 569                 .modes          = dm365evm_enc_preset_timing,
 570                 .if_params      = MEDIA_BUS_FMT_FIXED,
 571         },
 572 };
 573
 574 /*
 575  * Amplifiers on the board
 576  */
 577 static struct ths7303_platform_data ths7303_pdata = {
 578         .ch_1 = 3,
 579         .ch_2 = 3,
 580         .ch_3 = 3,
 581 };
 582
 583 static struct amp_config_info vpbe_amp = {
 584         .module_name    = "ths7303",
 585         .is_i2c         = 1,
 586         .board_info     = {
 587                 I2C_BOARD_INFO("ths7303", 0x2c),
 588                 .platform_data = &ths7303_pdata,
 589         }
 590 };
 591
 592 static struct vpbe_config dm365evm_display_cfg = {
 593         .module_name    = "dm365-vpbe-display",
 594         .i2c_adapter_id = 1,
 595         .amp            = &vpbe_amp,
 596         .osd            = {
 597                 .module_name    = DM365_VPBE_OSD_SUBDEV_NAME,
 598         },
 599         .venc           = {
 600                 .module_name    = DM365_VPBE_VENC_SUBDEV_NAME,
 601         },
 602         .num_outputs    = ARRAY_SIZE(dm365evm_vpbe_outputs),
 603         .outputs        = dm365evm_vpbe_outputs,
 604 };
 605
 606 static void __init evm_init_i2c(void)
 607 {
 608         davinci_init_i2c(&i2c_pdata);
 609         i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
 610 }
 611
 612 static inline int have_leds(void)
 613 {
 614 #ifdef CONFIG_LEDS_CLASS
 615         return 1;
 616 #else
 617         return 0;
 618 #endif
 619 }
 620
 621 struct cpld_led {
 622         struct led_classdev     cdev;
 623         u8                      mask;
 624 };
 625
 626 static const struct {
 627         const char *name;
 628         const char *trigger;
 629 } cpld_leds[] = {
 630         { "dm365evm::ds2", },
 631         { "dm365evm::ds3", },
 632         { "dm365evm::ds4", },
 633         { "dm365evm::ds5", },
 634         { "dm365evm::ds6", "nand-disk", },
 635         { "dm365evm::ds7", "mmc1", },
 636         { "dm365evm::ds8", "mmc0", },
 637         { "dm365evm::ds9", "heartbeat", },
 638 };
 639
 640 static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b)
 641 {
 642         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 643         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 644
 645         if (b != LED_OFF)
 646                 reg &= ~led->mask;
 647         else
 648                 reg |= led->mask;
 649         __raw_writeb(reg, cpld + CPLD_LEDS);
 650 }
 651
 652 static enum led_brightness cpld_led_get(struct led_classdev *cdev)
 653 {
 654         struct cpld_led *led = container_of(cdev, struct cpld_led, cdev);
 655         u8 reg = __raw_readb(cpld + CPLD_LEDS);
 656
 657         return (reg & led->mask) ? LED_OFF : LED_FULL;
 658 }
 659
 660 static int __init cpld_leds_init(void)
 661 {
 662         int     i;
 663
 664         if (!have_leds() ||  !cpld)
 665                 return 0;
 666
 667         /* setup LEDs */
 668         __raw_writeb(0xff, cpld + CPLD_LEDS);
 669         for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) {
 670                 struct cpld_led *led;
 671
 672                 led = kzalloc(sizeof(*led), GFP_KERNEL);
 673                 if (!led)
 674                         break;
 675
 676                 led->cdev.name = cpld_leds[i].name;
 677                 led->cdev.brightness_set = cpld_led_set;
 678                 led->cdev.brightness_get = cpld_led_get;
 679                 led->cdev.default_trigger = cpld_leds[i].trigger;
 680                 led->mask = BIT(i);
 681
 682                 if (led_classdev_register(NULL, &led->cdev) < 0) {
 683                         kfree(led);
 684                         break;
 685                 }
 686         }
 687
 688         return 0;
 689 }
 690 /* run after subsys_initcall() for LEDs */
 691 fs_initcall(cpld_leds_init);
 692
 693
 694 static void __init evm_init_cpld(void)
 695 {
 696         u8 mux, resets;
 697         const char *label;
 698         struct clk *aemif_clk;
 699         int rc;
 700
 701         /* Make sure we can configure the CPLD through CS1.  Then
 702          * leave it on for later access to MMC and LED registers.
 703          */
 704         aemif_clk = clk_get(NULL, "aemif");
 705         if (IS_ERR(aemif_clk))
 706                 return;
 707         clk_prepare_enable(aemif_clk);
 708
 709         if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE,
 710                         "cpld") == NULL)
 711                 goto fail;
 712         cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE);
 713         if (!cpld) {
 714                 release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE,
 715                                 SECTION_SIZE);
 716 fail:
 717                 pr_err("ERROR: can't map CPLD\n");
 718                 clk_disable_unprepare(aemif_clk);
 719                 return;
 720         }
 721
 722         /* External muxing for some signals */
 723         mux = 0;
 724
 725         /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read).
 726          * NOTE:  SW4 bus width setting must match!
 727          */
 728         if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) {
 729                 /* external keypad mux */
 730                 mux |= BIT(7);
 731
 732                 rc = platform_device_register(&davinci_aemif_device);
 733                 if (rc)
 734                         pr_warn("%s(): error registering the aemif device: %d\n",
 735                                 __func__, rc);
 736         } else {
 737                 /* no OneNAND support yet */
 738         }
 739
 740         /* Leave external chips in reset when unused. */
 741         resets = BIT(3) | BIT(2) | BIT(1) | BIT(0);
 742
 743         /* Static video input config with SN74CBT16214 1-of-3 mux:
 744          *  - port b1 == tvp7002 (mux lowbits == 1 or 6)
 745          *  - port b2 == imager (mux lowbits == 2 or 7)
 746          *  - port b3 == tvp5146 (mux lowbits == 5)
 747          *
 748          * Runtime switching could work too, with limitations.
 749          */
 750         if (have_imager()) {
 751                 label = "HD imager";
 752                 mux |= 2;
 753
 754                 /* externally mux MMC1/ENET/AIC33 to imager */
 755                 mux |= BIT(6) | BIT(5) | BIT(3);
 756         } else {
 757                 struct davinci_soc_info *soc_info = &davinci_soc_info;
 758
 759                 /* we can use MMC1 ... */
 760                 dm365evm_mmc_configure();
 761                 davinci_setup_mmc(1, &dm365evm_mmc_config);
 762
 763                 /* ... and ENET ... */
 764                 dm365evm_emac_configure();
 765                 soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID;
 766                 resets &= ~BIT(3);
 767
 768                 /* ... and AIC33 */
 769                 resets &= ~BIT(1);
 770
 771                 if (have_tvp7002()) {
 772                         mux |= 1;
 773                         resets &= ~BIT(2);
 774                         label = "tvp7002 HD";
 775                 } else {
 776                         /* default to tvp5146 */
 777                         mux |= 5;
 778                         resets &= ~BIT(0);
 779                         label = "tvp5146 SD";
 780                 }
 781         }
 782         __raw_writeb(mux, cpld + CPLD_MUX);
 783         __raw_writeb(resets, cpld + CPLD_RESETS);
 784         pr_info("EVM: %s video input\n", label);
 785
 786         /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
 787 }
 788
 789 static void __init dm365_evm_map_io(void)
 790 {
 791         dm365_init();
 792 }
 793
 794 static struct spi_eeprom at25640 = {
 795         .byte_len       = SZ_64K / 8,
 796         .name           = "at25640",
 797         .page_size      = 32,
 798         .flags          = EE_ADDR2,
 799 };
 800
 801 static const struct spi_board_info dm365_evm_spi_info[] __initconst = {
 802         {
 803                 .modalias       = "at25",
 804                 .platform_data  = &at25640,
 805                 .max_speed_hz   = 10 * 1000 * 1000,
 806                 .bus_num        = 0,
 807                 .chip_select    = 0,
 808                 .mode           = SPI_MODE_0,
 809         },
 810 };
 811
 812 static __init void dm365_evm_init(void)
 813 {
 814         int ret;
 815
 816         dm365_register_clocks();
 817
 818         ret = dm365_gpio_register();
 819         if (ret)
 820                 pr_warn("%s: GPIO init failed: %d\n", __func__, ret);
 821
 822         regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v,
 823                                      ARRAY_SIZE(fixed_supplies_1_8v), 1800000);
 824         regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v,
 825                                      ARRAY_SIZE(fixed_supplies_3_3v), 3300000);
 826
 827         nvmem_add_cell_table(&davinci_nvmem_cell_table);
 828         nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1);
 829
 830         evm_init_i2c();
 831         davinci_serial_init(dm365_serial_device);
 832
 833         dm365evm_emac_configure();
 834         dm365evm_mmc_configure();
 835
 836         davinci_setup_mmc(0, &dm365evm_mmc_config);
 837
 838         dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg);
 839
 840         /* maybe setup mmc1/etc ... _after_ mmc0 */
 841         evm_init_cpld();
 842
 843 #ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC
 844         dm365_init_asp();
 845 #elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC)
 846         dm365_init_vc();
 847 #endif
 848         dm365_init_rtc();
 849         dm365_init_ks(&dm365evm_ks_data);
 850
 851         dm365_init_spi0(BIT(0), dm365_evm_spi_info,
 852                         ARRAY_SIZE(dm365_evm_spi_info));
 853 }
 854
 855 MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
 856         .atag_offset    = 0x100,
 857         .map_io         = dm365_evm_map_io,
 858         .init_irq       = dm365_init_irq,
 859         .init_time      = dm365_init_time,
 860         .init_machine   = dm365_evm_init,
 861         .init_late      = davinci_init_late,
 862         .dma_zone_size  = SZ_128M,
 863 MACHINE_END
 864