2 * arch/arm/mach-at91/pm_slow_clock.S
4 * Copyright (C) 2006 Savin Zlobec
7 * Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/linkage.h>
15 #include <linux/clk/at91_pmc.h>
17 #include "generated/at91_pm_data-offsets.h"
19 #define SRAMC_SELF_FRESH_ACTIVE 0x01
20 #define SRAMC_SELF_FRESH_EXIT 0x00
27 * Wait until master clock is ready (after switching master clock source)
30 1: ldr tmp1, [pmc, #AT91_PMC_SR]
31 tst tmp1, #AT91_PMC_MCKRDY
36 * Wait until master oscillator has stabilized.
39 1: ldr tmp1, [pmc, #AT91_PMC_SR]
40 tst tmp1, #AT91_PMC_MOSCS
45 * Wait for main oscillator selection is done
48 1: ldr tmp1, [pmc, #AT91_PMC_SR]
49 tst tmp1, #AT91_PMC_MOSCSELS
54 * Put the processor to enter the idle state
58 #if defined(CONFIG_CPU_V7)
59 mov tmp1, #AT91_PMC_PCK
60 str tmp1, [pmc, #AT91_PMC_SCDR]
64 wfi @ Wait For Interrupt
66 mcr p15, 0, tmp1, c7, c0, 4
76 * void at91_suspend_sram_fn(struct at91_pm_data*)
78 * @r0: base address of struct at91_pm_data
80 /* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */
82 ENTRY(at91_pm_suspend_in_sram)
83 /* Save registers on stack */
84 stmfd sp!, {r4 - r12, lr}
86 /* Drain write buffer */
88 mcr p15, 0, tmp1, c7, c10, 4
90 ldr tmp1, [r0, #PM_DATA_PMC]
92 ldr tmp1, [r0, #PM_DATA_RAMC0]
94 ldr tmp1, [r0, #PM_DATA_RAMC1]
95 str tmp1, .sramc1_base
96 ldr tmp1, [r0, #PM_DATA_MEMCTRL]
98 ldr tmp1, [r0, #PM_DATA_MODE]
100 /* Both ldrne below are here to preload their address in the TLB */
101 ldr tmp1, [r0, #PM_DATA_SHDWC]
104 ldrne tmp2, [tmp1, #0]
105 ldr tmp1, [r0, #PM_DATA_SFRBU]
108 ldrne tmp2, [tmp1, #0x10]
110 /* Active the self-refresh mode */
111 mov r0, #SRAMC_SELF_FRESH_ACTIVE
112 bl at91_sramc_self_refresh
115 cmp r0, #AT91_PM_STANDBY
117 cmp r0, #AT91_PM_BACKUP
124 /* Wait for interrupt */
134 /* Exit the self-refresh mode */
135 mov r0, #SRAMC_SELF_FRESH_EXIT
136 bl at91_sramc_self_refresh
138 /* Restore registers, and return */
139 ldmfd sp!, {r4 - r12, pc}
140 ENDPROC(at91_pm_suspend_in_sram)
142 ENTRY(at91_backup_mode)
143 /* Switch the master clock source to slow clock. */
145 ldr tmp1, [pmc, #AT91_PMC_MCKR]
146 bic tmp1, tmp1, #AT91_PMC_CSS
147 str tmp1, [pmc, #AT91_PMC_MCKR]
154 str tmp1, [r0, #0x10]
158 mov tmp1, #0xA5000000
161 ENDPROC(at91_backup_mode)
163 .macro at91_pm_ulp0_mode
166 /* Turn off the crystal oscillator */
167 ldr tmp1, [pmc, #AT91_CKGR_MOR]
168 bic tmp1, tmp1, #AT91_PMC_MOSCEN
169 orr tmp1, tmp1, #AT91_PMC_KEY
170 str tmp1, [pmc, #AT91_CKGR_MOR]
172 /* Save RC oscillator state */
173 ldr tmp1, [pmc, #AT91_PMC_SR]
174 str tmp1, .saved_osc_status
175 tst tmp1, #AT91_PMC_MOSCRCS
178 /* Turn off RC oscillator */
179 ldr tmp1, [pmc, #AT91_CKGR_MOR]
180 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
181 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
182 orr tmp1, tmp1, #AT91_PMC_KEY
183 str tmp1, [pmc, #AT91_CKGR_MOR]
185 /* Wait main RC disabled done */
186 2: ldr tmp1, [pmc, #AT91_PMC_SR]
187 tst tmp1, #AT91_PMC_MOSCRCS
190 /* Wait for interrupt */
193 /* Restore RC oscillator state */
194 ldr tmp1, .saved_osc_status
195 tst tmp1, #AT91_PMC_MOSCRCS
198 /* Turn on RC oscillator */
199 ldr tmp1, [pmc, #AT91_CKGR_MOR]
200 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
201 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
202 orr tmp1, tmp1, #AT91_PMC_KEY
203 str tmp1, [pmc, #AT91_CKGR_MOR]
205 /* Wait main RC stabilization */
206 3: ldr tmp1, [pmc, #AT91_PMC_SR]
207 tst tmp1, #AT91_PMC_MOSCRCS
210 /* Turn on the crystal oscillator */
211 4: ldr tmp1, [pmc, #AT91_CKGR_MOR]
212 orr tmp1, tmp1, #AT91_PMC_MOSCEN
213 orr tmp1, tmp1, #AT91_PMC_KEY
214 str tmp1, [pmc, #AT91_CKGR_MOR]
220 * Note: This procedure only applies on the platform which uses
221 * the external crystal oscillator as a main clock source.
223 .macro at91_pm_ulp1_mode
226 /* Save RC oscillator state and check if it is enabled. */
227 ldr tmp1, [pmc, #AT91_PMC_SR]
228 str tmp1, .saved_osc_status
229 tst tmp1, #AT91_PMC_MOSCRCS
232 /* Enable RC oscillator */
233 ldr tmp1, [pmc, #AT91_CKGR_MOR]
234 orr tmp1, tmp1, #AT91_PMC_MOSCRCEN
235 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
236 orr tmp1, tmp1, #AT91_PMC_KEY
237 str tmp1, [pmc, #AT91_CKGR_MOR]
239 /* Wait main RC stabilization */
240 1: ldr tmp1, [pmc, #AT91_PMC_SR]
241 tst tmp1, #AT91_PMC_MOSCRCS
244 /* Switch the main clock source to 12-MHz RC oscillator */
245 2: ldr tmp1, [pmc, #AT91_CKGR_MOR]
246 bic tmp1, tmp1, #AT91_PMC_MOSCSEL
247 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
248 orr tmp1, tmp1, #AT91_PMC_KEY
249 str tmp1, [pmc, #AT91_CKGR_MOR]
253 /* Disable the crystal oscillator */
254 ldr tmp1, [pmc, #AT91_CKGR_MOR]
255 bic tmp1, tmp1, #AT91_PMC_MOSCEN
256 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
257 orr tmp1, tmp1, #AT91_PMC_KEY
258 str tmp1, [pmc, #AT91_CKGR_MOR]
260 /* Switch the master clock source to main clock */
261 ldr tmp1, [pmc, #AT91_PMC_MCKR]
262 bic tmp1, tmp1, #AT91_PMC_CSS
263 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
264 str tmp1, [pmc, #AT91_PMC_MCKR]
268 /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
269 ldr tmp1, [pmc, #AT91_CKGR_MOR]
270 orr tmp1, tmp1, #AT91_PMC_WAITMODE
271 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
272 orr tmp1, tmp1, #AT91_PMC_KEY
273 str tmp1, [pmc, #AT91_CKGR_MOR]
277 /* Enable the crystal oscillator */
278 ldr tmp1, [pmc, #AT91_CKGR_MOR]
279 orr tmp1, tmp1, #AT91_PMC_MOSCEN
280 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
281 orr tmp1, tmp1, #AT91_PMC_KEY
282 str tmp1, [pmc, #AT91_CKGR_MOR]
286 /* Switch the master clock source to slow clock */
287 ldr tmp1, [pmc, #AT91_PMC_MCKR]
288 bic tmp1, tmp1, #AT91_PMC_CSS
289 str tmp1, [pmc, #AT91_PMC_MCKR]
293 /* Switch main clock source to crystal oscillator */
294 ldr tmp1, [pmc, #AT91_CKGR_MOR]
295 orr tmp1, tmp1, #AT91_PMC_MOSCSEL
296 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
297 orr tmp1, tmp1, #AT91_PMC_KEY
298 str tmp1, [pmc, #AT91_CKGR_MOR]
302 /* Switch the master clock source to main clock */
303 ldr tmp1, [pmc, #AT91_PMC_MCKR]
304 bic tmp1, tmp1, #AT91_PMC_CSS
305 orr tmp1, tmp1, #AT91_PMC_CSS_MAIN
306 str tmp1, [pmc, #AT91_PMC_MCKR]
310 /* Restore RC oscillator state */
311 ldr tmp1, .saved_osc_status
312 tst tmp1, #AT91_PMC_MOSCRCS
315 /* Disable RC oscillator */
316 ldr tmp1, [pmc, #AT91_CKGR_MOR]
317 bic tmp1, tmp1, #AT91_PMC_MOSCRCEN
318 bic tmp1, tmp1, #AT91_PMC_KEY_MASK
319 orr tmp1, tmp1, #AT91_PMC_KEY
320 str tmp1, [pmc, #AT91_CKGR_MOR]
322 /* Wait RC oscillator disable done */
323 4: ldr tmp1, [pmc, #AT91_PMC_SR]
324 tst tmp1, #AT91_PMC_MOSCRCS
333 /* Save Master clock setting */
334 ldr tmp1, [pmc, #AT91_PMC_MCKR]
335 str tmp1, .saved_mckr
338 * Set the Master clock source to slow clock
340 bic tmp1, tmp1, #AT91_PMC_CSS
341 str tmp1, [pmc, #AT91_PMC_MCKR]
346 cmp r0, #AT91_PM_ULP1
360 * Restore master clock setting
362 ldr tmp1, .saved_mckr
363 str tmp1, [pmc, #AT91_PMC_MCKR]
368 ENDPROC(at91_ulp_mode)
371 * void at91_sramc_self_refresh(unsigned int is_active)
374 * @r0: 1 - active self-refresh mode
375 * 0 - exit self-refresh mode
378 * @r2: base address of the sram controller
381 ENTRY(at91_sramc_self_refresh)
385 cmp r1, #AT91_MEMCTRL_MC
389 * at91rm9200 Memory controller
393 * For exiting the self-refresh mode, do nothing,
394 * automatically exit the self-refresh mode.
396 tst r0, #SRAMC_SELF_FRESH_ACTIVE
399 /* Active SDRAM self-refresh mode */
401 str r3, [r2, #AT91_MC_SDRAMC_SRR]
405 cmp r1, #AT91_MEMCTRL_DDRSDR
409 * DDR Memory controller
411 tst r0, #SRAMC_SELF_FRESH_ACTIVE
414 /* LPDDR1 --> force DDR2 mode during self-refresh */
415 ldr r3, [r2, #AT91_DDRSDRC_MDR]
416 str r3, .saved_sam9_mdr
417 bic r3, r3, #~AT91_DDRSDRC_MD
418 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
419 ldreq r3, [r2, #AT91_DDRSDRC_MDR]
420 biceq r3, r3, #AT91_DDRSDRC_MD
421 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
422 streq r3, [r2, #AT91_DDRSDRC_MDR]
424 /* Active DDRC self-refresh mode */
425 ldr r3, [r2, #AT91_DDRSDRC_LPR]
426 str r3, .saved_sam9_lpr
427 bic r3, r3, #AT91_DDRSDRC_LPCB
428 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
429 str r3, [r2, #AT91_DDRSDRC_LPR]
431 /* If using the 2nd ddr controller */
436 ldr r3, [r2, #AT91_DDRSDRC_MDR]
437 str r3, .saved_sam9_mdr1
438 bic r3, r3, #~AT91_DDRSDRC_MD
439 cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR
440 ldreq r3, [r2, #AT91_DDRSDRC_MDR]
441 biceq r3, r3, #AT91_DDRSDRC_MD
442 orreq r3, r3, #AT91_DDRSDRC_MD_DDR2
443 streq r3, [r2, #AT91_DDRSDRC_MDR]
445 /* Active DDRC self-refresh mode */
446 ldr r3, [r2, #AT91_DDRSDRC_LPR]
447 str r3, .saved_sam9_lpr1
448 bic r3, r3, #AT91_DDRSDRC_LPCB
449 orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH
450 str r3, [r2, #AT91_DDRSDRC_LPR]
456 /* Restore MDR in case of LPDDR1 */
457 ldr r3, .saved_sam9_mdr
458 str r3, [r2, #AT91_DDRSDRC_MDR]
459 /* Restore LPR on AT91 with DDRAM */
460 ldr r3, .saved_sam9_lpr
461 str r3, [r2, #AT91_DDRSDRC_LPR]
463 /* If using the 2nd ddr controller */
466 ldrne r3, .saved_sam9_mdr1
467 strne r3, [r2, #AT91_DDRSDRC_MDR]
468 ldrne r3, .saved_sam9_lpr1
469 strne r3, [r2, #AT91_DDRSDRC_LPR]
474 * SDRAMC Memory controller
477 tst r0, #SRAMC_SELF_FRESH_ACTIVE
480 /* Active SDRAMC self-refresh mode */
481 ldr r3, [r2, #AT91_SDRAMC_LPR]
482 str r3, .saved_sam9_lpr
483 bic r3, r3, #AT91_SDRAMC_LPCB
484 orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH
485 str r3, [r2, #AT91_SDRAMC_LPR]
488 ldr r3, .saved_sam9_lpr
489 str r3, [r2, #AT91_SDRAMC_LPR]
493 ENDPROC(at91_sramc_self_refresh)
522 ENTRY(at91_pm_suspend_in_sram_sz)
523 .word .-at91_pm_suspend_in_sram