1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
6 * Copyright (C) 2005 David Brownell
9 #include <linux/genalloc.h>
11 #include <linux/of_address.h>
13 #include <linux/of_fdt.h>
14 #include <linux/of_platform.h>
15 #include <linux/parser.h>
16 #include <linux/suspend.h>
18 #include <linux/clk/at91_pmc.h>
19 #include <linux/platform_data/atmel.h>
21 #include <soc/at91/pm.h>
23 #include <asm/cacheflush.h>
24 #include <asm/fncpy.h>
25 #include <asm/system_misc.h>
26 #include <asm/suspend.h>
31 #define BACKUP_DDR_PHY_CALIBRATION (9)
34 * struct at91_pm_bu - AT91 power management backup unit data structure
35 * @suspended: true if suspended to backup mode
37 * @canary: canary data for memory checking after exit from backup mode
39 * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words
44 unsigned long reserved;
47 unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
51 * struct at91_pm_sfrbu_offsets: registers mapping for SFRBU
52 * @pswbu: power switch BU control registers
54 struct at91_pm_sfrbu_regs {
64 * struct at91_soc_pm - AT91 SoC power management data structure
65 * @config_shdwc_ws: wakeup sources configuration function for SHDWC
66 * @config_pmc_ws: wakeup srouces configuration function for PMC
67 * @ws_ids: wakup sources of_device_id array
68 * @data: PM data to be used on last phase of suspend
69 * @sfrbu_regs: SFRBU registers mapping
70 * @bu: backup unit mapped data (for backup mode)
71 * @memcs: memory chip select
74 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
75 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
76 const struct of_device_id *ws_ids;
77 struct at91_pm_bu *bu;
78 struct at91_pm_data data;
79 struct at91_pm_sfrbu_regs sfrbu_regs;
84 * enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes
85 * @AT91_PM_IOMAP_SHDWC: SHDWC controller
86 * @AT91_PM_IOMAP_SFRBU: SFRBU controller
93 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name)
95 static struct at91_soc_pm soc_pm = {
97 .standby_mode = AT91_PM_STANDBY,
98 .suspend_mode = AT91_PM_ULP0,
102 static const match_table_t pm_modes __initconst = {
103 { AT91_PM_STANDBY, "standby" },
104 { AT91_PM_ULP0, "ulp0" },
105 { AT91_PM_ULP0_FAST, "ulp0-fast" },
106 { AT91_PM_ULP1, "ulp1" },
107 { AT91_PM_BACKUP, "backup" },
111 #define at91_ramc_read(id, field) \
112 __raw_readl(soc_pm.data.ramc[id] + field)
114 #define at91_ramc_write(id, field, value) \
115 __raw_writel(value, soc_pm.data.ramc[id] + field)
117 static int at91_pm_valid_state(suspend_state_t state)
121 case PM_SUSPEND_STANDBY:
130 static int canary = 0xA5A5A5A5;
132 struct wakeup_source_info {
133 unsigned int pmc_fsmr_bit;
134 unsigned int shdwc_mr_bit;
138 static const struct wakeup_source_info ws_info[] = {
139 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
140 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
141 { .pmc_fsmr_bit = AT91_PMC_USBAL },
142 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
143 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
144 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
147 static const struct of_device_id sama5d2_ws_ids[] = {
148 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
149 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
150 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
151 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
152 { .compatible = "usb-ohci", .data = &ws_info[2] },
153 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
154 { .compatible = "usb-ehci", .data = &ws_info[2] },
155 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
159 static const struct of_device_id sam9x60_ws_ids[] = {
160 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
161 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
162 { .compatible = "usb-ohci", .data = &ws_info[2] },
163 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
164 { .compatible = "usb-ehci", .data = &ws_info[2] },
165 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
166 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
170 static const struct of_device_id sama7g5_ws_ids[] = {
171 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
172 { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
173 { .compatible = "usb-ohci", .data = &ws_info[2] },
174 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
175 { .compatible = "usb-ehci", .data = &ws_info[2] },
176 { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
177 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
181 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
183 const struct wakeup_source_info *wsi;
184 const struct of_device_id *match;
185 struct platform_device *pdev;
186 struct device_node *np;
187 unsigned int mode = 0, polarity = 0, val = 0;
189 if (pm_mode != AT91_PM_ULP1)
192 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
196 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
200 if (soc_pm.config_shdwc_ws)
201 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
204 val = readl(soc_pm.data.shdwc + 0x04);
206 /* Loop through defined wakeup sources. */
207 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
208 pdev = of_find_device_by_node(np);
212 if (device_may_wakeup(&pdev->dev)) {
215 /* Check if enabled on SHDWC. */
216 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
219 mode |= wsi->pmc_fsmr_bit;
220 if (wsi->set_polarity)
221 polarity |= wsi->pmc_fsmr_bit;
225 put_device(&pdev->dev);
229 if (soc_pm.config_pmc_ws)
230 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
232 pr_err("AT91: PM: no ULP1 wakeup sources found!");
235 return mode ? 0 : -EPERM;
238 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
244 val = readl(shdwc + 0x0c);
245 *mode |= (val & 0x3ff);
246 *polarity |= ((val >> 16) & 0x3ff);
251 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
253 writel(mode, pmc + AT91_PMC_FSMR);
254 writel(polarity, pmc + AT91_PMC_FSPR);
259 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
261 writel(mode, pmc + AT91_PMC_FSMR);
267 * Called after processes are frozen, but before we shutdown devices.
269 static int at91_pm_begin(suspend_state_t state)
275 soc_pm.data.mode = soc_pm.data.suspend_mode;
278 case PM_SUSPEND_STANDBY:
279 soc_pm.data.mode = soc_pm.data.standby_mode;
283 soc_pm.data.mode = -1;
286 ret = at91_pm_config_ws(soc_pm.data.mode, true);
290 if (soc_pm.data.mode == AT91_PM_BACKUP)
291 soc_pm.bu->suspended = 1;
293 soc_pm.bu->suspended = 0;
299 * Verify that all the clocks are correct before entering
302 static int at91_pm_verify_clocks(void)
307 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
309 /* USB must not be using PLLB */
310 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
311 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
315 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
316 for (i = 0; i < 4; i++) {
319 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
321 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
322 if (css != AT91_PMC_CSS_SLOW) {
323 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
332 * Call this from platform driver suspend() to see how deeply to suspend.
333 * For example, some controllers (like OHCI) need one of the PLL clocks
334 * in order to act as a wakeup source, and those are not available when
335 * going into slow clock mode.
337 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
338 * the very same problem (but not using at91 main_clk), and it'd be better
339 * to add one generic API rather than lots of platform-specific ones.
341 int at91_suspend_entering_slow_clock(void)
343 return (soc_pm.data.mode >= AT91_PM_ULP0);
345 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
347 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
348 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
349 extern u32 at91_pm_suspend_in_sram_sz;
351 static int at91_suspend_finish(unsigned long val)
355 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
357 * The 1st 8 words of memory might get corrupted in the process
358 * of DDR PHY recalibration; it is saved here in securam and it
359 * will be restored later, after recalibration, by bootloader
361 for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++)
362 soc_pm.bu->ddr_phy_calibration[i] =
363 *((unsigned int *)soc_pm.memcs + (i - 1));
369 at91_suspend_sram_fn(&soc_pm.data);
374 static void at91_pm_switch_ba_to_vbat(void)
376 unsigned int offset = offsetof(struct at91_pm_sfrbu_regs, pswbu);
379 /* Just for safety. */
380 if (!soc_pm.data.sfrbu)
383 val = readl(soc_pm.data.sfrbu + offset);
385 /* Already on VBAT. */
386 if (!(val & soc_pm.sfrbu_regs.pswbu.state))
389 val &= ~soc_pm.sfrbu_regs.pswbu.softsw;
390 val |= soc_pm.sfrbu_regs.pswbu.key | soc_pm.sfrbu_regs.pswbu.ctrl;
391 writel(val, soc_pm.data.sfrbu + offset);
393 /* Wait for update. */
394 val = readl(soc_pm.data.sfrbu + offset);
395 while (val & soc_pm.sfrbu_regs.pswbu.state)
396 val = readl(soc_pm.data.sfrbu + offset);
399 static void at91_pm_suspend(suspend_state_t state)
401 if (soc_pm.data.mode == AT91_PM_BACKUP) {
402 at91_pm_switch_ba_to_vbat();
404 cpu_suspend(0, at91_suspend_finish);
406 /* The SRAM is lost between suspend cycles */
407 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
408 &at91_pm_suspend_in_sram,
409 at91_pm_suspend_in_sram_sz);
411 at91_suspend_finish(0);
418 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
419 * event sources; and reduces DRAM power. But otherwise it's identical to
420 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
422 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
423 * suspend more deeply, the master clock switches to the clk32k and turns off
424 * the main oscillator
426 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
428 static int at91_pm_enter(suspend_state_t state)
430 #ifdef CONFIG_PINCTRL_AT91
432 * FIXME: this is needed to communicate between the pinctrl driver and
433 * the PM implementation in the machine. Possibly part of the PM
434 * implementation should be moved down into the pinctrl driver and get
435 * called as part of the generic suspend/resume path.
437 at91_pinctrl_gpio_suspend();
442 case PM_SUSPEND_STANDBY:
444 * Ensure that clocks are in a valid state.
446 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
447 !at91_pm_verify_clocks())
450 at91_pm_suspend(state);
459 pr_debug("AT91: PM - bogus suspend state %d\n", state);
464 #ifdef CONFIG_PINCTRL_AT91
465 at91_pinctrl_gpio_resume();
471 * Called right prior to thawing processes.
473 static void at91_pm_end(void)
475 at91_pm_config_ws(soc_pm.data.mode, false);
479 static const struct platform_suspend_ops at91_pm_ops = {
480 .valid = at91_pm_valid_state,
481 .begin = at91_pm_begin,
482 .enter = at91_pm_enter,
486 static struct platform_device at91_cpuidle_device = {
487 .name = "cpuidle-at91",
491 * The AT91RM9200 goes into self-refresh mode with this command, and will
492 * terminate self-refresh automatically on the next SDRAM access.
494 * Self-refresh mode is exited as soon as a memory access is made, but we don't
495 * know for sure when that happens. However, we need to restore the low-power
496 * mode if it was enabled before going idle. Restoring low-power mode while
497 * still in self-refresh is "not recommended", but seems to work.
499 static void at91rm9200_standby(void)
504 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
505 " str %2, [%1, %3]\n\t"
506 " mcr p15, 0, %0, c7, c0, 4\n\t"
508 : "r" (0), "r" (soc_pm.data.ramc[0]),
509 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
512 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
515 static void at91_ddr_standby(void)
517 /* Those two values allow us to delay self-refresh activation
520 u32 mdr, saved_mdr0, saved_mdr1 = 0;
521 u32 saved_lpr0, saved_lpr1 = 0;
523 /* LPDDR1 --> force DDR2 mode during self-refresh */
524 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
525 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
526 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
527 mdr |= AT91_DDRSDRC_MD_DDR2;
528 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
531 if (soc_pm.data.ramc[1]) {
532 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
533 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
534 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
535 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
536 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
537 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
538 mdr |= AT91_DDRSDRC_MD_DDR2;
539 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
543 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
544 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
545 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
547 /* self-refresh mode now */
548 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
549 if (soc_pm.data.ramc[1])
550 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
554 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
555 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
556 if (soc_pm.data.ramc[1]) {
557 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
558 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
562 static void sama5d3_ddr_standby(void)
567 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
568 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
569 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
571 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
575 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
578 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
581 static void at91sam9_sdram_standby(void)
584 u32 saved_lpr0, saved_lpr1 = 0;
586 if (soc_pm.data.ramc[1]) {
587 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
588 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
589 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
592 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
593 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
594 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
596 /* self-refresh mode now */
597 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
598 if (soc_pm.data.ramc[1])
599 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
603 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
604 if (soc_pm.data.ramc[1])
605 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
610 unsigned int memctrl;
613 static const struct ramc_info ramc_infos[] __initconst = {
614 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
615 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
616 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
617 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
620 static const struct of_device_id ramc_ids[] __initconst = {
621 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
622 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
623 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
624 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
625 { .compatible = "microchip,sama7g5-uddrc", },
629 static const struct of_device_id ramc_phy_ids[] __initconst = {
630 { .compatible = "microchip,sama7g5-ddr3phy", },
634 static __init int at91_dt_ramc(bool phy_mandatory)
636 struct device_node *np;
637 const struct of_device_id *of_id;
639 void *standby = NULL;
640 const struct ramc_info *ramc;
643 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
644 soc_pm.data.ramc[idx] = of_iomap(np, 0);
645 if (!soc_pm.data.ramc[idx]) {
646 pr_err("unable to map ramc[%d] cpu registers\n", idx);
655 standby = ramc->idle;
656 soc_pm.data.memctrl = ramc->memctrl;
663 pr_err("unable to find compatible ram controller node in dtb\n");
668 /* Lookup for DDR PHY node, if any. */
669 for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {
670 soc_pm.data.ramc_phy = of_iomap(np, 0);
671 if (!soc_pm.data.ramc_phy) {
672 pr_err("unable to map ramc phy cpu registers\n");
679 if (phy_mandatory && !soc_pm.data.ramc_phy) {
680 pr_err("DDR PHY is mandatory!\n");
686 pr_warn("ramc no standby function available\n");
690 at91_cpuidle_device.dev.platform_data = standby;
696 iounmap(soc_pm.data.ramc[--idx]);
701 static void at91rm9200_idle(void)
704 * Disable the processor clock. The processor will be automatically
705 * re-enabled by an interrupt or by a reset.
707 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
710 static void at91sam9_idle(void)
712 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
716 static void __init at91_pm_sram_init(void)
718 struct gen_pool *sram_pool;
719 phys_addr_t sram_pbase;
720 unsigned long sram_base;
721 struct device_node *node;
722 struct platform_device *pdev = NULL;
724 for_each_compatible_node(node, NULL, "mmio-sram") {
725 pdev = of_find_device_by_node(node);
733 pr_warn("%s: failed to find sram device!\n", __func__);
737 sram_pool = gen_pool_get(&pdev->dev, NULL);
739 pr_warn("%s: sram pool unavailable!\n", __func__);
743 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
745 pr_warn("%s: unable to alloc sram!\n", __func__);
749 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
750 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
751 at91_pm_suspend_in_sram_sz, false);
752 if (!at91_suspend_sram_fn) {
753 pr_warn("SRAM: Could not map\n");
757 /* Copy the pm suspend handler to SRAM */
758 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
759 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
763 put_device(&pdev->dev);
767 static bool __init at91_is_pm_mode_active(int pm_mode)
769 return (soc_pm.data.standby_mode == pm_mode ||
770 soc_pm.data.suspend_mode == pm_mode);
773 static int __init at91_pm_backup_scan_memcs(unsigned long node,
774 const char *uname, int depth,
782 /* Memory node already located. */
786 type = of_get_flat_dt_prop(node, "device_type", NULL);
788 /* We are scanning "memory" nodes only. */
789 if (!type || strcmp(type, "memory"))
792 reg = of_get_flat_dt_prop(node, "reg", &size);
794 soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));
801 static int __init at91_pm_backup_init(void)
803 struct gen_pool *sram_pool;
804 struct device_node *np;
805 struct platform_device *pdev;
806 int ret = -ENODEV, located = 0;
808 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
809 !IS_ENABLED(CONFIG_SOC_SAMA7G5))
812 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
815 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
819 pdev = of_find_device_by_node(np);
822 pr_warn("%s: failed to find securam device!\n", __func__);
826 sram_pool = gen_pool_get(&pdev->dev, NULL);
828 pr_warn("%s: securam pool unavailable!\n", __func__);
832 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
834 pr_warn("%s: unable to alloc securam!\n", __func__);
839 soc_pm.bu->suspended = 0;
840 soc_pm.bu->canary = __pa_symbol(&canary);
841 soc_pm.bu->resume = __pa_symbol(cpu_resume);
842 if (soc_pm.data.ramc_phy) {
843 of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
848 soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy +
855 put_device(&pdev->dev);
859 static const struct of_device_id atmel_shdwc_ids[] = {
860 { .compatible = "atmel,sama5d2-shdwc" },
861 { .compatible = "microchip,sam9x60-shdwc" },
862 { .compatible = "microchip,sama7g5-shdwc" },
866 static void __init at91_pm_modes_init(const u32 *maps, int len)
868 struct device_node *np;
871 ret = at91_pm_backup_init();
873 if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
874 soc_pm.data.standby_mode = AT91_PM_ULP0;
875 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
876 soc_pm.data.suspend_mode = AT91_PM_ULP0;
879 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
880 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
881 np = of_find_matching_node(NULL, atmel_shdwc_ids);
883 pr_warn("%s: failed to find shdwc!\n", __func__);
885 /* Use ULP0 if it doesn't needs SHDWC.*/
886 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)))
889 mode = AT91_PM_STANDBY;
891 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC))
892 soc_pm.data.standby_mode = mode;
893 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))
894 soc_pm.data.suspend_mode = mode;
896 soc_pm.data.shdwc = of_iomap(np, 0);
901 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
902 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
903 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
905 pr_warn("%s: failed to find sfrbu!\n", __func__);
908 * Use ULP0 if it doesn't need SHDWC or if SHDWC
909 * was already located.
911 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) ||
915 mode = AT91_PM_STANDBY;
917 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU))
918 soc_pm.data.standby_mode = mode;
919 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))
920 soc_pm.data.suspend_mode = mode;
922 soc_pm.data.sfrbu = of_iomap(np, 0);
927 /* Unmap all unnecessary. */
928 if (soc_pm.data.shdwc &&
929 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
930 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
931 iounmap(soc_pm.data.shdwc);
932 soc_pm.data.shdwc = NULL;
935 if (soc_pm.data.sfrbu &&
936 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
937 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
938 iounmap(soc_pm.data.sfrbu);
939 soc_pm.data.sfrbu = NULL;
946 unsigned long uhp_udp_mask;
948 unsigned long version;
951 static const struct pmc_info pmc_infos[] __initconst = {
953 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
955 .version = AT91_PMC_V1,
959 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
961 .version = AT91_PMC_V1,
964 .uhp_udp_mask = AT91SAM926x_PMC_UHP,
966 .version = AT91_PMC_V1,
970 .version = AT91_PMC_V1,
973 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
975 .version = AT91_PMC_V2,
979 .version = AT91_PMC_V2,
984 static const struct of_device_id atmel_pmc_ids[] __initconst = {
985 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
986 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
987 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
988 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
989 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
990 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
991 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
992 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
993 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
994 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
995 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
996 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
997 { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
1001 static void __init at91_pm_modes_validate(const int *modes, int len)
1003 u8 i, standby = 0, suspend = 0;
1006 for (i = 0; i < len; i++) {
1007 if (standby && suspend)
1010 if (modes[i] == soc_pm.data.standby_mode && !standby) {
1015 if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
1022 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
1023 mode = AT91_PM_ULP0;
1025 mode = AT91_PM_STANDBY;
1027 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
1028 pm_modes[soc_pm.data.standby_mode].pattern,
1029 pm_modes[mode].pattern);
1030 soc_pm.data.standby_mode = mode;
1034 if (soc_pm.data.standby_mode == AT91_PM_ULP0)
1035 mode = AT91_PM_STANDBY;
1037 mode = AT91_PM_ULP0;
1039 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
1040 pm_modes[soc_pm.data.suspend_mode].pattern,
1041 pm_modes[mode].pattern);
1042 soc_pm.data.suspend_mode = mode;
1046 static void __init at91_pm_init(void (*pm_idle)(void))
1048 struct device_node *pmc_np;
1049 const struct of_device_id *of_id;
1050 const struct pmc_info *pmc;
1052 if (at91_cpuidle_device.dev.platform_data)
1053 platform_device_register(&at91_cpuidle_device);
1055 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
1056 soc_pm.data.pmc = of_iomap(pmc_np, 0);
1057 of_node_put(pmc_np);
1058 if (!soc_pm.data.pmc) {
1059 pr_err("AT91: PM not supported, PMC not found\n");
1064 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
1065 soc_pm.data.pmc_mckr_offset = pmc->mckr;
1066 soc_pm.data.pmc_version = pmc->version;
1069 arm_pm_idle = pm_idle;
1071 at91_pm_sram_init();
1073 if (at91_suspend_sram_fn) {
1074 suspend_set_ops(&at91_pm_ops);
1075 pr_info("AT91: PM: standby: %s, suspend: %s\n",
1076 pm_modes[soc_pm.data.standby_mode].pattern,
1077 pm_modes[soc_pm.data.suspend_mode].pattern);
1079 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
1083 void __init at91rm9200_pm_init(void)
1087 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
1091 * Force STANDBY and ULP0 mode to avoid calling
1092 * at91_pm_modes_validate() which may increase booting time.
1093 * Platform supports anyway only STANDBY and ULP0 modes.
1095 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1096 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1098 ret = at91_dt_ramc(false);
1103 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
1105 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
1107 at91_pm_init(at91rm9200_idle);
1110 void __init sam9x60_pm_init(void)
1112 static const int modes[] __initconst = {
1113 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1115 static const int iomaps[] __initconst = {
1116 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
1120 if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
1123 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1124 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1125 ret = at91_dt_ramc(false);
1131 soc_pm.ws_ids = sam9x60_ws_ids;
1132 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1135 void __init at91sam9_pm_init(void)
1139 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
1143 * Force STANDBY and ULP0 mode to avoid calling
1144 * at91_pm_modes_validate() which may increase booting time.
1145 * Platform supports anyway only STANDBY and ULP0 modes.
1147 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1148 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1150 ret = at91_dt_ramc(false);
1154 at91_pm_init(at91sam9_idle);
1157 void __init sama5_pm_init(void)
1159 static const int modes[] __initconst = {
1160 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
1164 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
1167 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1168 ret = at91_dt_ramc(false);
1175 void __init sama5d2_pm_init(void)
1177 static const int modes[] __initconst = {
1178 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1181 static const u32 iomaps[] __initconst = {
1182 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
1183 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) |
1184 AT91_PM_IOMAP(SFRBU),
1188 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
1191 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1192 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1193 ret = at91_dt_ramc(false);
1199 soc_pm.ws_ids = sama5d2_ws_ids;
1200 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
1201 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
1203 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1204 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1205 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1206 soc_pm.sfrbu_regs.pswbu.state = BIT(3);
1209 void __init sama7_pm_init(void)
1211 static const int modes[] __initconst = {
1212 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP1, AT91_PM_BACKUP,
1214 static const u32 iomaps[] __initconst = {
1215 [AT91_PM_ULP0] = AT91_PM_IOMAP(SFRBU),
1216 [AT91_PM_ULP1] = AT91_PM_IOMAP(SFRBU) |
1217 AT91_PM_IOMAP(SHDWC),
1218 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SFRBU) |
1219 AT91_PM_IOMAP(SHDWC),
1223 if (!IS_ENABLED(CONFIG_SOC_SAMA7))
1226 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1228 ret = at91_dt_ramc(true);
1232 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1235 soc_pm.ws_ids = sama7g5_ws_ids;
1236 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1238 soc_pm.sfrbu_regs.pswbu.key = (0x4BD20C << 8);
1239 soc_pm.sfrbu_regs.pswbu.ctrl = BIT(0);
1240 soc_pm.sfrbu_regs.pswbu.softsw = BIT(1);
1241 soc_pm.sfrbu_regs.pswbu.state = BIT(2);
1244 static int __init at91_pm_modes_select(char *str)
1247 substring_t args[MAX_OPT_ARGS];
1248 int standby, suspend;
1253 s = strsep(&str, ",");
1254 standby = match_token(s, pm_modes, args);
1258 suspend = match_token(str, pm_modes, args);
1262 soc_pm.data.standby_mode = standby;
1263 soc_pm.data.suspend_mode = suspend;
1267 early_param("atmel.pm_modes", at91_pm_modes_select);