1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
6 * Copyright (C) 2005 David Brownell
9 #include <linux/genalloc.h>
11 #include <linux/of_address.h>
13 #include <linux/of_fdt.h>
14 #include <linux/of_platform.h>
15 #include <linux/parser.h>
16 #include <linux/suspend.h>
18 #include <linux/clk/at91_pmc.h>
19 #include <linux/platform_data/atmel.h>
21 #include <soc/at91/pm.h>
23 #include <asm/cacheflush.h>
24 #include <asm/fncpy.h>
25 #include <asm/system_misc.h>
26 #include <asm/suspend.h>
31 #define BACKUP_DDR_PHY_CALIBRATION (9)
34 * struct at91_pm_bu - AT91 power management backup unit data structure
35 * @suspended: true if suspended to backup mode
37 * @canary: canary data for memory checking after exit from backup mode
39 * @ddr_phy_calibration: DDR PHY calibration data: ZQ0CR0, first 8 words
44 unsigned long reserved;
47 unsigned long ddr_phy_calibration[BACKUP_DDR_PHY_CALIBRATION];
51 * struct at91_soc_pm - AT91 SoC power management data structure
52 * @config_shdwc_ws: wakeup sources configuration function for SHDWC
53 * @config_pmc_ws: wakeup srouces configuration function for PMC
54 * @ws_ids: wakup sources of_device_id array
55 * @data: PM data to be used on last phase of suspend
56 * @bu: backup unit mapped data (for backup mode)
57 * @memcs: memory chip select
60 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
61 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
62 const struct of_device_id *ws_ids;
63 struct at91_pm_bu *bu;
64 struct at91_pm_data data;
69 * enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes
70 * @AT91_PM_IOMAP_SHDWC: SHDWC controller
71 * @AT91_PM_IOMAP_SFRBU: SFRBU controller
78 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name)
80 static struct at91_soc_pm soc_pm = {
82 .standby_mode = AT91_PM_STANDBY,
83 .suspend_mode = AT91_PM_ULP0,
87 static const match_table_t pm_modes __initconst = {
88 { AT91_PM_STANDBY, "standby" },
89 { AT91_PM_ULP0, "ulp0" },
90 { AT91_PM_ULP0_FAST, "ulp0-fast" },
91 { AT91_PM_ULP1, "ulp1" },
92 { AT91_PM_BACKUP, "backup" },
96 #define at91_ramc_read(id, field) \
97 __raw_readl(soc_pm.data.ramc[id] + field)
99 #define at91_ramc_write(id, field, value) \
100 __raw_writel(value, soc_pm.data.ramc[id] + field)
102 static int at91_pm_valid_state(suspend_state_t state)
106 case PM_SUSPEND_STANDBY:
115 static int canary = 0xA5A5A5A5;
117 struct wakeup_source_info {
118 unsigned int pmc_fsmr_bit;
119 unsigned int shdwc_mr_bit;
123 static const struct wakeup_source_info ws_info[] = {
124 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
125 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
126 { .pmc_fsmr_bit = AT91_PMC_USBAL },
127 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
128 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
129 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
132 static const struct of_device_id sama5d2_ws_ids[] = {
133 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
134 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
135 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
136 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
137 { .compatible = "usb-ohci", .data = &ws_info[2] },
138 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
139 { .compatible = "usb-ehci", .data = &ws_info[2] },
140 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
144 static const struct of_device_id sam9x60_ws_ids[] = {
145 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
146 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
147 { .compatible = "usb-ohci", .data = &ws_info[2] },
148 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
149 { .compatible = "usb-ehci", .data = &ws_info[2] },
150 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
151 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
155 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
157 const struct wakeup_source_info *wsi;
158 const struct of_device_id *match;
159 struct platform_device *pdev;
160 struct device_node *np;
161 unsigned int mode = 0, polarity = 0, val = 0;
163 if (pm_mode != AT91_PM_ULP1)
166 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
170 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
174 if (soc_pm.config_shdwc_ws)
175 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
178 val = readl(soc_pm.data.shdwc + 0x04);
180 /* Loop through defined wakeup sources. */
181 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
182 pdev = of_find_device_by_node(np);
186 if (device_may_wakeup(&pdev->dev)) {
189 /* Check if enabled on SHDWC. */
190 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
193 mode |= wsi->pmc_fsmr_bit;
194 if (wsi->set_polarity)
195 polarity |= wsi->pmc_fsmr_bit;
199 put_device(&pdev->dev);
203 if (soc_pm.config_pmc_ws)
204 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
206 pr_err("AT91: PM: no ULP1 wakeup sources found!");
209 return mode ? 0 : -EPERM;
212 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
218 val = readl(shdwc + 0x0c);
219 *mode |= (val & 0x3ff);
220 *polarity |= ((val >> 16) & 0x3ff);
225 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
227 writel(mode, pmc + AT91_PMC_FSMR);
228 writel(polarity, pmc + AT91_PMC_FSPR);
233 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
235 writel(mode, pmc + AT91_PMC_FSMR);
241 * Called after processes are frozen, but before we shutdown devices.
243 static int at91_pm_begin(suspend_state_t state)
249 soc_pm.data.mode = soc_pm.data.suspend_mode;
252 case PM_SUSPEND_STANDBY:
253 soc_pm.data.mode = soc_pm.data.standby_mode;
257 soc_pm.data.mode = -1;
260 ret = at91_pm_config_ws(soc_pm.data.mode, true);
264 if (soc_pm.data.mode == AT91_PM_BACKUP)
265 soc_pm.bu->suspended = 1;
267 soc_pm.bu->suspended = 0;
273 * Verify that all the clocks are correct before entering
276 static int at91_pm_verify_clocks(void)
281 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
283 /* USB must not be using PLLB */
284 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
285 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
289 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
290 for (i = 0; i < 4; i++) {
293 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
295 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
296 if (css != AT91_PMC_CSS_SLOW) {
297 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
306 * Call this from platform driver suspend() to see how deeply to suspend.
307 * For example, some controllers (like OHCI) need one of the PLL clocks
308 * in order to act as a wakeup source, and those are not available when
309 * going into slow clock mode.
311 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
312 * the very same problem (but not using at91 main_clk), and it'd be better
313 * to add one generic API rather than lots of platform-specific ones.
315 int at91_suspend_entering_slow_clock(void)
317 return (soc_pm.data.mode >= AT91_PM_ULP0);
319 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
321 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
322 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
323 extern u32 at91_pm_suspend_in_sram_sz;
325 static int at91_suspend_finish(unsigned long val)
329 if (soc_pm.data.mode == AT91_PM_BACKUP && soc_pm.data.ramc_phy) {
331 * The 1st 8 words of memory might get corrupted in the process
332 * of DDR PHY recalibration; it is saved here in securam and it
333 * will be restored later, after recalibration, by bootloader
335 for (i = 1; i < BACKUP_DDR_PHY_CALIBRATION; i++)
336 soc_pm.bu->ddr_phy_calibration[i] =
337 *((unsigned int *)soc_pm.memcs + (i - 1));
343 at91_suspend_sram_fn(&soc_pm.data);
348 static void at91_pm_suspend(suspend_state_t state)
350 if (soc_pm.data.mode == AT91_PM_BACKUP) {
351 cpu_suspend(0, at91_suspend_finish);
353 /* The SRAM is lost between suspend cycles */
354 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
355 &at91_pm_suspend_in_sram,
356 at91_pm_suspend_in_sram_sz);
358 at91_suspend_finish(0);
365 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
366 * event sources; and reduces DRAM power. But otherwise it's identical to
367 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
369 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
370 * suspend more deeply, the master clock switches to the clk32k and turns off
371 * the main oscillator
373 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
375 static int at91_pm_enter(suspend_state_t state)
377 #ifdef CONFIG_PINCTRL_AT91
379 * FIXME: this is needed to communicate between the pinctrl driver and
380 * the PM implementation in the machine. Possibly part of the PM
381 * implementation should be moved down into the pinctrl driver and get
382 * called as part of the generic suspend/resume path.
384 at91_pinctrl_gpio_suspend();
389 case PM_SUSPEND_STANDBY:
391 * Ensure that clocks are in a valid state.
393 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
394 !at91_pm_verify_clocks())
397 at91_pm_suspend(state);
406 pr_debug("AT91: PM - bogus suspend state %d\n", state);
411 #ifdef CONFIG_PINCTRL_AT91
412 at91_pinctrl_gpio_resume();
418 * Called right prior to thawing processes.
420 static void at91_pm_end(void)
422 at91_pm_config_ws(soc_pm.data.mode, false);
426 static const struct platform_suspend_ops at91_pm_ops = {
427 .valid = at91_pm_valid_state,
428 .begin = at91_pm_begin,
429 .enter = at91_pm_enter,
433 static struct platform_device at91_cpuidle_device = {
434 .name = "cpuidle-at91",
438 * The AT91RM9200 goes into self-refresh mode with this command, and will
439 * terminate self-refresh automatically on the next SDRAM access.
441 * Self-refresh mode is exited as soon as a memory access is made, but we don't
442 * know for sure when that happens. However, we need to restore the low-power
443 * mode if it was enabled before going idle. Restoring low-power mode while
444 * still in self-refresh is "not recommended", but seems to work.
446 static void at91rm9200_standby(void)
451 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
452 " str %2, [%1, %3]\n\t"
453 " mcr p15, 0, %0, c7, c0, 4\n\t"
455 : "r" (0), "r" (soc_pm.data.ramc[0]),
456 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
459 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
462 static void at91_ddr_standby(void)
464 /* Those two values allow us to delay self-refresh activation
467 u32 mdr, saved_mdr0, saved_mdr1 = 0;
468 u32 saved_lpr0, saved_lpr1 = 0;
470 /* LPDDR1 --> force DDR2 mode during self-refresh */
471 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
472 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
473 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
474 mdr |= AT91_DDRSDRC_MD_DDR2;
475 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
478 if (soc_pm.data.ramc[1]) {
479 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
480 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
481 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
482 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
483 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
484 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
485 mdr |= AT91_DDRSDRC_MD_DDR2;
486 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
490 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
491 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
492 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
494 /* self-refresh mode now */
495 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
496 if (soc_pm.data.ramc[1])
497 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
501 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
502 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
503 if (soc_pm.data.ramc[1]) {
504 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
505 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
509 static void sama5d3_ddr_standby(void)
514 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
515 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
516 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
518 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
522 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
525 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
528 static void at91sam9_sdram_standby(void)
531 u32 saved_lpr0, saved_lpr1 = 0;
533 if (soc_pm.data.ramc[1]) {
534 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
535 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
536 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
539 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
540 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
541 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
543 /* self-refresh mode now */
544 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
545 if (soc_pm.data.ramc[1])
546 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
550 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
551 if (soc_pm.data.ramc[1])
552 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
557 unsigned int memctrl;
560 static const struct ramc_info ramc_infos[] __initconst = {
561 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
562 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
563 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
564 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
567 static const struct of_device_id ramc_ids[] __initconst = {
568 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
569 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
570 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
571 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
572 { .compatible = "microchip,sama7g5-uddrc", },
576 static const struct of_device_id ramc_phy_ids[] __initconst = {
577 { .compatible = "microchip,sama7g5-ddr3phy", },
581 static __init void at91_dt_ramc(bool phy_mandatory)
583 struct device_node *np;
584 const struct of_device_id *of_id;
586 void *standby = NULL;
587 const struct ramc_info *ramc;
589 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
590 soc_pm.data.ramc[idx] = of_iomap(np, 0);
591 if (!soc_pm.data.ramc[idx])
592 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
597 standby = ramc->idle;
598 soc_pm.data.memctrl = ramc->memctrl;
605 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
607 /* Lookup for DDR PHY node, if any. */
608 for_each_matching_node_and_match(np, ramc_phy_ids, &of_id) {
609 soc_pm.data.ramc_phy = of_iomap(np, 0);
610 if (!soc_pm.data.ramc_phy)
611 panic(pr_fmt("unable to map ramc phy cpu registers\n"));
614 if (phy_mandatory && !soc_pm.data.ramc_phy)
615 panic(pr_fmt("DDR PHY is mandatory!\n"));
618 pr_warn("ramc no standby function available\n");
622 at91_cpuidle_device.dev.platform_data = standby;
625 static void at91rm9200_idle(void)
628 * Disable the processor clock. The processor will be automatically
629 * re-enabled by an interrupt or by a reset.
631 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
634 static void at91sam9_idle(void)
636 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
640 static void __init at91_pm_sram_init(void)
642 struct gen_pool *sram_pool;
643 phys_addr_t sram_pbase;
644 unsigned long sram_base;
645 struct device_node *node;
646 struct platform_device *pdev = NULL;
648 for_each_compatible_node(node, NULL, "mmio-sram") {
649 pdev = of_find_device_by_node(node);
657 pr_warn("%s: failed to find sram device!\n", __func__);
661 sram_pool = gen_pool_get(&pdev->dev, NULL);
663 pr_warn("%s: sram pool unavailable!\n", __func__);
667 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
669 pr_warn("%s: unable to alloc sram!\n", __func__);
673 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
674 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
675 at91_pm_suspend_in_sram_sz, false);
676 if (!at91_suspend_sram_fn) {
677 pr_warn("SRAM: Could not map\n");
681 /* Copy the pm suspend handler to SRAM */
682 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
683 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
687 put_device(&pdev->dev);
691 static bool __init at91_is_pm_mode_active(int pm_mode)
693 return (soc_pm.data.standby_mode == pm_mode ||
694 soc_pm.data.suspend_mode == pm_mode);
697 static int __init at91_pm_backup_scan_memcs(unsigned long node,
698 const char *uname, int depth,
706 /* Memory node already located. */
710 type = of_get_flat_dt_prop(node, "device_type", NULL);
712 /* We are scanning "memory" nodes only. */
713 if (!type || strcmp(type, "memory"))
716 reg = of_get_flat_dt_prop(node, "reg", &size);
718 soc_pm.memcs = __va((phys_addr_t)be32_to_cpu(*reg));
725 static int __init at91_pm_backup_init(void)
727 struct gen_pool *sram_pool;
728 struct device_node *np;
729 struct platform_device *pdev;
730 int ret = -ENODEV, located = 0;
732 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2) &&
733 !IS_ENABLED(CONFIG_SOC_SAMA7G5))
736 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
739 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
743 pdev = of_find_device_by_node(np);
746 pr_warn("%s: failed to find securam device!\n", __func__);
750 sram_pool = gen_pool_get(&pdev->dev, NULL);
752 pr_warn("%s: securam pool unavailable!\n", __func__);
756 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
758 pr_warn("%s: unable to alloc securam!\n", __func__);
763 soc_pm.bu->suspended = 0;
764 soc_pm.bu->canary = __pa_symbol(&canary);
765 soc_pm.bu->resume = __pa_symbol(cpu_resume);
766 if (soc_pm.data.ramc_phy) {
767 of_scan_flat_dt(at91_pm_backup_scan_memcs, &located);
772 soc_pm.bu->ddr_phy_calibration[0] = readl(soc_pm.data.ramc_phy +
779 put_device(&pdev->dev);
783 static const struct of_device_id atmel_shdwc_ids[] = {
784 { .compatible = "atmel,sama5d2-shdwc" },
785 { .compatible = "microchip,sam9x60-shdwc" },
789 static void __init at91_pm_modes_init(const u32 *maps, int len)
791 struct device_node *np;
794 ret = at91_pm_backup_init();
796 if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
797 soc_pm.data.standby_mode = AT91_PM_ULP0;
798 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
799 soc_pm.data.suspend_mode = AT91_PM_ULP0;
802 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
803 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
804 np = of_find_matching_node(NULL, atmel_shdwc_ids);
806 pr_warn("%s: failed to find shdwc!\n", __func__);
808 /* Use ULP0 if it doesn't needs SHDWC.*/
809 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)))
812 mode = AT91_PM_STANDBY;
814 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC))
815 soc_pm.data.standby_mode = mode;
816 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))
817 soc_pm.data.suspend_mode = mode;
819 soc_pm.data.shdwc = of_iomap(np, 0);
824 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
825 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
826 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
828 pr_warn("%s: failed to find sfrbu!\n", __func__);
831 * Use ULP0 if it doesn't need SHDWC or if SHDWC
832 * was already located.
834 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) ||
838 mode = AT91_PM_STANDBY;
840 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU))
841 soc_pm.data.standby_mode = mode;
842 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))
843 soc_pm.data.suspend_mode = mode;
845 soc_pm.data.sfrbu = of_iomap(np, 0);
850 /* Unmap all unnecessary. */
851 if (soc_pm.data.shdwc &&
852 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
853 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
854 iounmap(soc_pm.data.shdwc);
855 soc_pm.data.shdwc = NULL;
858 if (soc_pm.data.sfrbu &&
859 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
860 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
861 iounmap(soc_pm.data.sfrbu);
862 soc_pm.data.sfrbu = NULL;
869 unsigned long uhp_udp_mask;
871 unsigned long version;
874 static const struct pmc_info pmc_infos[] __initconst = {
876 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
878 .version = AT91_PMC_V1,
882 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
884 .version = AT91_PMC_V1,
887 .uhp_udp_mask = AT91SAM926x_PMC_UHP,
889 .version = AT91_PMC_V1,
893 .version = AT91_PMC_V1,
896 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
898 .version = AT91_PMC_V2,
902 .version = AT91_PMC_V2,
907 static const struct of_device_id atmel_pmc_ids[] __initconst = {
908 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
909 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
910 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
911 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
912 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
913 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
914 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
915 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
916 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
917 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
918 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
919 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
920 { .compatible = "microchip,sama7g5-pmc", .data = &pmc_infos[5] },
924 static void __init at91_pm_modes_validate(const int *modes, int len)
926 u8 i, standby = 0, suspend = 0;
929 for (i = 0; i < len; i++) {
930 if (standby && suspend)
933 if (modes[i] == soc_pm.data.standby_mode && !standby) {
938 if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
945 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
948 mode = AT91_PM_STANDBY;
950 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
951 pm_modes[soc_pm.data.standby_mode].pattern,
952 pm_modes[mode].pattern);
953 soc_pm.data.standby_mode = mode;
957 if (soc_pm.data.standby_mode == AT91_PM_ULP0)
958 mode = AT91_PM_STANDBY;
962 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
963 pm_modes[soc_pm.data.suspend_mode].pattern,
964 pm_modes[mode].pattern);
965 soc_pm.data.suspend_mode = mode;
969 static void __init at91_pm_init(void (*pm_idle)(void))
971 struct device_node *pmc_np;
972 const struct of_device_id *of_id;
973 const struct pmc_info *pmc;
975 if (at91_cpuidle_device.dev.platform_data)
976 platform_device_register(&at91_cpuidle_device);
978 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
979 soc_pm.data.pmc = of_iomap(pmc_np, 0);
981 if (!soc_pm.data.pmc) {
982 pr_err("AT91: PM not supported, PMC not found\n");
987 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
988 soc_pm.data.pmc_mckr_offset = pmc->mckr;
989 soc_pm.data.pmc_version = pmc->version;
992 arm_pm_idle = pm_idle;
996 if (at91_suspend_sram_fn) {
997 suspend_set_ops(&at91_pm_ops);
998 pr_info("AT91: PM: standby: %s, suspend: %s\n",
999 pm_modes[soc_pm.data.standby_mode].pattern,
1000 pm_modes[soc_pm.data.suspend_mode].pattern);
1002 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
1006 void __init at91rm9200_pm_init(void)
1008 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
1012 * Force STANDBY and ULP0 mode to avoid calling
1013 * at91_pm_modes_validate() which may increase booting time.
1014 * Platform supports anyway only STANDBY and ULP0 modes.
1016 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1017 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1019 at91_dt_ramc(false);
1022 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
1024 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
1026 at91_pm_init(at91rm9200_idle);
1029 void __init sam9x60_pm_init(void)
1031 static const int modes[] __initconst = {
1032 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1034 static const int iomaps[] __initconst = {
1035 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
1038 if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
1041 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1042 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1043 at91_dt_ramc(false);
1046 soc_pm.ws_ids = sam9x60_ws_ids;
1047 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
1050 void __init at91sam9_pm_init(void)
1052 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
1056 * Force STANDBY and ULP0 mode to avoid calling
1057 * at91_pm_modes_validate() which may increase booting time.
1058 * Platform supports anyway only STANDBY and ULP0 modes.
1060 soc_pm.data.standby_mode = AT91_PM_STANDBY;
1061 soc_pm.data.suspend_mode = AT91_PM_ULP0;
1063 at91_dt_ramc(false);
1064 at91_pm_init(at91sam9_idle);
1067 void __init sama5_pm_init(void)
1069 static const int modes[] __initconst = {
1070 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
1073 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
1076 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1077 at91_dt_ramc(false);
1081 void __init sama5d2_pm_init(void)
1083 static const int modes[] __initconst = {
1084 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1087 static const u32 iomaps[] __initconst = {
1088 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
1089 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) |
1090 AT91_PM_IOMAP(SFRBU),
1093 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
1096 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1097 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1098 at91_dt_ramc(false);
1101 soc_pm.ws_ids = sama5d2_ws_ids;
1102 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
1103 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
1106 static int __init at91_pm_modes_select(char *str)
1109 substring_t args[MAX_OPT_ARGS];
1110 int standby, suspend;
1115 s = strsep(&str, ",");
1116 standby = match_token(s, pm_modes, args);
1120 suspend = match_token(str, pm_modes, args);
1124 soc_pm.data.standby_mode = standby;
1125 soc_pm.data.suspend_mode = suspend;
1129 early_param("atmel.pm_modes", at91_pm_modes_select);