2 * arch/arm/mach-at91/pm.c
3 * AT91 Power Management
5 * Copyright (C) 2005 David Brownell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/genalloc.h>
15 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/parser.h>
19 #include <linux/suspend.h>
21 #include <linux/clk/at91_pmc.h>
23 #include <asm/cacheflush.h>
24 #include <asm/fncpy.h>
25 #include <asm/system_misc.h>
26 #include <asm/suspend.h>
32 * FIXME: this is needed to communicate between the pinctrl driver and
33 * the PM implementation in the machine. Possibly part of the PM
34 * implementation should be moved down into the pinctrl driver and get
35 * called as part of the generic suspend/resume path.
37 #ifdef CONFIG_PINCTRL_AT91
38 extern void at91_pinctrl_gpio_suspend(void);
39 extern void at91_pinctrl_gpio_resume(void);
43 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
44 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
45 const struct of_device_id *ws_ids;
46 struct at91_pm_data data;
49 static struct at91_soc_pm soc_pm = {
51 .standby_mode = AT91_PM_STANDBY,
52 .suspend_mode = AT91_PM_ULP0,
56 static const match_table_t pm_modes __initconst = {
57 { AT91_PM_STANDBY, "standby" },
58 { AT91_PM_ULP0, "ulp0" },
59 { AT91_PM_ULP1, "ulp1" },
60 { AT91_PM_BACKUP, "backup" },
64 #define at91_ramc_read(id, field) \
65 __raw_readl(soc_pm.data.ramc[id] + field)
67 #define at91_ramc_write(id, field, value) \
68 __raw_writel(value, soc_pm.data.ramc[id] + field)
70 static int at91_pm_valid_state(suspend_state_t state)
74 case PM_SUSPEND_STANDBY:
83 static int canary = 0xA5A5A5A5;
85 static struct at91_pm_bu {
87 unsigned long reserved;
92 struct wakeup_source_info {
93 unsigned int pmc_fsmr_bit;
94 unsigned int shdwc_mr_bit;
98 static const struct wakeup_source_info ws_info[] = {
99 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
100 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
101 { .pmc_fsmr_bit = AT91_PMC_USBAL },
102 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
103 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
104 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
107 static const struct of_device_id sama5d2_ws_ids[] = {
108 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
109 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
110 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
111 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
112 { .compatible = "usb-ohci", .data = &ws_info[2] },
113 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
114 { .compatible = "usb-ehci", .data = &ws_info[2] },
115 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
119 static const struct of_device_id sam9x60_ws_ids[] = {
120 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
121 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
122 { .compatible = "usb-ohci", .data = &ws_info[2] },
123 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
124 { .compatible = "usb-ehci", .data = &ws_info[2] },
125 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
126 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
130 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
132 const struct wakeup_source_info *wsi;
133 const struct of_device_id *match;
134 struct platform_device *pdev;
135 struct device_node *np;
136 unsigned int mode = 0, polarity = 0, val = 0;
138 if (pm_mode != AT91_PM_ULP1)
141 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
145 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
149 if (soc_pm.config_shdwc_ws)
150 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
153 val = readl(soc_pm.data.shdwc + 0x04);
155 /* Loop through defined wakeup sources. */
156 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
157 pdev = of_find_device_by_node(np);
161 if (device_may_wakeup(&pdev->dev)) {
164 /* Check if enabled on SHDWC. */
165 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
168 mode |= wsi->pmc_fsmr_bit;
169 if (wsi->set_polarity)
170 polarity |= wsi->pmc_fsmr_bit;
174 put_device(&pdev->dev);
178 if (soc_pm.config_pmc_ws)
179 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
181 pr_err("AT91: PM: no ULP1 wakeup sources found!");
184 return mode ? 0 : -EPERM;
187 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
193 val = readl(shdwc + 0x0c);
194 *mode |= (val & 0x3ff);
195 *polarity |= ((val >> 16) & 0x3ff);
200 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
202 writel(mode, pmc + AT91_PMC_FSMR);
203 writel(polarity, pmc + AT91_PMC_FSPR);
208 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
210 writel(mode, pmc + AT91_PMC_FSMR);
216 * Called after processes are frozen, but before we shutdown devices.
218 static int at91_pm_begin(suspend_state_t state)
222 soc_pm.data.mode = soc_pm.data.suspend_mode;
225 case PM_SUSPEND_STANDBY:
226 soc_pm.data.mode = soc_pm.data.standby_mode;
230 soc_pm.data.mode = -1;
233 return at91_pm_config_ws(soc_pm.data.mode, true);
237 * Verify that all the clocks are correct before entering
240 static int at91_pm_verify_clocks(void)
245 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
247 /* USB must not be using PLLB */
248 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
249 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
253 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
254 for (i = 0; i < 4; i++) {
257 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
259 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
260 if (css != AT91_PMC_CSS_SLOW) {
261 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
270 * Call this from platform driver suspend() to see how deeply to suspend.
271 * For example, some controllers (like OHCI) need one of the PLL clocks
272 * in order to act as a wakeup source, and those are not available when
273 * going into slow clock mode.
275 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
276 * the very same problem (but not using at91 main_clk), and it'd be better
277 * to add one generic API rather than lots of platform-specific ones.
279 int at91_suspend_entering_slow_clock(void)
281 return (soc_pm.data.mode >= AT91_PM_ULP0);
283 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
285 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
286 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
287 extern u32 at91_pm_suspend_in_sram_sz;
289 static int at91_suspend_finish(unsigned long val)
294 at91_suspend_sram_fn(&soc_pm.data);
299 static void at91_pm_suspend(suspend_state_t state)
301 if (soc_pm.data.mode == AT91_PM_BACKUP) {
302 pm_bu->suspended = 1;
304 cpu_suspend(0, at91_suspend_finish);
306 /* The SRAM is lost between suspend cycles */
307 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
308 &at91_pm_suspend_in_sram,
309 at91_pm_suspend_in_sram_sz);
311 at91_suspend_finish(0);
318 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
319 * event sources; and reduces DRAM power. But otherwise it's identical to
320 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
322 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
323 * suspend more deeply, the master clock switches to the clk32k and turns off
324 * the main oscillator
326 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
328 static int at91_pm_enter(suspend_state_t state)
330 #ifdef CONFIG_PINCTRL_AT91
331 at91_pinctrl_gpio_suspend();
336 case PM_SUSPEND_STANDBY:
338 * Ensure that clocks are in a valid state.
340 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
341 !at91_pm_verify_clocks())
344 at91_pm_suspend(state);
353 pr_debug("AT91: PM - bogus suspend state %d\n", state);
358 #ifdef CONFIG_PINCTRL_AT91
359 at91_pinctrl_gpio_resume();
365 * Called right prior to thawing processes.
367 static void at91_pm_end(void)
369 at91_pm_config_ws(soc_pm.data.mode, false);
373 static const struct platform_suspend_ops at91_pm_ops = {
374 .valid = at91_pm_valid_state,
375 .begin = at91_pm_begin,
376 .enter = at91_pm_enter,
380 static struct platform_device at91_cpuidle_device = {
381 .name = "cpuidle-at91",
385 * The AT91RM9200 goes into self-refresh mode with this command, and will
386 * terminate self-refresh automatically on the next SDRAM access.
388 * Self-refresh mode is exited as soon as a memory access is made, but we don't
389 * know for sure when that happens. However, we need to restore the low-power
390 * mode if it was enabled before going idle. Restoring low-power mode while
391 * still in self-refresh is "not recommended", but seems to work.
393 static void at91rm9200_standby(void)
398 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
399 " str %2, [%1, %3]\n\t"
400 " mcr p15, 0, %0, c7, c0, 4\n\t"
402 : "r" (0), "r" (soc_pm.data.ramc[0]),
403 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
406 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
409 static void at91_ddr_standby(void)
411 /* Those two values allow us to delay self-refresh activation
414 u32 mdr, saved_mdr0, saved_mdr1 = 0;
415 u32 saved_lpr0, saved_lpr1 = 0;
417 /* LPDDR1 --> force DDR2 mode during self-refresh */
418 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
419 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
420 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
421 mdr |= AT91_DDRSDRC_MD_DDR2;
422 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
425 if (soc_pm.data.ramc[1]) {
426 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
427 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
428 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
429 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
430 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
431 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
432 mdr |= AT91_DDRSDRC_MD_DDR2;
433 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
437 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
438 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
439 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
441 /* self-refresh mode now */
442 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
443 if (soc_pm.data.ramc[1])
444 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
448 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
449 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
450 if (soc_pm.data.ramc[1]) {
451 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
452 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
456 static void sama5d3_ddr_standby(void)
461 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
462 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
463 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
465 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
469 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
472 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
475 static void at91sam9_sdram_standby(void)
478 u32 saved_lpr0, saved_lpr1 = 0;
480 if (soc_pm.data.ramc[1]) {
481 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
482 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
483 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
486 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
487 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
488 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
490 /* self-refresh mode now */
491 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
492 if (soc_pm.data.ramc[1])
493 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
497 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
498 if (soc_pm.data.ramc[1])
499 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
504 unsigned int memctrl;
507 static const struct ramc_info ramc_infos[] __initconst = {
508 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
509 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
510 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
511 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
514 static const struct of_device_id ramc_ids[] __initconst = {
515 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
516 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
517 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
518 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
522 static __init void at91_dt_ramc(void)
524 struct device_node *np;
525 const struct of_device_id *of_id;
527 void *standby = NULL;
528 const struct ramc_info *ramc;
530 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
531 soc_pm.data.ramc[idx] = of_iomap(np, 0);
532 if (!soc_pm.data.ramc[idx])
533 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
537 standby = ramc->idle;
538 soc_pm.data.memctrl = ramc->memctrl;
544 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
547 pr_warn("ramc no standby function available\n");
551 at91_cpuidle_device.dev.platform_data = standby;
554 static void at91rm9200_idle(void)
557 * Disable the processor clock. The processor will be automatically
558 * re-enabled by an interrupt or by a reset.
560 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
563 static void at91sam9x60_idle(void)
568 static void at91sam9_idle(void)
570 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
574 static void __init at91_pm_sram_init(void)
576 struct gen_pool *sram_pool;
577 phys_addr_t sram_pbase;
578 unsigned long sram_base;
579 struct device_node *node;
580 struct platform_device *pdev = NULL;
582 for_each_compatible_node(node, NULL, "mmio-sram") {
583 pdev = of_find_device_by_node(node);
591 pr_warn("%s: failed to find sram device!\n", __func__);
595 sram_pool = gen_pool_get(&pdev->dev, NULL);
597 pr_warn("%s: sram pool unavailable!\n", __func__);
601 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
603 pr_warn("%s: unable to alloc sram!\n", __func__);
607 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
608 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
609 at91_pm_suspend_in_sram_sz, false);
610 if (!at91_suspend_sram_fn) {
611 pr_warn("SRAM: Could not map\n");
615 /* Copy the pm suspend handler to SRAM */
616 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
617 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
620 static bool __init at91_is_pm_mode_active(int pm_mode)
622 return (soc_pm.data.standby_mode == pm_mode ||
623 soc_pm.data.suspend_mode == pm_mode);
626 static int __init at91_pm_backup_init(void)
628 struct gen_pool *sram_pool;
629 struct device_node *np;
630 struct platform_device *pdev = NULL;
633 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
636 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
639 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
641 pr_warn("%s: failed to find sfrbu!\n", __func__);
645 soc_pm.data.sfrbu = of_iomap(np, 0);
648 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
650 goto securam_fail_no_ref_dev;
652 pdev = of_find_device_by_node(np);
655 pr_warn("%s: failed to find securam device!\n", __func__);
656 goto securam_fail_no_ref_dev;
659 sram_pool = gen_pool_get(&pdev->dev, NULL);
661 pr_warn("%s: securam pool unavailable!\n", __func__);
665 pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
667 pr_warn("%s: unable to alloc securam!\n", __func__);
672 pm_bu->suspended = 0;
673 pm_bu->canary = __pa_symbol(&canary);
674 pm_bu->resume = __pa_symbol(cpu_resume);
679 put_device(&pdev->dev);
680 securam_fail_no_ref_dev:
681 iounmap(soc_pm.data.sfrbu);
682 soc_pm.data.sfrbu = NULL;
686 static void __init at91_pm_use_default_mode(int pm_mode)
688 if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
691 if (soc_pm.data.standby_mode == pm_mode)
692 soc_pm.data.standby_mode = AT91_PM_ULP0;
693 if (soc_pm.data.suspend_mode == pm_mode)
694 soc_pm.data.suspend_mode = AT91_PM_ULP0;
697 static void __init at91_pm_modes_init(void)
699 struct device_node *np;
702 if (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&
703 !at91_is_pm_mode_active(AT91_PM_ULP1))
706 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc");
708 pr_warn("%s: failed to find shdwc!\n", __func__);
712 soc_pm.data.shdwc = of_iomap(np, 0);
715 ret = at91_pm_backup_init();
717 if (!at91_is_pm_mode_active(AT91_PM_ULP1))
726 iounmap(soc_pm.data.shdwc);
727 soc_pm.data.shdwc = NULL;
729 at91_pm_use_default_mode(AT91_PM_ULP1);
731 at91_pm_use_default_mode(AT91_PM_BACKUP);
735 unsigned long uhp_udp_mask;
738 static const struct pmc_info pmc_infos[] __initconst = {
739 { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP },
740 { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP },
741 { .uhp_udp_mask = AT91SAM926x_PMC_UHP },
742 { .uhp_udp_mask = 0 },
745 static const struct of_device_id atmel_pmc_ids[] __initconst = {
746 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
747 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
748 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
749 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
750 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
751 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
752 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
753 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
754 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
755 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
756 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
760 static void __init at91_pm_init(void (*pm_idle)(void))
762 struct device_node *pmc_np;
763 const struct of_device_id *of_id;
764 const struct pmc_info *pmc;
766 if (at91_cpuidle_device.dev.platform_data)
767 platform_device_register(&at91_cpuidle_device);
769 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
770 soc_pm.data.pmc = of_iomap(pmc_np, 0);
771 if (!soc_pm.data.pmc) {
772 pr_err("AT91: PM not supported, PMC not found\n");
777 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
780 arm_pm_idle = pm_idle;
784 if (at91_suspend_sram_fn) {
785 suspend_set_ops(&at91_pm_ops);
786 pr_info("AT91: PM: standby: %s, suspend: %s\n",
787 pm_modes[soc_pm.data.standby_mode].pattern,
788 pm_modes[soc_pm.data.suspend_mode].pattern);
790 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
794 void __init at91rm9200_pm_init(void)
796 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
802 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
804 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
806 at91_pm_init(at91rm9200_idle);
809 void __init sam9x60_pm_init(void)
811 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
814 at91_pm_modes_init();
816 at91_pm_init(at91sam9x60_idle);
818 soc_pm.ws_ids = sam9x60_ws_ids;
819 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
822 void __init at91sam9_pm_init(void)
824 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
828 at91_pm_init(at91sam9_idle);
831 void __init sama5_pm_init(void)
833 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
840 void __init sama5d2_pm_init(void)
842 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
845 at91_pm_modes_init();
848 soc_pm.ws_ids = sama5d2_ws_ids;
849 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
850 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
853 static int __init at91_pm_modes_select(char *str)
856 substring_t args[MAX_OPT_ARGS];
857 int standby, suspend;
862 s = strsep(&str, ",");
863 standby = match_token(s, pm_modes, args);
867 suspend = match_token(str, pm_modes, args);
871 soc_pm.data.standby_mode = standby;
872 soc_pm.data.suspend_mode = suspend;
876 early_param("atmel.pm_modes", at91_pm_modes_select);