1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
6 * Copyright (C) 2005 David Brownell
9 #include <linux/genalloc.h>
11 #include <linux/of_address.h>
13 #include <linux/of_platform.h>
14 #include <linux/parser.h>
15 #include <linux/suspend.h>
17 #include <linux/clk/at91_pmc.h>
18 #include <linux/platform_data/atmel.h>
20 #include <soc/at91/pm.h>
22 #include <asm/cacheflush.h>
23 #include <asm/fncpy.h>
24 #include <asm/system_misc.h>
25 #include <asm/suspend.h>
31 * struct at91_pm_bu - AT91 power management backup unit data structure
32 * @suspended: true if suspended to backup mode
34 * @canary: canary data for memory checking after exit from backup mode
39 unsigned long reserved;
45 * struct at91_soc_pm - AT91 SoC power management data structure
46 * @config_shdwc_ws: wakeup sources configuration function for SHDWC
47 * @config_pmc_ws: wakeup srouces configuration function for PMC
48 * @ws_ids: wakup sources of_device_id array
49 * @data: PM data to be used on last phase of suspend
50 * @bu: backup unit mapped data (for backup mode)
53 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
54 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
55 const struct of_device_id *ws_ids;
56 struct at91_pm_bu *bu;
57 struct at91_pm_data data;
61 * enum at91_pm_iomaps: IOs that needs to be mapped for different PM modes
62 * @AT91_PM_IOMAP_SHDWC: SHDWC controller
63 * @AT91_PM_IOMAP_SFRBU: SFRBU controller
70 #define AT91_PM_IOMAP(name) BIT(AT91_PM_IOMAP_##name)
72 static struct at91_soc_pm soc_pm = {
74 .standby_mode = AT91_PM_STANDBY,
75 .suspend_mode = AT91_PM_ULP0,
79 static const match_table_t pm_modes __initconst = {
80 { AT91_PM_STANDBY, "standby" },
81 { AT91_PM_ULP0, "ulp0" },
82 { AT91_PM_ULP0_FAST, "ulp0-fast" },
83 { AT91_PM_ULP1, "ulp1" },
84 { AT91_PM_BACKUP, "backup" },
88 #define at91_ramc_read(id, field) \
89 __raw_readl(soc_pm.data.ramc[id] + field)
91 #define at91_ramc_write(id, field, value) \
92 __raw_writel(value, soc_pm.data.ramc[id] + field)
94 static int at91_pm_valid_state(suspend_state_t state)
98 case PM_SUSPEND_STANDBY:
107 static int canary = 0xA5A5A5A5;
109 struct wakeup_source_info {
110 unsigned int pmc_fsmr_bit;
111 unsigned int shdwc_mr_bit;
115 static const struct wakeup_source_info ws_info[] = {
116 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
117 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
118 { .pmc_fsmr_bit = AT91_PMC_USBAL },
119 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
120 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
121 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
124 static const struct of_device_id sama5d2_ws_ids[] = {
125 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
126 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
127 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
128 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
129 { .compatible = "usb-ohci", .data = &ws_info[2] },
130 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
131 { .compatible = "usb-ehci", .data = &ws_info[2] },
132 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
136 static const struct of_device_id sam9x60_ws_ids[] = {
137 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
138 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
139 { .compatible = "usb-ohci", .data = &ws_info[2] },
140 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
141 { .compatible = "usb-ehci", .data = &ws_info[2] },
142 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
143 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
147 static int at91_pm_config_ws(unsigned int pm_mode, bool set)
149 const struct wakeup_source_info *wsi;
150 const struct of_device_id *match;
151 struct platform_device *pdev;
152 struct device_node *np;
153 unsigned int mode = 0, polarity = 0, val = 0;
155 if (pm_mode != AT91_PM_ULP1)
158 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
162 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
166 if (soc_pm.config_shdwc_ws)
167 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
170 val = readl(soc_pm.data.shdwc + 0x04);
172 /* Loop through defined wakeup sources. */
173 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
174 pdev = of_find_device_by_node(np);
178 if (device_may_wakeup(&pdev->dev)) {
181 /* Check if enabled on SHDWC. */
182 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
185 mode |= wsi->pmc_fsmr_bit;
186 if (wsi->set_polarity)
187 polarity |= wsi->pmc_fsmr_bit;
191 put_device(&pdev->dev);
195 if (soc_pm.config_pmc_ws)
196 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
198 pr_err("AT91: PM: no ULP1 wakeup sources found!");
201 return mode ? 0 : -EPERM;
204 static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
210 val = readl(shdwc + 0x0c);
211 *mode |= (val & 0x3ff);
212 *polarity |= ((val >> 16) & 0x3ff);
217 static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
219 writel(mode, pmc + AT91_PMC_FSMR);
220 writel(polarity, pmc + AT91_PMC_FSPR);
225 static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
227 writel(mode, pmc + AT91_PMC_FSMR);
233 * Called after processes are frozen, but before we shutdown devices.
235 static int at91_pm_begin(suspend_state_t state)
241 soc_pm.data.mode = soc_pm.data.suspend_mode;
244 case PM_SUSPEND_STANDBY:
245 soc_pm.data.mode = soc_pm.data.standby_mode;
249 soc_pm.data.mode = -1;
252 ret = at91_pm_config_ws(soc_pm.data.mode, true);
256 if (soc_pm.data.mode == AT91_PM_BACKUP)
257 soc_pm.bu->suspended = 1;
259 soc_pm.bu->suspended = 0;
265 * Verify that all the clocks are correct before entering
268 static int at91_pm_verify_clocks(void)
273 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
275 /* USB must not be using PLLB */
276 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
277 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
281 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
282 for (i = 0; i < 4; i++) {
285 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
287 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
288 if (css != AT91_PMC_CSS_SLOW) {
289 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
298 * Call this from platform driver suspend() to see how deeply to suspend.
299 * For example, some controllers (like OHCI) need one of the PLL clocks
300 * in order to act as a wakeup source, and those are not available when
301 * going into slow clock mode.
303 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
304 * the very same problem (but not using at91 main_clk), and it'd be better
305 * to add one generic API rather than lots of platform-specific ones.
307 int at91_suspend_entering_slow_clock(void)
309 return (soc_pm.data.mode >= AT91_PM_ULP0);
311 EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
313 static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
314 extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
315 extern u32 at91_pm_suspend_in_sram_sz;
317 static int at91_suspend_finish(unsigned long val)
322 at91_suspend_sram_fn(&soc_pm.data);
327 static void at91_pm_suspend(suspend_state_t state)
329 if (soc_pm.data.mode == AT91_PM_BACKUP) {
330 cpu_suspend(0, at91_suspend_finish);
332 /* The SRAM is lost between suspend cycles */
333 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
334 &at91_pm_suspend_in_sram,
335 at91_pm_suspend_in_sram_sz);
337 at91_suspend_finish(0);
344 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
345 * event sources; and reduces DRAM power. But otherwise it's identical to
346 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
348 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
349 * suspend more deeply, the master clock switches to the clk32k and turns off
350 * the main oscillator
352 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
354 static int at91_pm_enter(suspend_state_t state)
356 #ifdef CONFIG_PINCTRL_AT91
358 * FIXME: this is needed to communicate between the pinctrl driver and
359 * the PM implementation in the machine. Possibly part of the PM
360 * implementation should be moved down into the pinctrl driver and get
361 * called as part of the generic suspend/resume path.
363 at91_pinctrl_gpio_suspend();
368 case PM_SUSPEND_STANDBY:
370 * Ensure that clocks are in a valid state.
372 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
373 !at91_pm_verify_clocks())
376 at91_pm_suspend(state);
385 pr_debug("AT91: PM - bogus suspend state %d\n", state);
390 #ifdef CONFIG_PINCTRL_AT91
391 at91_pinctrl_gpio_resume();
397 * Called right prior to thawing processes.
399 static void at91_pm_end(void)
401 at91_pm_config_ws(soc_pm.data.mode, false);
405 static const struct platform_suspend_ops at91_pm_ops = {
406 .valid = at91_pm_valid_state,
407 .begin = at91_pm_begin,
408 .enter = at91_pm_enter,
412 static struct platform_device at91_cpuidle_device = {
413 .name = "cpuidle-at91",
417 * The AT91RM9200 goes into self-refresh mode with this command, and will
418 * terminate self-refresh automatically on the next SDRAM access.
420 * Self-refresh mode is exited as soon as a memory access is made, but we don't
421 * know for sure when that happens. However, we need to restore the low-power
422 * mode if it was enabled before going idle. Restoring low-power mode while
423 * still in self-refresh is "not recommended", but seems to work.
425 static void at91rm9200_standby(void)
430 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
431 " str %2, [%1, %3]\n\t"
432 " mcr p15, 0, %0, c7, c0, 4\n\t"
434 : "r" (0), "r" (soc_pm.data.ramc[0]),
435 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
438 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
441 static void at91_ddr_standby(void)
443 /* Those two values allow us to delay self-refresh activation
446 u32 mdr, saved_mdr0, saved_mdr1 = 0;
447 u32 saved_lpr0, saved_lpr1 = 0;
449 /* LPDDR1 --> force DDR2 mode during self-refresh */
450 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
451 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
452 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
453 mdr |= AT91_DDRSDRC_MD_DDR2;
454 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
457 if (soc_pm.data.ramc[1]) {
458 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
459 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
460 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
461 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
462 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
463 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
464 mdr |= AT91_DDRSDRC_MD_DDR2;
465 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
469 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
470 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
471 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
473 /* self-refresh mode now */
474 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
475 if (soc_pm.data.ramc[1])
476 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
480 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
481 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
482 if (soc_pm.data.ramc[1]) {
483 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
484 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
488 static void sama5d3_ddr_standby(void)
493 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
494 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
495 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
497 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
501 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
504 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
507 static void at91sam9_sdram_standby(void)
510 u32 saved_lpr0, saved_lpr1 = 0;
512 if (soc_pm.data.ramc[1]) {
513 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
514 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
515 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
518 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
519 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
520 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
522 /* self-refresh mode now */
523 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
524 if (soc_pm.data.ramc[1])
525 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
529 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
530 if (soc_pm.data.ramc[1])
531 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
536 unsigned int memctrl;
539 static const struct ramc_info ramc_infos[] __initconst = {
540 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
541 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
542 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
543 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
546 static const struct of_device_id ramc_ids[] __initconst = {
547 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
548 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
549 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
550 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
554 static __init void at91_dt_ramc(void)
556 struct device_node *np;
557 const struct of_device_id *of_id;
559 void *standby = NULL;
560 const struct ramc_info *ramc;
562 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
563 soc_pm.data.ramc[idx] = of_iomap(np, 0);
564 if (!soc_pm.data.ramc[idx])
565 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
569 standby = ramc->idle;
570 soc_pm.data.memctrl = ramc->memctrl;
576 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
579 pr_warn("ramc no standby function available\n");
583 at91_cpuidle_device.dev.platform_data = standby;
586 static void at91rm9200_idle(void)
589 * Disable the processor clock. The processor will be automatically
590 * re-enabled by an interrupt or by a reset.
592 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
595 static void at91sam9_idle(void)
597 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
601 static void __init at91_pm_sram_init(void)
603 struct gen_pool *sram_pool;
604 phys_addr_t sram_pbase;
605 unsigned long sram_base;
606 struct device_node *node;
607 struct platform_device *pdev = NULL;
609 for_each_compatible_node(node, NULL, "mmio-sram") {
610 pdev = of_find_device_by_node(node);
618 pr_warn("%s: failed to find sram device!\n", __func__);
622 sram_pool = gen_pool_get(&pdev->dev, NULL);
624 pr_warn("%s: sram pool unavailable!\n", __func__);
628 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
630 pr_warn("%s: unable to alloc sram!\n", __func__);
634 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
635 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
636 at91_pm_suspend_in_sram_sz, false);
637 if (!at91_suspend_sram_fn) {
638 pr_warn("SRAM: Could not map\n");
642 /* Copy the pm suspend handler to SRAM */
643 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
644 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
648 put_device(&pdev->dev);
652 static bool __init at91_is_pm_mode_active(int pm_mode)
654 return (soc_pm.data.standby_mode == pm_mode ||
655 soc_pm.data.suspend_mode == pm_mode);
658 static int __init at91_pm_backup_init(void)
660 struct gen_pool *sram_pool;
661 struct device_node *np;
662 struct platform_device *pdev = NULL;
665 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
668 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
671 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
675 pdev = of_find_device_by_node(np);
678 pr_warn("%s: failed to find securam device!\n", __func__);
682 sram_pool = gen_pool_get(&pdev->dev, NULL);
684 pr_warn("%s: securam pool unavailable!\n", __func__);
688 soc_pm.bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
690 pr_warn("%s: unable to alloc securam!\n", __func__);
695 soc_pm.bu->suspended = 0;
696 soc_pm.bu->canary = __pa_symbol(&canary);
697 soc_pm.bu->resume = __pa_symbol(cpu_resume);
702 put_device(&pdev->dev);
706 static const struct of_device_id atmel_shdwc_ids[] = {
707 { .compatible = "atmel,sama5d2-shdwc" },
708 { .compatible = "microchip,sam9x60-shdwc" },
712 static void __init at91_pm_modes_init(const u32 *maps, int len)
714 struct device_node *np;
717 ret = at91_pm_backup_init();
719 if (soc_pm.data.standby_mode == AT91_PM_BACKUP)
720 soc_pm.data.standby_mode = AT91_PM_ULP0;
721 if (soc_pm.data.suspend_mode == AT91_PM_BACKUP)
722 soc_pm.data.suspend_mode = AT91_PM_ULP0;
725 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
726 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC)) {
727 np = of_find_matching_node(NULL, atmel_shdwc_ids);
729 pr_warn("%s: failed to find shdwc!\n", __func__);
731 /* Use ULP0 if it doesn't needs SHDWC.*/
732 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)))
735 mode = AT91_PM_STANDBY;
737 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC))
738 soc_pm.data.standby_mode = mode;
739 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))
740 soc_pm.data.suspend_mode = mode;
742 soc_pm.data.shdwc = of_iomap(np, 0);
747 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
748 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU)) {
749 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
751 pr_warn("%s: failed to find sfrbu!\n", __func__);
754 * Use ULP0 if it doesn't need SHDWC or if SHDWC
755 * was already located.
757 if (!(maps[AT91_PM_ULP0] & AT91_PM_IOMAP(SHDWC)) ||
761 mode = AT91_PM_STANDBY;
763 if (maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU))
764 soc_pm.data.standby_mode = mode;
765 if (maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))
766 soc_pm.data.suspend_mode = mode;
768 soc_pm.data.sfrbu = of_iomap(np, 0);
773 /* Unmap all unnecessary. */
774 if (soc_pm.data.shdwc &&
775 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SHDWC) ||
776 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SHDWC))) {
777 iounmap(soc_pm.data.shdwc);
778 soc_pm.data.shdwc = NULL;
781 if (soc_pm.data.sfrbu &&
782 !(maps[soc_pm.data.standby_mode] & AT91_PM_IOMAP(SFRBU) ||
783 maps[soc_pm.data.suspend_mode] & AT91_PM_IOMAP(SFRBU))) {
784 iounmap(soc_pm.data.sfrbu);
785 soc_pm.data.sfrbu = NULL;
792 unsigned long uhp_udp_mask;
794 unsigned long version;
797 static const struct pmc_info pmc_infos[] __initconst = {
799 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
801 .version = AT91_PMC_V1,
805 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
807 .version = AT91_PMC_V1,
810 .uhp_udp_mask = AT91SAM926x_PMC_UHP,
812 .version = AT91_PMC_V1,
816 .version = AT91_PMC_V1,
819 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
821 .version = AT91_PMC_V2,
825 static const struct of_device_id atmel_pmc_ids[] __initconst = {
826 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
827 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
828 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
829 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
830 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
831 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
832 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
833 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
834 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
835 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
836 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
837 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
841 static void __init at91_pm_modes_validate(const int *modes, int len)
843 u8 i, standby = 0, suspend = 0;
846 for (i = 0; i < len; i++) {
847 if (standby && suspend)
850 if (modes[i] == soc_pm.data.standby_mode && !standby) {
855 if (modes[i] == soc_pm.data.suspend_mode && !suspend) {
862 if (soc_pm.data.suspend_mode == AT91_PM_STANDBY)
865 mode = AT91_PM_STANDBY;
867 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
868 pm_modes[soc_pm.data.standby_mode].pattern,
869 pm_modes[mode].pattern);
870 soc_pm.data.standby_mode = mode;
874 if (soc_pm.data.standby_mode == AT91_PM_ULP0)
875 mode = AT91_PM_STANDBY;
879 pr_warn("AT91: PM: %s mode not supported! Using %s.\n",
880 pm_modes[soc_pm.data.suspend_mode].pattern,
881 pm_modes[mode].pattern);
882 soc_pm.data.suspend_mode = mode;
886 static void __init at91_pm_init(void (*pm_idle)(void))
888 struct device_node *pmc_np;
889 const struct of_device_id *of_id;
890 const struct pmc_info *pmc;
892 if (at91_cpuidle_device.dev.platform_data)
893 platform_device_register(&at91_cpuidle_device);
895 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
896 soc_pm.data.pmc = of_iomap(pmc_np, 0);
898 if (!soc_pm.data.pmc) {
899 pr_err("AT91: PM not supported, PMC not found\n");
904 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
905 soc_pm.data.pmc_mckr_offset = pmc->mckr;
906 soc_pm.data.pmc_version = pmc->version;
909 arm_pm_idle = pm_idle;
913 if (at91_suspend_sram_fn) {
914 suspend_set_ops(&at91_pm_ops);
915 pr_info("AT91: PM: standby: %s, suspend: %s\n",
916 pm_modes[soc_pm.data.standby_mode].pattern,
917 pm_modes[soc_pm.data.suspend_mode].pattern);
919 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
923 void __init at91rm9200_pm_init(void)
925 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
929 * Force STANDBY and ULP0 mode to avoid calling
930 * at91_pm_modes_validate() which may increase booting time.
931 * Platform supports anyway only STANDBY and ULP0 modes.
933 soc_pm.data.standby_mode = AT91_PM_STANDBY;
934 soc_pm.data.suspend_mode = AT91_PM_ULP0;
939 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
941 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
943 at91_pm_init(at91rm9200_idle);
946 void __init sam9x60_pm_init(void)
948 static const int modes[] __initconst = {
949 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
951 static const int iomaps[] __initconst = {
952 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
955 if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
958 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
959 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
963 soc_pm.ws_ids = sam9x60_ws_ids;
964 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
967 void __init at91sam9_pm_init(void)
969 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
973 * Force STANDBY and ULP0 mode to avoid calling
974 * at91_pm_modes_validate() which may increase booting time.
975 * Platform supports anyway only STANDBY and ULP0 modes.
977 soc_pm.data.standby_mode = AT91_PM_STANDBY;
978 soc_pm.data.suspend_mode = AT91_PM_ULP0;
981 at91_pm_init(at91sam9_idle);
984 void __init sama5_pm_init(void)
986 static const int modes[] __initconst = {
987 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST,
990 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
993 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
998 void __init sama5d2_pm_init(void)
1000 static const int modes[] __initconst = {
1001 AT91_PM_STANDBY, AT91_PM_ULP0, AT91_PM_ULP0_FAST, AT91_PM_ULP1,
1004 static const u32 iomaps[] __initconst = {
1005 [AT91_PM_ULP1] = AT91_PM_IOMAP(SHDWC),
1006 [AT91_PM_BACKUP] = AT91_PM_IOMAP(SHDWC) |
1007 AT91_PM_IOMAP(SFRBU),
1010 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
1013 at91_pm_modes_validate(modes, ARRAY_SIZE(modes));
1014 at91_pm_modes_init(iomaps, ARRAY_SIZE(iomaps));
1018 soc_pm.ws_ids = sama5d2_ws_ids;
1019 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
1020 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
1023 static int __init at91_pm_modes_select(char *str)
1026 substring_t args[MAX_OPT_ARGS];
1027 int standby, suspend;
1032 s = strsep(&str, ",");
1033 standby = match_token(s, pm_modes, args);
1037 suspend = match_token(str, pm_modes, args);
1041 soc_pm.data.standby_mode = standby;
1042 soc_pm.data.suspend_mode = suspend;
1046 early_param("atmel.pm_modes", at91_pm_modes_select);