2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Authors: Rusty Russell <rusty@rustcorp.com.au>
4 * Christoffer Dall <c.dall@virtualopensystems.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, version 2, as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 #include <linux/bsearch.h>
22 #include <linux/kvm_host.h>
23 #include <linux/uaccess.h>
24 #include <asm/kvm_arm.h>
25 #include <asm/kvm_host.h>
26 #include <asm/kvm_emulate.h>
27 #include <asm/kvm_coproc.h>
28 #include <asm/kvm_mmu.h>
29 #include <asm/cacheflush.h>
30 #include <asm/cputype.h>
31 #include <trace/events/kvm.h>
33 #include "../vfp/vfpinstr.h"
35 #define CREATE_TRACE_POINTS
40 /******************************************************************************
41 * Co-processor emulation
42 *****************************************************************************/
44 static bool write_to_read_only(struct kvm_vcpu *vcpu,
45 const struct coproc_params *params)
47 WARN_ONCE(1, "CP15 write to read-only register\n");
48 print_cp_instr(params);
49 kvm_inject_undefined(vcpu);
53 static bool read_from_write_only(struct kvm_vcpu *vcpu,
54 const struct coproc_params *params)
56 WARN_ONCE(1, "CP15 read to write-only register\n");
57 print_cp_instr(params);
58 kvm_inject_undefined(vcpu);
62 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
63 static u32 cache_levels;
65 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
69 * kvm_vcpu_arch.cp15 holds cp15 registers as an array of u32, but some
70 * of cp15 registers can be viewed either as couple of two u32 registers
71 * or one u64 register. Current u64 register encoding is that least
72 * significant u32 word is followed by most significant u32 word.
74 static inline void vcpu_cp15_reg64_set(struct kvm_vcpu *vcpu,
75 const struct coproc_reg *r,
78 vcpu_cp15(vcpu, r->reg) = val & 0xffffffff;
79 vcpu_cp15(vcpu, r->reg + 1) = val >> 32;
82 static inline u64 vcpu_cp15_reg64_get(struct kvm_vcpu *vcpu,
83 const struct coproc_reg *r)
87 val = vcpu_cp15(vcpu, r->reg + 1);
89 val = val | vcpu_cp15(vcpu, r->reg);
93 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu, struct kvm_run *run)
95 kvm_inject_undefined(vcpu);
99 int kvm_handle_cp_0_13_access(struct kvm_vcpu *vcpu, struct kvm_run *run)
102 * We can get here, if the host has been built without VFPv3 support,
103 * but the guest attempted a floating point operation.
105 kvm_inject_undefined(vcpu);
109 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
111 kvm_inject_undefined(vcpu);
115 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
118 * Compute guest MPIDR. We build a virtual cluster out of the
119 * vcpu_id, but we read the 'U' bit from the underlying
122 vcpu_cp15(vcpu, c0_MPIDR) = ((read_cpuid_mpidr() & MPIDR_SMP_BITMASK) |
123 ((vcpu->vcpu_id >> 2) << MPIDR_LEVEL_BITS) |
124 (vcpu->vcpu_id & 3));
127 /* TRM entries A7:4.3.31 A15:4.3.28 - RO WI */
128 static bool access_actlr(struct kvm_vcpu *vcpu,
129 const struct coproc_params *p,
130 const struct coproc_reg *r)
133 return ignore_write(vcpu, p);
135 *vcpu_reg(vcpu, p->Rt1) = vcpu_cp15(vcpu, c1_ACTLR);
139 /* TRM entries A7:4.3.56, A15:4.3.60 - R/O. */
140 static bool access_cbar(struct kvm_vcpu *vcpu,
141 const struct coproc_params *p,
142 const struct coproc_reg *r)
145 return write_to_read_only(vcpu, p);
146 return read_zero(vcpu, p);
149 /* TRM entries A7:4.3.49, A15:4.3.48 - R/O WI */
150 static bool access_l2ctlr(struct kvm_vcpu *vcpu,
151 const struct coproc_params *p,
152 const struct coproc_reg *r)
155 return ignore_write(vcpu, p);
157 *vcpu_reg(vcpu, p->Rt1) = vcpu_cp15(vcpu, c9_L2CTLR);
161 static void reset_l2ctlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
165 asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
166 l2ctlr &= ~(3 << 24);
167 ncores = atomic_read(&vcpu->kvm->online_vcpus) - 1;
168 /* How many cores in the current cluster and the next ones */
169 ncores -= (vcpu->vcpu_id & ~3);
170 /* Cap it to the maximum number of cores in a single cluster */
171 ncores = min(ncores, 3U);
172 l2ctlr |= (ncores & 3) << 24;
174 vcpu_cp15(vcpu, c9_L2CTLR) = l2ctlr;
177 static void reset_actlr(struct kvm_vcpu *vcpu, const struct coproc_reg *r)
181 /* ACTLR contains SMP bit: make sure you create all cpus first! */
182 asm volatile("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));
183 /* Make the SMP bit consistent with the guest configuration */
184 if (atomic_read(&vcpu->kvm->online_vcpus) > 1)
189 vcpu_cp15(vcpu, c1_ACTLR) = actlr;
193 * TRM entries: A7:4.3.50, A15:4.3.49
194 * R/O WI (even if NSACR.NS_L2ERR, a write of 1 is ignored).
196 static bool access_l2ectlr(struct kvm_vcpu *vcpu,
197 const struct coproc_params *p,
198 const struct coproc_reg *r)
201 return ignore_write(vcpu, p);
203 *vcpu_reg(vcpu, p->Rt1) = 0;
208 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
210 static bool access_dcsw(struct kvm_vcpu *vcpu,
211 const struct coproc_params *p,
212 const struct coproc_reg *r)
215 return read_from_write_only(vcpu, p);
217 kvm_set_way_flush(vcpu);
222 * Generic accessor for VM registers. Only called as long as HCR_TVM
223 * is set. If the guest enables the MMU, we stop trapping the VM
224 * sys_regs and leave it in complete control of the caches.
226 * Used by the cpu-specific code.
228 bool access_vm_reg(struct kvm_vcpu *vcpu,
229 const struct coproc_params *p,
230 const struct coproc_reg *r)
232 bool was_enabled = vcpu_has_cache_enabled(vcpu);
234 BUG_ON(!p->is_write);
236 vcpu_cp15(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt1);
238 vcpu_cp15(vcpu, r->reg + 1) = *vcpu_reg(vcpu, p->Rt2);
240 kvm_toggle_cache(vcpu, was_enabled);
244 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
245 const struct coproc_params *p,
246 const struct coproc_reg *r)
251 return read_from_write_only(vcpu, p);
253 reg = (u64)*vcpu_reg(vcpu, p->Rt2) << 32;
254 reg |= *vcpu_reg(vcpu, p->Rt1) ;
256 vgic_v3_dispatch_sgi(vcpu, reg);
261 static bool access_gic_sre(struct kvm_vcpu *vcpu,
262 const struct coproc_params *p,
263 const struct coproc_reg *r)
266 return ignore_write(vcpu, p);
268 *vcpu_reg(vcpu, p->Rt1) = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
273 static bool access_cntp_tval(struct kvm_vcpu *vcpu,
274 const struct coproc_params *p,
275 const struct coproc_reg *r)
277 u64 now = kvm_phys_timer_read();
281 val = *vcpu_reg(vcpu, p->Rt1);
282 kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL, val + now);
284 val = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL);
285 *vcpu_reg(vcpu, p->Rt1) = val - now;
291 static bool access_cntp_ctl(struct kvm_vcpu *vcpu,
292 const struct coproc_params *p,
293 const struct coproc_reg *r)
298 val = *vcpu_reg(vcpu, p->Rt1);
299 kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CTL, val);
301 val = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CTL);
302 *vcpu_reg(vcpu, p->Rt1) = val;
308 static bool access_cntp_cval(struct kvm_vcpu *vcpu,
309 const struct coproc_params *p,
310 const struct coproc_reg *r)
315 val = (u64)*vcpu_reg(vcpu, p->Rt2) << 32;
316 val |= *vcpu_reg(vcpu, p->Rt1);
317 kvm_arm_timer_set_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL, val);
319 val = kvm_arm_timer_get_reg(vcpu, KVM_REG_ARM_PTIMER_CVAL);
320 *vcpu_reg(vcpu, p->Rt1) = val;
321 *vcpu_reg(vcpu, p->Rt2) = val >> 32;
328 * We could trap ID_DFR0 and tell the guest we don't support performance
329 * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
330 * NAKed, so it will read the PMCR anyway.
332 * Therefore we tell the guest we have 0 counters. Unfortunately, we
333 * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
334 * all PM registers, which doesn't crash the guest kernel at least.
336 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
337 const struct coproc_params *p,
338 const struct coproc_reg *r)
341 return ignore_write(vcpu, p);
343 return read_zero(vcpu, p);
346 #define access_pmcr trap_raz_wi
347 #define access_pmcntenset trap_raz_wi
348 #define access_pmcntenclr trap_raz_wi
349 #define access_pmovsr trap_raz_wi
350 #define access_pmselr trap_raz_wi
351 #define access_pmceid0 trap_raz_wi
352 #define access_pmceid1 trap_raz_wi
353 #define access_pmccntr trap_raz_wi
354 #define access_pmxevtyper trap_raz_wi
355 #define access_pmxevcntr trap_raz_wi
356 #define access_pmuserenr trap_raz_wi
357 #define access_pmintenset trap_raz_wi
358 #define access_pmintenclr trap_raz_wi
360 /* Architected CP15 registers.
361 * CRn denotes the primary register number, but is copied to the CRm in the
362 * user space API for 64-bit register access in line with the terminology used
364 * Important: Must be sorted ascending by CRn, CRM, Op1, Op2 and with 64-bit
365 * registers preceding 32-bit ones.
367 static const struct coproc_reg cp15_regs[] = {
368 /* MPIDR: we use VMPIDR for guest access. */
369 { CRn( 0), CRm( 0), Op1( 0), Op2( 5), is32,
370 NULL, reset_mpidr, c0_MPIDR },
372 /* CSSELR: swapped by interrupt.S. */
373 { CRn( 0), CRm( 0), Op1( 2), Op2( 0), is32,
374 NULL, reset_unknown, c0_CSSELR },
376 /* ACTLR: trapped by HCR.TAC bit. */
377 { CRn( 1), CRm( 0), Op1( 0), Op2( 1), is32,
378 access_actlr, reset_actlr, c1_ACTLR },
380 /* CPACR: swapped by interrupt.S. */
381 { CRn( 1), CRm( 0), Op1( 0), Op2( 2), is32,
382 NULL, reset_val, c1_CPACR, 0x00000000 },
384 /* TTBR0/TTBR1/TTBCR: swapped by interrupt.S. */
385 { CRm64( 2), Op1( 0), is64, access_vm_reg, reset_unknown64, c2_TTBR0 },
386 { CRn(2), CRm( 0), Op1( 0), Op2( 0), is32,
387 access_vm_reg, reset_unknown, c2_TTBR0 },
388 { CRn(2), CRm( 0), Op1( 0), Op2( 1), is32,
389 access_vm_reg, reset_unknown, c2_TTBR1 },
390 { CRn( 2), CRm( 0), Op1( 0), Op2( 2), is32,
391 access_vm_reg, reset_val, c2_TTBCR, 0x00000000 },
392 { CRm64( 2), Op1( 1), is64, access_vm_reg, reset_unknown64, c2_TTBR1 },
395 /* DACR: swapped by interrupt.S. */
396 { CRn( 3), CRm( 0), Op1( 0), Op2( 0), is32,
397 access_vm_reg, reset_unknown, c3_DACR },
399 /* DFSR/IFSR/ADFSR/AIFSR: swapped by interrupt.S. */
400 { CRn( 5), CRm( 0), Op1( 0), Op2( 0), is32,
401 access_vm_reg, reset_unknown, c5_DFSR },
402 { CRn( 5), CRm( 0), Op1( 0), Op2( 1), is32,
403 access_vm_reg, reset_unknown, c5_IFSR },
404 { CRn( 5), CRm( 1), Op1( 0), Op2( 0), is32,
405 access_vm_reg, reset_unknown, c5_ADFSR },
406 { CRn( 5), CRm( 1), Op1( 0), Op2( 1), is32,
407 access_vm_reg, reset_unknown, c5_AIFSR },
409 /* DFAR/IFAR: swapped by interrupt.S. */
410 { CRn( 6), CRm( 0), Op1( 0), Op2( 0), is32,
411 access_vm_reg, reset_unknown, c6_DFAR },
412 { CRn( 6), CRm( 0), Op1( 0), Op2( 2), is32,
413 access_vm_reg, reset_unknown, c6_IFAR },
415 /* PAR swapped by interrupt.S */
416 { CRm64( 7), Op1( 0), is64, NULL, reset_unknown64, c7_PAR },
419 * DC{C,I,CI}SW operations:
421 { CRn( 7), CRm( 6), Op1( 0), Op2( 2), is32, access_dcsw},
422 { CRn( 7), CRm(10), Op1( 0), Op2( 2), is32, access_dcsw},
423 { CRn( 7), CRm(14), Op1( 0), Op2( 2), is32, access_dcsw},
425 * L2CTLR access (guest wants to know #CPUs).
427 { CRn( 9), CRm( 0), Op1( 1), Op2( 2), is32,
428 access_l2ctlr, reset_l2ctlr, c9_L2CTLR },
429 { CRn( 9), CRm( 0), Op1( 1), Op2( 3), is32, access_l2ectlr},
432 * Dummy performance monitor implementation.
434 { CRn( 9), CRm(12), Op1( 0), Op2( 0), is32, access_pmcr},
435 { CRn( 9), CRm(12), Op1( 0), Op2( 1), is32, access_pmcntenset},
436 { CRn( 9), CRm(12), Op1( 0), Op2( 2), is32, access_pmcntenclr},
437 { CRn( 9), CRm(12), Op1( 0), Op2( 3), is32, access_pmovsr},
438 { CRn( 9), CRm(12), Op1( 0), Op2( 5), is32, access_pmselr},
439 { CRn( 9), CRm(12), Op1( 0), Op2( 6), is32, access_pmceid0},
440 { CRn( 9), CRm(12), Op1( 0), Op2( 7), is32, access_pmceid1},
441 { CRn( 9), CRm(13), Op1( 0), Op2( 0), is32, access_pmccntr},
442 { CRn( 9), CRm(13), Op1( 0), Op2( 1), is32, access_pmxevtyper},
443 { CRn( 9), CRm(13), Op1( 0), Op2( 2), is32, access_pmxevcntr},
444 { CRn( 9), CRm(14), Op1( 0), Op2( 0), is32, access_pmuserenr},
445 { CRn( 9), CRm(14), Op1( 0), Op2( 1), is32, access_pmintenset},
446 { CRn( 9), CRm(14), Op1( 0), Op2( 2), is32, access_pmintenclr},
448 /* PRRR/NMRR (aka MAIR0/MAIR1): swapped by interrupt.S. */
449 { CRn(10), CRm( 2), Op1( 0), Op2( 0), is32,
450 access_vm_reg, reset_unknown, c10_PRRR},
451 { CRn(10), CRm( 2), Op1( 0), Op2( 1), is32,
452 access_vm_reg, reset_unknown, c10_NMRR},
454 /* AMAIR0/AMAIR1: swapped by interrupt.S. */
455 { CRn(10), CRm( 3), Op1( 0), Op2( 0), is32,
456 access_vm_reg, reset_unknown, c10_AMAIR0},
457 { CRn(10), CRm( 3), Op1( 0), Op2( 1), is32,
458 access_vm_reg, reset_unknown, c10_AMAIR1},
461 { CRm64(12), Op1( 0), is64, access_gic_sgi},
463 /* VBAR: swapped by interrupt.S. */
464 { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32,
465 NULL, reset_val, c12_VBAR, 0x00000000 },
468 { CRn(12), CRm(12), Op1( 0), Op2(5), is32, access_gic_sre },
470 /* CONTEXTIDR/TPIDRURW/TPIDRURO/TPIDRPRW: swapped by interrupt.S. */
471 { CRn(13), CRm( 0), Op1( 0), Op2( 1), is32,
472 access_vm_reg, reset_val, c13_CID, 0x00000000 },
473 { CRn(13), CRm( 0), Op1( 0), Op2( 2), is32,
474 NULL, reset_unknown, c13_TID_URW },
475 { CRn(13), CRm( 0), Op1( 0), Op2( 3), is32,
476 NULL, reset_unknown, c13_TID_URO },
477 { CRn(13), CRm( 0), Op1( 0), Op2( 4), is32,
478 NULL, reset_unknown, c13_TID_PRIV },
481 { CRm64(14), Op1( 2), is64, access_cntp_cval},
483 /* CNTKCTL: swapped by interrupt.S. */
484 { CRn(14), CRm( 1), Op1( 0), Op2( 0), is32,
485 NULL, reset_val, c14_CNTKCTL, 0x00000000 },
488 { CRn(14), CRm( 2), Op1( 0), Op2( 0), is32, access_cntp_tval },
489 { CRn(14), CRm( 2), Op1( 0), Op2( 1), is32, access_cntp_ctl },
491 /* The Configuration Base Address Register. */
492 { CRn(15), CRm( 0), Op1( 4), Op2( 0), is32, access_cbar},
495 static int check_reg_table(const struct coproc_reg *table, unsigned int n)
499 for (i = 1; i < n; i++) {
500 if (cmp_reg(&table[i-1], &table[i]) >= 0) {
501 kvm_err("reg table %p out of order (%d)\n", table, i - 1);
509 /* Target specific emulation tables */
510 static struct kvm_coproc_target_table *target_tables[KVM_ARM_NUM_TARGETS];
512 void kvm_register_target_coproc_table(struct kvm_coproc_target_table *table)
514 BUG_ON(check_reg_table(table->table, table->num));
515 target_tables[table->target] = table;
518 /* Get specific register table for this target. */
519 static const struct coproc_reg *get_target_table(unsigned target, size_t *num)
521 struct kvm_coproc_target_table *table;
523 table = target_tables[target];
528 #define reg_to_match_value(x) \
531 val = (x)->CRn << 11; \
532 val |= (x)->CRm << 7; \
533 val |= (x)->Op1 << 4; \
534 val |= (x)->Op2 << 1; \
535 val |= !(x)->is_64bit; \
539 static int match_reg(const void *key, const void *elt)
541 const unsigned long pval = (unsigned long)key;
542 const struct coproc_reg *r = elt;
544 return pval - reg_to_match_value(r);
547 static const struct coproc_reg *find_reg(const struct coproc_params *params,
548 const struct coproc_reg table[],
551 unsigned long pval = reg_to_match_value(params);
553 return bsearch((void *)pval, table, num, sizeof(table[0]), match_reg);
556 static int emulate_cp15(struct kvm_vcpu *vcpu,
557 const struct coproc_params *params)
560 const struct coproc_reg *table, *r;
562 trace_kvm_emulate_cp15_imp(params->Op1, params->Rt1, params->CRn,
563 params->CRm, params->Op2, params->is_write);
565 table = get_target_table(vcpu->arch.target, &num);
567 /* Search target-specific then generic table. */
568 r = find_reg(params, table, num);
570 r = find_reg(params, cp15_regs, ARRAY_SIZE(cp15_regs));
573 /* If we don't have an accessor, we should never get here! */
576 if (likely(r->access(vcpu, params, r))) {
577 /* Skip instruction, since it was emulated */
578 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
581 /* If access function fails, it should complain. */
582 kvm_err("Unsupported guest CP15 access at: %08lx\n",
584 print_cp_instr(params);
585 kvm_inject_undefined(vcpu);
591 static struct coproc_params decode_64bit_hsr(struct kvm_vcpu *vcpu)
593 struct coproc_params params;
595 params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
596 params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
597 params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
598 params.is_64bit = true;
600 params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf;
602 params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
609 * kvm_handle_cp15_64 -- handles a mrrc/mcrr trap on a guest CP15 access
610 * @vcpu: The VCPU pointer
611 * @run: The kvm_run struct
613 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
615 struct coproc_params params = decode_64bit_hsr(vcpu);
617 return emulate_cp15(vcpu, ¶ms);
621 * kvm_handle_cp14_64 -- handles a mrrc/mcrr trap on a guest CP14 access
622 * @vcpu: The VCPU pointer
623 * @run: The kvm_run struct
625 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
627 struct coproc_params params = decode_64bit_hsr(vcpu);
630 trap_raz_wi(vcpu, ¶ms, NULL);
633 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
637 static void reset_coproc_regs(struct kvm_vcpu *vcpu,
638 const struct coproc_reg *table, size_t num)
642 for (i = 0; i < num; i++)
644 table[i].reset(vcpu, &table[i]);
647 static struct coproc_params decode_32bit_hsr(struct kvm_vcpu *vcpu)
649 struct coproc_params params;
651 params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
652 params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
653 params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
654 params.is_64bit = false;
656 params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
657 params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7;
658 params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7;
665 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
666 * @vcpu: The VCPU pointer
667 * @run: The kvm_run struct
669 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
671 struct coproc_params params = decode_32bit_hsr(vcpu);
672 return emulate_cp15(vcpu, ¶ms);
676 * kvm_handle_cp14_32 -- handles a mrc/mcr trap on a guest CP14 access
677 * @vcpu: The VCPU pointer
678 * @run: The kvm_run struct
680 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
682 struct coproc_params params = decode_32bit_hsr(vcpu);
685 trap_raz_wi(vcpu, ¶ms, NULL);
688 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
692 /******************************************************************************
694 *****************************************************************************/
696 static bool index_to_params(u64 id, struct coproc_params *params)
698 switch (id & KVM_REG_SIZE_MASK) {
699 case KVM_REG_SIZE_U32:
700 /* Any unused index bits means it's not valid. */
701 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
702 | KVM_REG_ARM_COPROC_MASK
703 | KVM_REG_ARM_32_CRN_MASK
704 | KVM_REG_ARM_CRM_MASK
705 | KVM_REG_ARM_OPC1_MASK
706 | KVM_REG_ARM_32_OPC2_MASK))
709 params->is_64bit = false;
710 params->CRn = ((id & KVM_REG_ARM_32_CRN_MASK)
711 >> KVM_REG_ARM_32_CRN_SHIFT);
712 params->CRm = ((id & KVM_REG_ARM_CRM_MASK)
713 >> KVM_REG_ARM_CRM_SHIFT);
714 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
715 >> KVM_REG_ARM_OPC1_SHIFT);
716 params->Op2 = ((id & KVM_REG_ARM_32_OPC2_MASK)
717 >> KVM_REG_ARM_32_OPC2_SHIFT);
719 case KVM_REG_SIZE_U64:
720 /* Any unused index bits means it's not valid. */
721 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
722 | KVM_REG_ARM_COPROC_MASK
723 | KVM_REG_ARM_CRM_MASK
724 | KVM_REG_ARM_OPC1_MASK))
726 params->is_64bit = true;
727 /* CRm to CRn: see cp15_to_index for details */
728 params->CRn = ((id & KVM_REG_ARM_CRM_MASK)
729 >> KVM_REG_ARM_CRM_SHIFT);
730 params->Op1 = ((id & KVM_REG_ARM_OPC1_MASK)
731 >> KVM_REG_ARM_OPC1_SHIFT);
740 /* Decode an index value, and find the cp15 coproc_reg entry. */
741 static const struct coproc_reg *index_to_coproc_reg(struct kvm_vcpu *vcpu,
745 const struct coproc_reg *table, *r;
746 struct coproc_params params;
748 /* We only do cp15 for now. */
749 if ((id & KVM_REG_ARM_COPROC_MASK) >> KVM_REG_ARM_COPROC_SHIFT != 15)
752 if (!index_to_params(id, ¶ms))
755 table = get_target_table(vcpu->arch.target, &num);
756 r = find_reg(¶ms, table, num);
758 r = find_reg(¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
760 /* Not saved in the cp15 array? */
768 * These are the invariant cp15 registers: we let the guest see the host
769 * versions of these, so they're part of the guest state.
771 * A future CPU may provide a mechanism to present different values to
772 * the guest, or a future kvm may trap them.
774 /* Unfortunately, there's no register-argument for mrc, so generate. */
775 #define FUNCTION_FOR32(crn, crm, op1, op2, name) \
776 static void get_##name(struct kvm_vcpu *v, \
777 const struct coproc_reg *r) \
781 asm volatile("mrc p15, " __stringify(op1) \
782 ", %0, c" __stringify(crn) \
783 ", c" __stringify(crm) \
784 ", " __stringify(op2) "\n" : "=r" (val)); \
785 ((struct coproc_reg *)r)->val = val; \
788 FUNCTION_FOR32(0, 0, 0, 0, MIDR)
789 FUNCTION_FOR32(0, 0, 0, 1, CTR)
790 FUNCTION_FOR32(0, 0, 0, 2, TCMTR)
791 FUNCTION_FOR32(0, 0, 0, 3, TLBTR)
792 FUNCTION_FOR32(0, 0, 0, 6, REVIDR)
793 FUNCTION_FOR32(0, 1, 0, 0, ID_PFR0)
794 FUNCTION_FOR32(0, 1, 0, 1, ID_PFR1)
795 FUNCTION_FOR32(0, 1, 0, 2, ID_DFR0)
796 FUNCTION_FOR32(0, 1, 0, 3, ID_AFR0)
797 FUNCTION_FOR32(0, 1, 0, 4, ID_MMFR0)
798 FUNCTION_FOR32(0, 1, 0, 5, ID_MMFR1)
799 FUNCTION_FOR32(0, 1, 0, 6, ID_MMFR2)
800 FUNCTION_FOR32(0, 1, 0, 7, ID_MMFR3)
801 FUNCTION_FOR32(0, 2, 0, 0, ID_ISAR0)
802 FUNCTION_FOR32(0, 2, 0, 1, ID_ISAR1)
803 FUNCTION_FOR32(0, 2, 0, 2, ID_ISAR2)
804 FUNCTION_FOR32(0, 2, 0, 3, ID_ISAR3)
805 FUNCTION_FOR32(0, 2, 0, 4, ID_ISAR4)
806 FUNCTION_FOR32(0, 2, 0, 5, ID_ISAR5)
807 FUNCTION_FOR32(0, 0, 1, 1, CLIDR)
808 FUNCTION_FOR32(0, 0, 1, 7, AIDR)
810 /* ->val is filled in by kvm_invariant_coproc_table_init() */
811 static struct coproc_reg invariant_cp15[] = {
812 { CRn( 0), CRm( 0), Op1( 0), Op2( 0), is32, NULL, get_MIDR },
813 { CRn( 0), CRm( 0), Op1( 0), Op2( 1), is32, NULL, get_CTR },
814 { CRn( 0), CRm( 0), Op1( 0), Op2( 2), is32, NULL, get_TCMTR },
815 { CRn( 0), CRm( 0), Op1( 0), Op2( 3), is32, NULL, get_TLBTR },
816 { CRn( 0), CRm( 0), Op1( 0), Op2( 6), is32, NULL, get_REVIDR },
818 { CRn( 0), CRm( 0), Op1( 1), Op2( 1), is32, NULL, get_CLIDR },
819 { CRn( 0), CRm( 0), Op1( 1), Op2( 7), is32, NULL, get_AIDR },
821 { CRn( 0), CRm( 1), Op1( 0), Op2( 0), is32, NULL, get_ID_PFR0 },
822 { CRn( 0), CRm( 1), Op1( 0), Op2( 1), is32, NULL, get_ID_PFR1 },
823 { CRn( 0), CRm( 1), Op1( 0), Op2( 2), is32, NULL, get_ID_DFR0 },
824 { CRn( 0), CRm( 1), Op1( 0), Op2( 3), is32, NULL, get_ID_AFR0 },
825 { CRn( 0), CRm( 1), Op1( 0), Op2( 4), is32, NULL, get_ID_MMFR0 },
826 { CRn( 0), CRm( 1), Op1( 0), Op2( 5), is32, NULL, get_ID_MMFR1 },
827 { CRn( 0), CRm( 1), Op1( 0), Op2( 6), is32, NULL, get_ID_MMFR2 },
828 { CRn( 0), CRm( 1), Op1( 0), Op2( 7), is32, NULL, get_ID_MMFR3 },
830 { CRn( 0), CRm( 2), Op1( 0), Op2( 0), is32, NULL, get_ID_ISAR0 },
831 { CRn( 0), CRm( 2), Op1( 0), Op2( 1), is32, NULL, get_ID_ISAR1 },
832 { CRn( 0), CRm( 2), Op1( 0), Op2( 2), is32, NULL, get_ID_ISAR2 },
833 { CRn( 0), CRm( 2), Op1( 0), Op2( 3), is32, NULL, get_ID_ISAR3 },
834 { CRn( 0), CRm( 2), Op1( 0), Op2( 4), is32, NULL, get_ID_ISAR4 },
835 { CRn( 0), CRm( 2), Op1( 0), Op2( 5), is32, NULL, get_ID_ISAR5 },
839 * Reads a register value from a userspace address to a kernel
840 * variable. Make sure that register size matches sizeof(*__val).
842 static int reg_from_user(void *val, const void __user *uaddr, u64 id)
844 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
850 * Writes a register value to a userspace address from a kernel variable.
851 * Make sure that register size matches sizeof(*__val).
853 static int reg_to_user(void __user *uaddr, const void *val, u64 id)
855 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
860 static int get_invariant_cp15(u64 id, void __user *uaddr)
862 struct coproc_params params;
863 const struct coproc_reg *r;
866 if (!index_to_params(id, ¶ms))
869 r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15));
874 if (KVM_REG_SIZE(id) == 4) {
877 ret = reg_to_user(uaddr, &val, id);
878 } else if (KVM_REG_SIZE(id) == 8) {
879 ret = reg_to_user(uaddr, &r->val, id);
884 static int set_invariant_cp15(u64 id, void __user *uaddr)
886 struct coproc_params params;
887 const struct coproc_reg *r;
891 if (!index_to_params(id, ¶ms))
893 r = find_reg(¶ms, invariant_cp15, ARRAY_SIZE(invariant_cp15));
898 if (KVM_REG_SIZE(id) == 4) {
901 err = reg_from_user(&val32, uaddr, id);
904 } else if (KVM_REG_SIZE(id) == 8) {
905 err = reg_from_user(&val, uaddr, id);
910 /* This is what we mean by invariant: you can't change it. */
917 static bool is_valid_cache(u32 val)
921 if (val >= CSSELR_MAX)
924 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
926 ctype = (cache_levels >> (level * 3)) & 7;
929 case 0: /* No cache */
931 case 1: /* Instruction cache only */
933 case 2: /* Data cache only */
934 case 4: /* Unified cache */
936 case 3: /* Separate instruction and data caches */
938 default: /* Reserved: we can't know instruction or data. */
943 /* Which cache CCSIDR represents depends on CSSELR value. */
944 static u32 get_ccsidr(u32 csselr)
948 /* Make sure noone else changes CSSELR during this! */
950 /* Put value into CSSELR */
951 asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
953 /* Read result out of CCSIDR */
954 asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
960 static int demux_c15_get(u64 id, void __user *uaddr)
963 u32 __user *uval = uaddr;
965 /* Fail if we have unknown bits set. */
966 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
967 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
970 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
971 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
972 if (KVM_REG_SIZE(id) != 4)
974 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
975 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
976 if (!is_valid_cache(val))
979 return put_user(get_ccsidr(val), uval);
985 static int demux_c15_set(u64 id, void __user *uaddr)
988 u32 __user *uval = uaddr;
990 /* Fail if we have unknown bits set. */
991 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
992 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
995 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
996 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
997 if (KVM_REG_SIZE(id) != 4)
999 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1000 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1001 if (!is_valid_cache(val))
1004 if (get_user(newval, uval))
1007 /* This is also invariant: you can't change it. */
1008 if (newval != get_ccsidr(val))
1017 static const int vfp_sysregs[] = { KVM_REG_ARM_VFP_FPEXC,
1018 KVM_REG_ARM_VFP_FPSCR,
1019 KVM_REG_ARM_VFP_FPINST,
1020 KVM_REG_ARM_VFP_FPINST2,
1021 KVM_REG_ARM_VFP_MVFR0,
1022 KVM_REG_ARM_VFP_MVFR1,
1023 KVM_REG_ARM_VFP_FPSID };
1025 static unsigned int num_fp_regs(void)
1027 if (((fmrx(MVFR0) & MVFR0_A_SIMD_MASK) >> MVFR0_A_SIMD_BIT) == 2)
1033 static unsigned int num_vfp_regs(void)
1035 /* Normal FP regs + control regs. */
1036 return num_fp_regs() + ARRAY_SIZE(vfp_sysregs);
1039 static int copy_vfp_regids(u64 __user *uindices)
1042 const u64 u32reg = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP;
1043 const u64 u64reg = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP;
1045 for (i = 0; i < num_fp_regs(); i++) {
1046 if (put_user((u64reg | KVM_REG_ARM_VFP_BASE_REG) + i,
1052 for (i = 0; i < ARRAY_SIZE(vfp_sysregs); i++) {
1053 if (put_user(u32reg | vfp_sysregs[i], uindices))
1058 return num_vfp_regs();
1061 static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
1063 u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
1066 /* Fail if we have unknown bits set. */
1067 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1068 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1071 if (vfpid < num_fp_regs()) {
1072 if (KVM_REG_SIZE(id) != 8)
1074 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpregs[vfpid],
1078 /* FP control registers are all 32 bit. */
1079 if (KVM_REG_SIZE(id) != 4)
1083 case KVM_REG_ARM_VFP_FPEXC:
1084 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpexc, id);
1085 case KVM_REG_ARM_VFP_FPSCR:
1086 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpscr, id);
1087 case KVM_REG_ARM_VFP_FPINST:
1088 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpinst, id);
1089 case KVM_REG_ARM_VFP_FPINST2:
1090 return reg_to_user(uaddr, &vcpu->arch.ctxt.vfp.fpinst2, id);
1091 case KVM_REG_ARM_VFP_MVFR0:
1093 return reg_to_user(uaddr, &val, id);
1094 case KVM_REG_ARM_VFP_MVFR1:
1096 return reg_to_user(uaddr, &val, id);
1097 case KVM_REG_ARM_VFP_FPSID:
1099 return reg_to_user(uaddr, &val, id);
1105 static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
1107 u32 vfpid = (id & KVM_REG_ARM_VFP_MASK);
1110 /* Fail if we have unknown bits set. */
1111 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1112 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1115 if (vfpid < num_fp_regs()) {
1116 if (KVM_REG_SIZE(id) != 8)
1118 return reg_from_user(&vcpu->arch.ctxt.vfp.fpregs[vfpid],
1122 /* FP control registers are all 32 bit. */
1123 if (KVM_REG_SIZE(id) != 4)
1127 case KVM_REG_ARM_VFP_FPEXC:
1128 return reg_from_user(&vcpu->arch.ctxt.vfp.fpexc, uaddr, id);
1129 case KVM_REG_ARM_VFP_FPSCR:
1130 return reg_from_user(&vcpu->arch.ctxt.vfp.fpscr, uaddr, id);
1131 case KVM_REG_ARM_VFP_FPINST:
1132 return reg_from_user(&vcpu->arch.ctxt.vfp.fpinst, uaddr, id);
1133 case KVM_REG_ARM_VFP_FPINST2:
1134 return reg_from_user(&vcpu->arch.ctxt.vfp.fpinst2, uaddr, id);
1135 /* These are invariant. */
1136 case KVM_REG_ARM_VFP_MVFR0:
1137 if (reg_from_user(&val, uaddr, id))
1139 if (val != fmrx(MVFR0))
1142 case KVM_REG_ARM_VFP_MVFR1:
1143 if (reg_from_user(&val, uaddr, id))
1145 if (val != fmrx(MVFR1))
1148 case KVM_REG_ARM_VFP_FPSID:
1149 if (reg_from_user(&val, uaddr, id))
1151 if (val != fmrx(FPSID))
1158 #else /* !CONFIG_VFPv3 */
1159 static unsigned int num_vfp_regs(void)
1164 static int copy_vfp_regids(u64 __user *uindices)
1169 static int vfp_get_reg(const struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
1174 static int vfp_set_reg(struct kvm_vcpu *vcpu, u64 id, const void __user *uaddr)
1178 #endif /* !CONFIG_VFPv3 */
1180 int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1182 const struct coproc_reg *r;
1183 void __user *uaddr = (void __user *)(long)reg->addr;
1186 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1187 return demux_c15_get(reg->id, uaddr);
1189 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
1190 return vfp_get_reg(vcpu, reg->id, uaddr);
1192 r = index_to_coproc_reg(vcpu, reg->id);
1194 return get_invariant_cp15(reg->id, uaddr);
1197 if (KVM_REG_SIZE(reg->id) == 8) {
1200 val = vcpu_cp15_reg64_get(vcpu, r);
1201 ret = reg_to_user(uaddr, &val, reg->id);
1202 } else if (KVM_REG_SIZE(reg->id) == 4) {
1203 ret = reg_to_user(uaddr, &vcpu_cp15(vcpu, r->reg), reg->id);
1209 int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1211 const struct coproc_reg *r;
1212 void __user *uaddr = (void __user *)(long)reg->addr;
1215 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1216 return demux_c15_set(reg->id, uaddr);
1218 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_VFP)
1219 return vfp_set_reg(vcpu, reg->id, uaddr);
1221 r = index_to_coproc_reg(vcpu, reg->id);
1223 return set_invariant_cp15(reg->id, uaddr);
1226 if (KVM_REG_SIZE(reg->id) == 8) {
1229 ret = reg_from_user(&val, uaddr, reg->id);
1231 vcpu_cp15_reg64_set(vcpu, r, val);
1232 } else if (KVM_REG_SIZE(reg->id) == 4) {
1233 ret = reg_from_user(&vcpu_cp15(vcpu, r->reg), uaddr, reg->id);
1239 static unsigned int num_demux_regs(void)
1241 unsigned int i, count = 0;
1243 for (i = 0; i < CSSELR_MAX; i++)
1244 if (is_valid_cache(i))
1250 static int write_demux_regids(u64 __user *uindices)
1252 u64 val = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
1255 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
1256 for (i = 0; i < CSSELR_MAX; i++) {
1257 if (!is_valid_cache(i))
1259 if (put_user(val | i, uindices))
1266 static u64 cp15_to_index(const struct coproc_reg *reg)
1268 u64 val = KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT);
1269 if (reg->is_64bit) {
1270 val |= KVM_REG_SIZE_U64;
1271 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
1273 * CRn always denotes the primary coproc. reg. nr. for the
1274 * in-kernel representation, but the user space API uses the
1275 * CRm for the encoding, because it is modelled after the
1276 * MRRC/MCRR instructions: see the ARM ARM rev. c page
1279 val |= (reg->CRn << KVM_REG_ARM_CRM_SHIFT);
1281 val |= KVM_REG_SIZE_U32;
1282 val |= (reg->Op1 << KVM_REG_ARM_OPC1_SHIFT);
1283 val |= (reg->Op2 << KVM_REG_ARM_32_OPC2_SHIFT);
1284 val |= (reg->CRm << KVM_REG_ARM_CRM_SHIFT);
1285 val |= (reg->CRn << KVM_REG_ARM_32_CRN_SHIFT);
1290 static bool copy_reg_to_user(const struct coproc_reg *reg, u64 __user **uind)
1295 if (put_user(cp15_to_index(reg), *uind))
1302 /* Assumed ordered tables, see kvm_coproc_table_init. */
1303 static int walk_cp15(struct kvm_vcpu *vcpu, u64 __user *uind)
1305 const struct coproc_reg *i1, *i2, *end1, *end2;
1306 unsigned int total = 0;
1309 /* We check for duplicates here, to allow arch-specific overrides. */
1310 i1 = get_target_table(vcpu->arch.target, &num);
1313 end2 = cp15_regs + ARRAY_SIZE(cp15_regs);
1315 BUG_ON(i1 == end1 || i2 == end2);
1317 /* Walk carefully, as both tables may refer to the same register. */
1319 int cmp = cmp_reg(i1, i2);
1320 /* target-specific overrides generic entry. */
1322 /* Ignore registers we trap but don't save. */
1324 if (!copy_reg_to_user(i1, &uind))
1329 /* Ignore registers we trap but don't save. */
1331 if (!copy_reg_to_user(i2, &uind))
1337 if (cmp <= 0 && ++i1 == end1)
1339 if (cmp >= 0 && ++i2 == end2)
1345 unsigned long kvm_arm_num_coproc_regs(struct kvm_vcpu *vcpu)
1347 return ARRAY_SIZE(invariant_cp15)
1350 + walk_cp15(vcpu, (u64 __user *)NULL);
1353 int kvm_arm_copy_coproc_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1358 /* Then give them all the invariant registers' indices. */
1359 for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++) {
1360 if (put_user(cp15_to_index(&invariant_cp15[i]), uindices))
1365 err = walk_cp15(vcpu, uindices);
1370 err = copy_vfp_regids(uindices);
1375 return write_demux_regids(uindices);
1378 void kvm_coproc_table_init(void)
1382 /* Make sure tables are unique and in order. */
1383 BUG_ON(check_reg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
1384 BUG_ON(check_reg_table(invariant_cp15, ARRAY_SIZE(invariant_cp15)));
1386 /* We abuse the reset function to overwrite the table itself. */
1387 for (i = 0; i < ARRAY_SIZE(invariant_cp15); i++)
1388 invariant_cp15[i].reset(NULL, &invariant_cp15[i]);
1391 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
1393 * If software reads the Cache Type fields from Ctype1
1394 * upwards, once it has seen a value of 0b000, no caches
1395 * exist at further-out levels of the hierarchy. So, for
1396 * example, if Ctype3 is the first Cache Type field with a
1397 * value of 0b000, the values of Ctype4 to Ctype7 must be
1400 asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (cache_levels));
1401 for (i = 0; i < 7; i++)
1402 if (((cache_levels >> (i*3)) & 7) == 0)
1404 /* Clear all higher bits. */
1405 cache_levels &= (1 << (i*3))-1;
1409 * kvm_reset_coprocs - sets cp15 registers to reset value
1410 * @vcpu: The VCPU pointer
1412 * This function finds the right table above and sets the registers on the
1413 * virtual CPU struct to their architecturally defined reset values.
1415 void kvm_reset_coprocs(struct kvm_vcpu *vcpu)
1418 const struct coproc_reg *table;
1420 /* Catch someone adding a register without putting in reset entry. */
1421 memset(vcpu->arch.ctxt.cp15, 0x42, sizeof(vcpu->arch.ctxt.cp15));
1423 /* Generic chip reset first (so target could override). */
1424 reset_coproc_regs(vcpu, cp15_regs, ARRAY_SIZE(cp15_regs));
1426 table = get_target_table(vcpu->arch.target, &num);
1427 reset_coproc_regs(vcpu, table, num);
1429 for (num = 1; num < NR_CP15_REGS; num++)
1430 if (vcpu_cp15(vcpu, num) == 0x42424242)
1431 panic("Didn't reset vcpu_cp15(vcpu, %zi)", num);