2 * linux/arch/arm/kernel/setup.c
4 * Copyright (C) 1995-2001 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/export.h>
11 #include <linux/kernel.h>
12 #include <linux/stddef.h>
13 #include <linux/ioport.h>
14 #include <linux/delay.h>
15 #include <linux/utsname.h>
16 #include <linux/initrd.h>
17 #include <linux/console.h>
18 #include <linux/bootmem.h>
19 #include <linux/seq_file.h>
20 #include <linux/screen_info.h>
21 #include <linux/of_iommu.h>
22 #include <linux/of_platform.h>
23 #include <linux/init.h>
24 #include <linux/kexec.h>
25 #include <linux/of_fdt.h>
26 #include <linux/cpu.h>
27 #include <linux/interrupt.h>
28 #include <linux/smp.h>
29 #include <linux/proc_fs.h>
30 #include <linux/memblock.h>
31 #include <linux/bug.h>
32 #include <linux/compiler.h>
33 #include <linux/sort.h>
35 #include <asm/unified.h>
38 #include <asm/cputype.h>
40 #include <asm/procinfo.h>
42 #include <asm/sections.h>
43 #include <asm/setup.h>
44 #include <asm/smp_plat.h>
45 #include <asm/mach-types.h>
46 #include <asm/cacheflush.h>
47 #include <asm/cachetype.h>
48 #include <asm/tlbflush.h>
51 #include <asm/mach/arch.h>
52 #include <asm/mach/irq.h>
53 #include <asm/mach/time.h>
54 #include <asm/system_info.h>
55 #include <asm/system_misc.h>
56 #include <asm/traps.h>
57 #include <asm/unwind.h>
58 #include <asm/memblock.h>
64 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
67 static int __init fpe_setup(char *line)
69 memcpy(fpe_type, line, 8);
73 __setup("fpe=", fpe_setup);
76 extern void init_default_cache_policy(unsigned long);
77 extern void paging_init(const struct machine_desc *desc);
78 extern void early_paging_init(const struct machine_desc *,
79 struct proc_info_list *);
80 extern void sanity_check_meminfo(void);
81 extern enum reboot_mode reboot_mode;
82 extern void setup_dma_zone(const struct machine_desc *desc);
84 unsigned int processor_id;
85 EXPORT_SYMBOL(processor_id);
86 unsigned int __machine_arch_type __read_mostly;
87 EXPORT_SYMBOL(__machine_arch_type);
88 unsigned int cacheid __read_mostly;
89 EXPORT_SYMBOL(cacheid);
91 unsigned int __atags_pointer __initdata;
93 unsigned int system_rev;
94 EXPORT_SYMBOL(system_rev);
96 unsigned int system_serial_low;
97 EXPORT_SYMBOL(system_serial_low);
99 unsigned int system_serial_high;
100 EXPORT_SYMBOL(system_serial_high);
102 unsigned int elf_hwcap __read_mostly;
103 EXPORT_SYMBOL(elf_hwcap);
105 unsigned int elf_hwcap2 __read_mostly;
106 EXPORT_SYMBOL(elf_hwcap2);
110 struct processor processor __read_mostly;
113 struct cpu_tlb_fns cpu_tlb __read_mostly;
116 struct cpu_user_fns cpu_user __read_mostly;
119 struct cpu_cache_fns cpu_cache __read_mostly;
121 #ifdef CONFIG_OUTER_CACHE
122 struct outer_cache_fns outer_cache __read_mostly;
123 EXPORT_SYMBOL(outer_cache);
127 * Cached cpu_architecture() result for use by assembler code.
128 * C code should use the cpu_architecture() function instead of accessing this
131 int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
138 } ____cacheline_aligned;
140 #ifndef CONFIG_CPU_V7M
141 static struct stack stacks[NR_CPUS];
144 char elf_platform[ELF_PLATFORM_SIZE];
145 EXPORT_SYMBOL(elf_platform);
147 static const char *cpu_name;
148 static const char *machine_name;
149 static char __initdata cmd_line[COMMAND_LINE_SIZE];
150 const struct machine_desc *machine_desc __initdata;
152 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
153 #define ENDIANNESS ((char)endian_test.l)
155 DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
158 * Standard memory resources
160 static struct resource mem_res[] = {
165 .flags = IORESOURCE_MEM
168 .name = "Kernel code",
171 .flags = IORESOURCE_MEM
174 .name = "Kernel data",
177 .flags = IORESOURCE_MEM
181 #define video_ram mem_res[0]
182 #define kernel_code mem_res[1]
183 #define kernel_data mem_res[2]
185 static struct resource io_res[] = {
190 .flags = IORESOURCE_IO | IORESOURCE_BUSY
196 .flags = IORESOURCE_IO | IORESOURCE_BUSY
202 .flags = IORESOURCE_IO | IORESOURCE_BUSY
206 #define lp0 io_res[0]
207 #define lp1 io_res[1]
208 #define lp2 io_res[2]
210 static const char *proc_arch[] = {
230 #ifdef CONFIG_CPU_V7M
231 static int __get_cpu_architecture(void)
233 return CPU_ARCH_ARMv7M;
236 static int __get_cpu_architecture(void)
240 if ((read_cpuid_id() & 0x0008f000) == 0) {
241 cpu_arch = CPU_ARCH_UNKNOWN;
242 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
243 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
244 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
245 cpu_arch = (read_cpuid_id() >> 16) & 7;
247 cpu_arch += CPU_ARCH_ARMv3;
248 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
251 /* Revised CPUID format. Read the Memory Model Feature
252 * Register 0 and check for VMSAv7 or PMSAv7 */
253 asm("mrc p15, 0, %0, c0, c1, 4"
255 if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
256 (mmfr0 & 0x000000f0) >= 0x00000030)
257 cpu_arch = CPU_ARCH_ARMv7;
258 else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
259 (mmfr0 & 0x000000f0) == 0x00000020)
260 cpu_arch = CPU_ARCH_ARMv6;
262 cpu_arch = CPU_ARCH_UNKNOWN;
264 cpu_arch = CPU_ARCH_UNKNOWN;
270 int __pure cpu_architecture(void)
272 BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
274 return __cpu_architecture;
277 static int cpu_has_aliasing_icache(unsigned int arch)
280 unsigned int id_reg, num_sets, line_size;
282 /* PIPT caches never alias. */
283 if (icache_is_pipt())
286 /* arch specifies the register format */
289 asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
290 : /* No output operands */
293 asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
295 line_size = 4 << ((id_reg & 0x7) + 2);
296 num_sets = ((id_reg >> 13) & 0x7fff) + 1;
297 aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
300 aliasing_icache = read_cpuid_cachetype() & (1 << 11);
303 /* I-cache aliases will be handled by D-cache aliasing code */
307 return aliasing_icache;
310 static void __init cacheid_init(void)
312 unsigned int arch = cpu_architecture();
314 if (arch == CPU_ARCH_ARMv7M) {
316 } else if (arch >= CPU_ARCH_ARMv6) {
317 unsigned int cachetype = read_cpuid_cachetype();
318 if ((cachetype & (7 << 29)) == 4 << 29) {
319 /* ARMv7 register format */
320 arch = CPU_ARCH_ARMv7;
321 cacheid = CACHEID_VIPT_NONALIASING;
322 switch (cachetype & (3 << 14)) {
324 cacheid |= CACHEID_ASID_TAGGED;
327 cacheid |= CACHEID_PIPT;
331 arch = CPU_ARCH_ARMv6;
332 if (cachetype & (1 << 23))
333 cacheid = CACHEID_VIPT_ALIASING;
335 cacheid = CACHEID_VIPT_NONALIASING;
337 if (cpu_has_aliasing_icache(arch))
338 cacheid |= CACHEID_VIPT_I_ALIASING;
340 cacheid = CACHEID_VIVT;
343 pr_info("CPU: %s data cache, %s instruction cache\n",
344 cache_is_vivt() ? "VIVT" :
345 cache_is_vipt_aliasing() ? "VIPT aliasing" :
346 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
347 cache_is_vivt() ? "VIVT" :
348 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
349 icache_is_vipt_aliasing() ? "VIPT aliasing" :
350 icache_is_pipt() ? "PIPT" :
351 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
355 * These functions re-use the assembly code in head.S, which
356 * already provide the required functionality.
358 extern struct proc_info_list *lookup_processor_type(unsigned int);
360 void __init early_print(const char *str, ...)
362 extern void printascii(const char *);
367 vsnprintf(buf, sizeof(buf), str, ap);
370 #ifdef CONFIG_DEBUG_LL
376 static void __init cpuid_init_hwcaps(void)
378 unsigned int divide_instrs, vmsa;
380 if (cpu_architecture() < CPU_ARCH_ARMv7)
383 divide_instrs = (read_cpuid_ext(CPUID_EXT_ISAR0) & 0x0f000000) >> 24;
385 switch (divide_instrs) {
387 elf_hwcap |= HWCAP_IDIVA;
389 elf_hwcap |= HWCAP_IDIVT;
392 /* LPAE implies atomic ldrd/strd instructions */
393 vmsa = (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xf) >> 0;
395 elf_hwcap |= HWCAP_LPAE;
398 static void __init elf_hwcap_fixup(void)
400 unsigned id = read_cpuid_id();
404 * HWCAP_TLS is available only on 1136 r1p0 and later,
405 * see also kuser_get_tls_init.
407 if (read_cpuid_part() == ARM_CPU_PART_ARM1136 &&
408 ((id >> 20) & 3) == 0) {
409 elf_hwcap &= ~HWCAP_TLS;
413 /* Verify if CPUID scheme is implemented */
414 if ((id & 0x000f0000) != 0x000f0000)
418 * If the CPU supports LDREX/STREX and LDREXB/STREXB,
419 * avoid advertising SWP; it may not be atomic with
420 * multiprocessing cores.
422 sync_prim = ((read_cpuid_ext(CPUID_EXT_ISAR3) >> 8) & 0xf0) |
423 ((read_cpuid_ext(CPUID_EXT_ISAR4) >> 20) & 0x0f);
424 if (sync_prim >= 0x13)
425 elf_hwcap &= ~HWCAP_SWP;
429 * cpu_init - initialise one CPU.
431 * cpu_init sets up the per-CPU stacks.
433 void notrace cpu_init(void)
435 #ifndef CONFIG_CPU_V7M
436 unsigned int cpu = smp_processor_id();
437 struct stack *stk = &stacks[cpu];
439 if (cpu >= NR_CPUS) {
440 pr_crit("CPU%u: bad primary CPU number\n", cpu);
445 * This only works on resume and secondary cores. For booting on the
446 * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
448 set_my_cpu_offset(per_cpu_offset(cpu));
453 * Define the placement constraint for the inline asm directive below.
454 * In Thumb-2, msr with an immediate value is not allowed.
456 #ifdef CONFIG_THUMB2_KERNEL
463 * setup stacks for re-entrant exception handlers
467 "add r14, %0, %2\n\t"
470 "add r14, %0, %4\n\t"
473 "add r14, %0, %6\n\t"
476 "add r14, %0, %8\n\t"
481 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
482 "I" (offsetof(struct stack, irq[0])),
483 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
484 "I" (offsetof(struct stack, abt[0])),
485 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
486 "I" (offsetof(struct stack, und[0])),
487 PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
488 "I" (offsetof(struct stack, fiq[0])),
489 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
494 u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
496 void __init smp_setup_processor_id(void)
499 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
500 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
502 cpu_logical_map(0) = cpu;
503 for (i = 1; i < nr_cpu_ids; ++i)
504 cpu_logical_map(i) = i == cpu ? 0 : i;
507 * clear __my_cpu_offset on boot CPU to avoid hang caused by
508 * using percpu variable early, for example, lockdep will
509 * access percpu variable inside lock_release
511 set_my_cpu_offset(0);
513 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
516 struct mpidr_hash mpidr_hash;
519 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
520 * level in order to build a linear index from an
521 * MPIDR value. Resulting algorithm is a collision
522 * free hash carried out through shifting and ORing
524 static void __init smp_build_mpidr_hash(void)
527 u32 fs[3], bits[3], ls, mask = 0;
529 * Pre-scan the list of MPIDRS and filter out bits that do
530 * not contribute to affinity levels, ie they never toggle.
532 for_each_possible_cpu(i)
533 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
534 pr_debug("mask of set bits 0x%x\n", mask);
536 * Find and stash the last and first bit set at all affinity levels to
537 * check how many bits are required to represent them.
539 for (i = 0; i < 3; i++) {
540 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
542 * Find the MSB bit and LSB bits position
543 * to determine how many bits are required
544 * to express the affinity level.
547 fs[i] = affinity ? ffs(affinity) - 1 : 0;
548 bits[i] = ls - fs[i];
551 * An index can be created from the MPIDR by isolating the
552 * significant bits at each affinity level and by shifting
553 * them in order to compress the 24 bits values space to a
554 * compressed set of values. This is equivalent to hashing
555 * the MPIDR through shifting and ORing. It is a collision free
556 * hash though not minimal since some levels might contain a number
557 * of CPUs that is not an exact power of 2 and their bit
558 * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
560 mpidr_hash.shift_aff[0] = fs[0];
561 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
562 mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
564 mpidr_hash.mask = mask;
565 mpidr_hash.bits = bits[2] + bits[1] + bits[0];
566 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
567 mpidr_hash.shift_aff[0],
568 mpidr_hash.shift_aff[1],
569 mpidr_hash.shift_aff[2],
573 * 4x is an arbitrary value used to warn on a hash table much bigger
574 * than expected on most systems.
576 if (mpidr_hash_size() > 4 * num_possible_cpus())
577 pr_warn("Large number of MPIDR hash buckets detected\n");
578 sync_cache_w(&mpidr_hash);
582 static void __init setup_processor(void)
584 struct proc_info_list *list;
587 * locate processor in the list of supported processor
588 * types. The linker builds this table for us from the
589 * entries in arch/arm/mm/proc-*.S
591 list = lookup_processor_type(read_cpuid_id());
593 pr_err("CPU configuration botched (ID %08x), unable to continue.\n",
598 cpu_name = list->cpu_name;
599 __cpu_architecture = __get_cpu_architecture();
602 processor = *list->proc;
605 cpu_tlb = *list->tlb;
608 cpu_user = *list->user;
611 cpu_cache = *list->cache;
614 pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
615 cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
616 proc_arch[cpu_architecture()], get_cr());
618 snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
619 list->arch_name, ENDIANNESS);
620 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
621 list->elf_name, ENDIANNESS);
622 elf_hwcap = list->elf_hwcap;
626 #ifndef CONFIG_ARM_THUMB
627 elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
630 init_default_cache_policy(list->__cpu_mm_mmu_flags);
632 erratum_a15_798181_init();
640 void __init dump_machine_table(void)
642 const struct machine_desc *p;
644 early_print("Available machine support:\n\nID (hex)\tNAME\n");
645 for_each_machine_desc(p)
646 early_print("%08x\t%s\n", p->nr, p->name);
648 early_print("\nPlease check your kernel config and/or bootloader.\n");
651 /* can't use cpu_relax() here as it may require MMU setup */;
654 int __init arm_add_memory(u64 start, u64 size)
659 * Ensure that start/size are aligned to a page boundary.
660 * Size is appropriately rounded down, start is rounded up.
662 size -= start & ~PAGE_MASK;
663 aligned_start = PAGE_ALIGN(start);
665 #ifndef CONFIG_ARCH_PHYS_ADDR_T_64BIT
666 if (aligned_start > ULONG_MAX) {
667 pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
672 if (aligned_start + size > ULONG_MAX) {
673 pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
676 * To ensure bank->start + bank->size is representable in
677 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
678 * This means we lose a page after masking.
680 size = ULONG_MAX - aligned_start;
684 if (aligned_start < PHYS_OFFSET) {
685 if (aligned_start + size <= PHYS_OFFSET) {
686 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
687 aligned_start, aligned_start + size);
691 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
692 aligned_start, (u64)PHYS_OFFSET);
694 size -= PHYS_OFFSET - aligned_start;
695 aligned_start = PHYS_OFFSET;
698 start = aligned_start;
699 size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
702 * Check whether this memory region has non-zero size or
703 * invalid node number.
708 memblock_add(start, size);
713 * Pick out the memory size. We look for mem=size@start,
714 * where start and size are "size[KkMm]"
717 static int __init early_mem(char *p)
719 static int usermem __initdata = 0;
725 * If the user specifies memory size, we
726 * blow away any automatically generated
731 memblock_remove(memblock_start_of_DRAM(),
732 memblock_end_of_DRAM() - memblock_start_of_DRAM());
736 size = memparse(p, &endp);
738 start = memparse(endp + 1, NULL);
740 arm_add_memory(start, size);
744 early_param("mem", early_mem);
746 static void __init request_standard_resources(const struct machine_desc *mdesc)
748 struct memblock_region *region;
749 struct resource *res;
751 kernel_code.start = virt_to_phys(_text);
752 kernel_code.end = virt_to_phys(_etext - 1);
753 kernel_data.start = virt_to_phys(_sdata);
754 kernel_data.end = virt_to_phys(_end - 1);
756 for_each_memblock(memory, region) {
757 res = memblock_virt_alloc(sizeof(*res), 0);
758 res->name = "System RAM";
759 res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
760 res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
761 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
763 request_resource(&iomem_resource, res);
765 if (kernel_code.start >= res->start &&
766 kernel_code.end <= res->end)
767 request_resource(res, &kernel_code);
768 if (kernel_data.start >= res->start &&
769 kernel_data.end <= res->end)
770 request_resource(res, &kernel_data);
773 if (mdesc->video_start) {
774 video_ram.start = mdesc->video_start;
775 video_ram.end = mdesc->video_end;
776 request_resource(&iomem_resource, &video_ram);
780 * Some machines don't have the possibility of ever
781 * possessing lp0, lp1 or lp2
783 if (mdesc->reserve_lp0)
784 request_resource(&ioport_resource, &lp0);
785 if (mdesc->reserve_lp1)
786 request_resource(&ioport_resource, &lp1);
787 if (mdesc->reserve_lp2)
788 request_resource(&ioport_resource, &lp2);
791 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
792 struct screen_info screen_info = {
793 .orig_video_lines = 30,
794 .orig_video_cols = 80,
795 .orig_video_mode = 0,
796 .orig_video_ega_bx = 0,
797 .orig_video_isVGA = 1,
798 .orig_video_points = 8
802 static int __init customize_machine(void)
805 * customizes platform devices, or adds new ones
806 * On DT based machines, we fall back to populating the
807 * machine from the device tree, if no callback is provided,
808 * otherwise we would always need an init_machine callback.
811 if (machine_desc->init_machine)
812 machine_desc->init_machine();
815 of_platform_populate(NULL, of_default_bus_match_table,
820 arch_initcall(customize_machine);
822 static int __init init_machine_late(void)
824 if (machine_desc->init_late)
825 machine_desc->init_late();
828 late_initcall(init_machine_late);
831 static inline unsigned long long get_total_mem(void)
835 total = max_low_pfn - min_low_pfn;
836 return total << PAGE_SHIFT;
840 * reserve_crashkernel() - reserves memory are for crash kernel
842 * This function reserves memory area given in "crashkernel=" kernel command
843 * line parameter. The memory reserved is used by a dump capture kernel when
844 * primary kernel is crashing.
846 static void __init reserve_crashkernel(void)
848 unsigned long long crash_size, crash_base;
849 unsigned long long total_mem;
852 total_mem = get_total_mem();
853 ret = parse_crashkernel(boot_command_line, total_mem,
854 &crash_size, &crash_base);
858 ret = memblock_reserve(crash_base, crash_size);
860 pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
861 (unsigned long)crash_base);
865 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
866 (unsigned long)(crash_size >> 20),
867 (unsigned long)(crash_base >> 20),
868 (unsigned long)(total_mem >> 20));
870 crashk_res.start = crash_base;
871 crashk_res.end = crash_base + crash_size - 1;
872 insert_resource(&iomem_resource, &crashk_res);
875 static inline void reserve_crashkernel(void) {}
876 #endif /* CONFIG_KEXEC */
878 void __init hyp_mode_check(void)
880 #ifdef CONFIG_ARM_VIRT_EXT
883 if (is_hyp_mode_available()) {
884 pr_info("CPU: All CPU(s) started in HYP mode.\n");
885 pr_info("CPU: Virtualization extensions available.\n");
886 } else if (is_hyp_mode_mismatched()) {
887 pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
888 __boot_cpu_mode & MODE_MASK);
889 pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
891 pr_info("CPU: All CPU(s) started in SVC mode.\n");
895 void __init setup_arch(char **cmdline_p)
897 const struct machine_desc *mdesc;
900 mdesc = setup_machine_fdt(__atags_pointer);
902 mdesc = setup_machine_tags(__atags_pointer, __machine_arch_type);
903 machine_desc = mdesc;
904 machine_name = mdesc->name;
905 dump_stack_set_arch_desc("%s", mdesc->name);
907 if (mdesc->reboot_mode != REBOOT_HARD)
908 reboot_mode = mdesc->reboot_mode;
910 init_mm.start_code = (unsigned long) _text;
911 init_mm.end_code = (unsigned long) _etext;
912 init_mm.end_data = (unsigned long) _edata;
913 init_mm.brk = (unsigned long) _end;
915 /* populate cmd_line too for later use, preserving boot_command_line */
916 strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
917 *cmdline_p = cmd_line;
921 early_paging_init(mdesc, lookup_processor_type(read_cpuid_id()));
922 setup_dma_zone(mdesc);
923 sanity_check_meminfo();
924 arm_memblock_init(mdesc);
927 request_standard_resources(mdesc);
930 arm_pm_restart = mdesc->restart;
932 unflatten_device_tree();
934 arm_dt_init_cpu_maps();
938 if (!mdesc->smp_init || !mdesc->smp_init()) {
939 if (psci_smp_available())
940 smp_set_ops(&psci_smp_ops);
942 smp_set_ops(mdesc->smp);
945 smp_build_mpidr_hash();
952 reserve_crashkernel();
954 #ifdef CONFIG_MULTI_IRQ_HANDLER
955 handle_arch_irq = mdesc->handle_irq;
959 #if defined(CONFIG_VGA_CONSOLE)
960 conswitchp = &vga_con;
961 #elif defined(CONFIG_DUMMY_CONSOLE)
962 conswitchp = &dummy_con;
966 if (mdesc->init_early)
971 static int __init topology_init(void)
975 for_each_possible_cpu(cpu) {
976 struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
977 cpuinfo->cpu.hotpluggable = 1;
978 register_cpu(&cpuinfo->cpu, cpu);
983 subsys_initcall(topology_init);
985 #ifdef CONFIG_HAVE_PROC_CPU
986 static int __init proc_cpu_init(void)
988 struct proc_dir_entry *res;
990 res = proc_mkdir("cpu", NULL);
995 fs_initcall(proc_cpu_init);
998 static const char *hwcap_str[] = {
1024 static const char *hwcap2_str[] = {
1033 static int c_show(struct seq_file *m, void *v)
1038 for_each_online_cpu(i) {
1040 * glibc reads /proc/cpuinfo to determine the number of
1041 * online processors, looking for lines beginning with
1042 * "processor". Give glibc what it expects.
1044 seq_printf(m, "processor\t: %d\n", i);
1045 cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
1046 seq_printf(m, "model name\t: %s rev %d (%s)\n",
1047 cpu_name, cpuid & 15, elf_platform);
1049 /* dump out the processor features */
1050 seq_puts(m, "Features\t: ");
1052 for (j = 0; hwcap_str[j]; j++)
1053 if (elf_hwcap & (1 << j))
1054 seq_printf(m, "%s ", hwcap_str[j]);
1056 for (j = 0; hwcap2_str[j]; j++)
1057 if (elf_hwcap2 & (1 << j))
1058 seq_printf(m, "%s ", hwcap2_str[j]);
1060 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
1061 seq_printf(m, "CPU architecture: %s\n",
1062 proc_arch[cpu_architecture()]);
1064 if ((cpuid & 0x0008f000) == 0x00000000) {
1066 seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4);
1068 if ((cpuid & 0x0008f000) == 0x00007000) {
1070 seq_printf(m, "CPU variant\t: 0x%02x\n",
1071 (cpuid >> 16) & 127);
1074 seq_printf(m, "CPU variant\t: 0x%x\n",
1075 (cpuid >> 20) & 15);
1077 seq_printf(m, "CPU part\t: 0x%03x\n",
1078 (cpuid >> 4) & 0xfff);
1080 seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
1083 seq_printf(m, "Hardware\t: %s\n", machine_name);
1084 seq_printf(m, "Revision\t: %04x\n", system_rev);
1085 seq_printf(m, "Serial\t\t: %08x%08x\n",
1086 system_serial_high, system_serial_low);
1091 static void *c_start(struct seq_file *m, loff_t *pos)
1093 return *pos < 1 ? (void *)1 : NULL;
1096 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1102 static void c_stop(struct seq_file *m, void *v)
1106 const struct seq_operations cpuinfo_op = {