1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/kernel/setup.c
5 * Copyright (C) 1995-2001 Russell King
8 #include <linux/export.h>
9 #include <linux/kernel.h>
10 #include <linux/stddef.h>
11 #include <linux/ioport.h>
12 #include <linux/delay.h>
13 #include <linux/utsname.h>
14 #include <linux/initrd.h>
15 #include <linux/console.h>
16 #include <linux/seq_file.h>
17 #include <linux/screen_info.h>
18 #include <linux/of_platform.h>
19 #include <linux/init.h>
20 #include <linux/kexec.h>
21 #include <linux/libfdt.h>
22 #include <linux/of_fdt.h>
23 #include <linux/cpu.h>
24 #include <linux/interrupt.h>
25 #include <linux/smp.h>
26 #include <linux/proc_fs.h>
27 #include <linux/memblock.h>
28 #include <linux/bug.h>
29 #include <linux/compiler.h>
30 #include <linux/sort.h>
31 #include <linux/psci.h>
33 #include <asm/unified.h>
36 #include <asm/cputype.h>
39 #include <asm/early_ioremap.h>
40 #include <asm/fixmap.h>
41 #include <asm/procinfo.h>
43 #include <asm/sections.h>
44 #include <asm/setup.h>
45 #include <asm/smp_plat.h>
46 #include <asm/mach-types.h>
47 #include <asm/cacheflush.h>
48 #include <asm/cachetype.h>
49 #include <asm/tlbflush.h>
50 #include <asm/xen/hypervisor.h>
53 #include <asm/mach/arch.h>
54 #include <asm/mach/irq.h>
55 #include <asm/mach/time.h>
56 #include <asm/system_info.h>
57 #include <asm/system_misc.h>
58 #include <asm/traps.h>
59 #include <asm/unwind.h>
60 #include <asm/memblock.h>
66 #if defined(CONFIG_FPE_NWFPE) || defined(CONFIG_FPE_FASTFPE)
69 static int __init fpe_setup(char *line)
71 memcpy(fpe_type, line, 8);
75 __setup("fpe=", fpe_setup);
78 extern void init_default_cache_policy(unsigned long);
79 extern void paging_init(const struct machine_desc *desc);
80 extern void early_mm_init(const struct machine_desc *);
81 extern void adjust_lowmem_bounds(void);
82 extern enum reboot_mode reboot_mode;
83 extern void setup_dma_zone(const struct machine_desc *desc);
85 unsigned int processor_id;
86 EXPORT_SYMBOL(processor_id);
87 unsigned int __machine_arch_type __read_mostly;
88 EXPORT_SYMBOL(__machine_arch_type);
89 unsigned int cacheid __read_mostly;
90 EXPORT_SYMBOL(cacheid);
92 unsigned int __atags_pointer __initdata;
94 unsigned int system_rev;
95 EXPORT_SYMBOL(system_rev);
97 const char *system_serial;
98 EXPORT_SYMBOL(system_serial);
100 unsigned int system_serial_low;
101 EXPORT_SYMBOL(system_serial_low);
103 unsigned int system_serial_high;
104 EXPORT_SYMBOL(system_serial_high);
106 unsigned int elf_hwcap __read_mostly;
107 EXPORT_SYMBOL(elf_hwcap);
109 unsigned int elf_hwcap2 __read_mostly;
110 EXPORT_SYMBOL(elf_hwcap2);
114 struct processor processor __ro_after_init;
115 #if defined(CONFIG_BIG_LITTLE) && defined(CONFIG_HARDEN_BRANCH_PREDICTOR)
116 struct processor *cpu_vtable[NR_CPUS] = {
122 struct cpu_tlb_fns cpu_tlb __ro_after_init;
125 struct cpu_user_fns cpu_user __ro_after_init;
128 struct cpu_cache_fns cpu_cache __ro_after_init;
130 #ifdef CONFIG_OUTER_CACHE
131 struct outer_cache_fns outer_cache __ro_after_init;
132 EXPORT_SYMBOL(outer_cache);
136 * Cached cpu_architecture() result for use by assembler code.
137 * C code should use the cpu_architecture() function instead of accessing this
140 int __cpu_architecture __read_mostly = CPU_ARCH_UNKNOWN;
147 } ____cacheline_aligned;
149 #ifndef CONFIG_CPU_V7M
150 static struct stack stacks[NR_CPUS];
153 char elf_platform[ELF_PLATFORM_SIZE];
154 EXPORT_SYMBOL(elf_platform);
156 static const char *cpu_name;
157 static const char *machine_name;
158 static char __initdata cmd_line[COMMAND_LINE_SIZE];
159 const struct machine_desc *machine_desc __initdata;
161 static union { char c[4]; unsigned long l; } endian_test __initdata = { { 'l', '?', '?', 'b' } };
162 #define ENDIANNESS ((char)endian_test.l)
164 DEFINE_PER_CPU(struct cpuinfo_arm, cpu_data);
167 * Standard memory resources
169 static struct resource mem_res[] = {
174 .flags = IORESOURCE_MEM
177 .name = "Kernel code",
180 .flags = IORESOURCE_SYSTEM_RAM
183 .name = "Kernel data",
186 .flags = IORESOURCE_SYSTEM_RAM
190 #define video_ram mem_res[0]
191 #define kernel_code mem_res[1]
192 #define kernel_data mem_res[2]
194 static struct resource io_res[] = {
199 .flags = IORESOURCE_IO | IORESOURCE_BUSY
205 .flags = IORESOURCE_IO | IORESOURCE_BUSY
211 .flags = IORESOURCE_IO | IORESOURCE_BUSY
215 #define lp0 io_res[0]
216 #define lp1 io_res[1]
217 #define lp2 io_res[2]
219 static const char *proc_arch[] = {
239 #ifdef CONFIG_CPU_V7M
240 static int __get_cpu_architecture(void)
242 return CPU_ARCH_ARMv7M;
245 static int __get_cpu_architecture(void)
249 if ((read_cpuid_id() & 0x0008f000) == 0) {
250 cpu_arch = CPU_ARCH_UNKNOWN;
251 } else if ((read_cpuid_id() & 0x0008f000) == 0x00007000) {
252 cpu_arch = (read_cpuid_id() & (1 << 23)) ? CPU_ARCH_ARMv4T : CPU_ARCH_ARMv3;
253 } else if ((read_cpuid_id() & 0x00080000) == 0x00000000) {
254 cpu_arch = (read_cpuid_id() >> 16) & 7;
256 cpu_arch += CPU_ARCH_ARMv3;
257 } else if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) {
258 /* Revised CPUID format. Read the Memory Model Feature
259 * Register 0 and check for VMSAv7 or PMSAv7 */
260 unsigned int mmfr0 = read_cpuid_ext(CPUID_EXT_MMFR0);
261 if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
262 (mmfr0 & 0x000000f0) >= 0x00000030)
263 cpu_arch = CPU_ARCH_ARMv7;
264 else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
265 (mmfr0 & 0x000000f0) == 0x00000020)
266 cpu_arch = CPU_ARCH_ARMv6;
268 cpu_arch = CPU_ARCH_UNKNOWN;
270 cpu_arch = CPU_ARCH_UNKNOWN;
276 int __pure cpu_architecture(void)
278 BUG_ON(__cpu_architecture == CPU_ARCH_UNKNOWN);
280 return __cpu_architecture;
283 static int cpu_has_aliasing_icache(unsigned int arch)
286 unsigned int id_reg, num_sets, line_size;
288 /* PIPT caches never alias. */
289 if (icache_is_pipt())
292 /* arch specifies the register format */
295 set_csselr(CSSELR_ICACHE | CSSELR_L1);
297 id_reg = read_ccsidr();
298 line_size = 4 << ((id_reg & 0x7) + 2);
299 num_sets = ((id_reg >> 13) & 0x7fff) + 1;
300 aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
303 aliasing_icache = read_cpuid_cachetype() & (1 << 11);
306 /* I-cache aliases will be handled by D-cache aliasing code */
310 return aliasing_icache;
313 static void __init cacheid_init(void)
315 unsigned int arch = cpu_architecture();
317 if (arch >= CPU_ARCH_ARMv6) {
318 unsigned int cachetype = read_cpuid_cachetype();
320 if ((arch == CPU_ARCH_ARMv7M) && !(cachetype & 0xf000f)) {
322 } else if ((cachetype & (7 << 29)) == 4 << 29) {
323 /* ARMv7 register format */
324 arch = CPU_ARCH_ARMv7;
325 cacheid = CACHEID_VIPT_NONALIASING;
326 switch (cachetype & (3 << 14)) {
328 cacheid |= CACHEID_ASID_TAGGED;
331 cacheid |= CACHEID_PIPT;
335 arch = CPU_ARCH_ARMv6;
336 if (cachetype & (1 << 23))
337 cacheid = CACHEID_VIPT_ALIASING;
339 cacheid = CACHEID_VIPT_NONALIASING;
341 if (cpu_has_aliasing_icache(arch))
342 cacheid |= CACHEID_VIPT_I_ALIASING;
344 cacheid = CACHEID_VIVT;
347 pr_info("CPU: %s data cache, %s instruction cache\n",
348 cache_is_vivt() ? "VIVT" :
349 cache_is_vipt_aliasing() ? "VIPT aliasing" :
350 cache_is_vipt_nonaliasing() ? "PIPT / VIPT nonaliasing" : "unknown",
351 cache_is_vivt() ? "VIVT" :
352 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" :
353 icache_is_vipt_aliasing() ? "VIPT aliasing" :
354 icache_is_pipt() ? "PIPT" :
355 cache_is_vipt_nonaliasing() ? "VIPT nonaliasing" : "unknown");
359 * These functions re-use the assembly code in head.S, which
360 * already provide the required functionality.
362 extern struct proc_info_list *lookup_processor_type(unsigned int);
364 void __init early_print(const char *str, ...)
366 extern void printascii(const char *);
371 vsnprintf(buf, sizeof(buf), str, ap);
374 #ifdef CONFIG_DEBUG_LL
380 #ifdef CONFIG_ARM_PATCH_IDIV
382 static inline u32 __attribute_const__ sdiv_instruction(void)
384 if (IS_ENABLED(CONFIG_THUMB2_KERNEL)) {
385 /* "sdiv r0, r0, r1" */
386 u32 insn = __opcode_thumb32_compose(0xfb90, 0xf0f1);
387 return __opcode_to_mem_thumb32(insn);
390 /* "sdiv r0, r0, r1" */
391 return __opcode_to_mem_arm(0xe710f110);
394 static inline u32 __attribute_const__ udiv_instruction(void)
396 if (IS_ENABLED(CONFIG_THUMB2_KERNEL)) {
397 /* "udiv r0, r0, r1" */
398 u32 insn = __opcode_thumb32_compose(0xfbb0, 0xf0f1);
399 return __opcode_to_mem_thumb32(insn);
402 /* "udiv r0, r0, r1" */
403 return __opcode_to_mem_arm(0xe730f110);
406 static inline u32 __attribute_const__ bx_lr_instruction(void)
408 if (IS_ENABLED(CONFIG_THUMB2_KERNEL)) {
410 u32 insn = __opcode_thumb32_compose(0x4770, 0x46c0);
411 return __opcode_to_mem_thumb32(insn);
415 return __opcode_to_mem_arm(0xe12fff1e);
418 static void __init patch_aeabi_idiv(void)
420 extern void __aeabi_uidiv(void);
421 extern void __aeabi_idiv(void);
425 mask = IS_ENABLED(CONFIG_THUMB2_KERNEL) ? HWCAP_IDIVT : HWCAP_IDIVA;
426 if (!(elf_hwcap & mask))
429 pr_info("CPU: div instructions available: patching division code\n");
431 fn_addr = ((uintptr_t)&__aeabi_uidiv) & ~1;
432 asm ("" : "+g" (fn_addr));
433 ((u32 *)fn_addr)[0] = udiv_instruction();
434 ((u32 *)fn_addr)[1] = bx_lr_instruction();
435 flush_icache_range(fn_addr, fn_addr + 8);
437 fn_addr = ((uintptr_t)&__aeabi_idiv) & ~1;
438 asm ("" : "+g" (fn_addr));
439 ((u32 *)fn_addr)[0] = sdiv_instruction();
440 ((u32 *)fn_addr)[1] = bx_lr_instruction();
441 flush_icache_range(fn_addr, fn_addr + 8);
445 static inline void patch_aeabi_idiv(void) { }
448 static void __init cpuid_init_hwcaps(void)
453 if (cpu_architecture() < CPU_ARCH_ARMv7)
456 block = cpuid_feature_extract(CPUID_EXT_ISAR0, 24);
458 elf_hwcap |= HWCAP_IDIVA;
460 elf_hwcap |= HWCAP_IDIVT;
462 /* LPAE implies atomic ldrd/strd instructions */
463 block = cpuid_feature_extract(CPUID_EXT_MMFR0, 0);
465 elf_hwcap |= HWCAP_LPAE;
467 /* check for supported v8 Crypto instructions */
468 isar5 = read_cpuid_ext(CPUID_EXT_ISAR5);
470 block = cpuid_feature_extract_field(isar5, 4);
472 elf_hwcap2 |= HWCAP2_PMULL;
474 elf_hwcap2 |= HWCAP2_AES;
476 block = cpuid_feature_extract_field(isar5, 8);
478 elf_hwcap2 |= HWCAP2_SHA1;
480 block = cpuid_feature_extract_field(isar5, 12);
482 elf_hwcap2 |= HWCAP2_SHA2;
484 block = cpuid_feature_extract_field(isar5, 16);
486 elf_hwcap2 |= HWCAP2_CRC32;
489 static void __init elf_hwcap_fixup(void)
491 unsigned id = read_cpuid_id();
494 * HWCAP_TLS is available only on 1136 r1p0 and later,
495 * see also kuser_get_tls_init.
497 if (read_cpuid_part() == ARM_CPU_PART_ARM1136 &&
498 ((id >> 20) & 3) == 0) {
499 elf_hwcap &= ~HWCAP_TLS;
503 /* Verify if CPUID scheme is implemented */
504 if ((id & 0x000f0000) != 0x000f0000)
508 * If the CPU supports LDREX/STREX and LDREXB/STREXB,
509 * avoid advertising SWP; it may not be atomic with
510 * multiprocessing cores.
512 if (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) > 1 ||
513 (cpuid_feature_extract(CPUID_EXT_ISAR3, 12) == 1 &&
514 cpuid_feature_extract(CPUID_EXT_ISAR4, 20) >= 3))
515 elf_hwcap &= ~HWCAP_SWP;
519 * cpu_init - initialise one CPU.
521 * cpu_init sets up the per-CPU stacks.
523 void notrace cpu_init(void)
525 #ifndef CONFIG_CPU_V7M
526 unsigned int cpu = smp_processor_id();
527 struct stack *stk = &stacks[cpu];
529 if (cpu >= NR_CPUS) {
530 pr_crit("CPU%u: bad primary CPU number\n", cpu);
535 * This only works on resume and secondary cores. For booting on the
536 * boot cpu, smp_prepare_boot_cpu is called after percpu area setup.
538 set_my_cpu_offset(per_cpu_offset(cpu));
543 * Define the placement constraint for the inline asm directive below.
544 * In Thumb-2, msr with an immediate value is not allowed.
546 #ifdef CONFIG_THUMB2_KERNEL
553 * setup stacks for re-entrant exception handlers
557 "add r14, %0, %2\n\t"
560 "add r14, %0, %4\n\t"
563 "add r14, %0, %6\n\t"
566 "add r14, %0, %8\n\t"
571 PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
572 "I" (offsetof(struct stack, irq[0])),
573 PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
574 "I" (offsetof(struct stack, abt[0])),
575 PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
576 "I" (offsetof(struct stack, und[0])),
577 PLC (PSR_F_BIT | PSR_I_BIT | FIQ_MODE),
578 "I" (offsetof(struct stack, fiq[0])),
579 PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
584 u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
586 void __init smp_setup_processor_id(void)
589 u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
590 u32 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
592 cpu_logical_map(0) = cpu;
593 for (i = 1; i < nr_cpu_ids; ++i)
594 cpu_logical_map(i) = i == cpu ? 0 : i;
597 * clear __my_cpu_offset on boot CPU to avoid hang caused by
598 * using percpu variable early, for example, lockdep will
599 * access percpu variable inside lock_release
601 set_my_cpu_offset(0);
603 pr_info("Booting Linux on physical CPU 0x%x\n", mpidr);
606 struct mpidr_hash mpidr_hash;
609 * smp_build_mpidr_hash - Pre-compute shifts required at each affinity
610 * level in order to build a linear index from an
611 * MPIDR value. Resulting algorithm is a collision
612 * free hash carried out through shifting and ORing
614 static void __init smp_build_mpidr_hash(void)
617 u32 fs[3], bits[3], ls, mask = 0;
619 * Pre-scan the list of MPIDRS and filter out bits that do
620 * not contribute to affinity levels, ie they never toggle.
622 for_each_possible_cpu(i)
623 mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
624 pr_debug("mask of set bits 0x%x\n", mask);
626 * Find and stash the last and first bit set at all affinity levels to
627 * check how many bits are required to represent them.
629 for (i = 0; i < 3; i++) {
630 affinity = MPIDR_AFFINITY_LEVEL(mask, i);
632 * Find the MSB bit and LSB bits position
633 * to determine how many bits are required
634 * to express the affinity level.
637 fs[i] = affinity ? ffs(affinity) - 1 : 0;
638 bits[i] = ls - fs[i];
641 * An index can be created from the MPIDR by isolating the
642 * significant bits at each affinity level and by shifting
643 * them in order to compress the 24 bits values space to a
644 * compressed set of values. This is equivalent to hashing
645 * the MPIDR through shifting and ORing. It is a collision free
646 * hash though not minimal since some levels might contain a number
647 * of CPUs that is not an exact power of 2 and their bit
648 * representation might contain holes, eg MPIDR[7:0] = {0x2, 0x80}.
650 mpidr_hash.shift_aff[0] = fs[0];
651 mpidr_hash.shift_aff[1] = MPIDR_LEVEL_BITS + fs[1] - bits[0];
652 mpidr_hash.shift_aff[2] = 2*MPIDR_LEVEL_BITS + fs[2] -
654 mpidr_hash.mask = mask;
655 mpidr_hash.bits = bits[2] + bits[1] + bits[0];
656 pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] mask[0x%x] bits[%u]\n",
657 mpidr_hash.shift_aff[0],
658 mpidr_hash.shift_aff[1],
659 mpidr_hash.shift_aff[2],
663 * 4x is an arbitrary value used to warn on a hash table much bigger
664 * than expected on most systems.
666 if (mpidr_hash_size() > 4 * num_possible_cpus())
667 pr_warn("Large number of MPIDR hash buckets detected\n");
668 sync_cache_w(&mpidr_hash);
673 * locate processor in the list of supported processor types. The linker
674 * builds this table for us from the entries in arch/arm/mm/proc-*.S
676 struct proc_info_list *lookup_processor(u32 midr)
678 struct proc_info_list *list = lookup_processor_type(midr);
681 pr_err("CPU%u: configuration botched (ID %08x), CPU halted\n",
682 smp_processor_id(), midr);
684 /* can't use cpu_relax() here as it may require MMU setup */;
690 static void __init setup_processor(void)
692 unsigned int midr = read_cpuid_id();
693 struct proc_info_list *list = lookup_processor(midr);
695 cpu_name = list->cpu_name;
696 __cpu_architecture = __get_cpu_architecture();
698 init_proc_vtable(list->proc);
700 cpu_tlb = *list->tlb;
703 cpu_user = *list->user;
706 cpu_cache = *list->cache;
709 pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
710 list->cpu_name, midr, midr & 15,
711 proc_arch[cpu_architecture()], get_cr());
713 snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
714 list->arch_name, ENDIANNESS);
715 snprintf(elf_platform, ELF_PLATFORM_SIZE, "%s%c",
716 list->elf_name, ENDIANNESS);
717 elf_hwcap = list->elf_hwcap;
722 #ifndef CONFIG_ARM_THUMB
723 elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
726 init_default_cache_policy(list->__cpu_mm_mmu_flags);
728 erratum_a15_798181_init();
736 void __init dump_machine_table(void)
738 const struct machine_desc *p;
740 early_print("Available machine support:\n\nID (hex)\tNAME\n");
741 for_each_machine_desc(p)
742 early_print("%08x\t%s\n", p->nr, p->name);
744 early_print("\nPlease check your kernel config and/or bootloader.\n");
747 /* can't use cpu_relax() here as it may require MMU setup */;
750 int __init arm_add_memory(u64 start, u64 size)
755 * Ensure that start/size are aligned to a page boundary.
756 * Size is rounded down, start is rounded up.
758 aligned_start = PAGE_ALIGN(start);
759 if (aligned_start > start + size)
762 size -= aligned_start - start;
764 #ifndef CONFIG_PHYS_ADDR_T_64BIT
765 if (aligned_start > ULONG_MAX) {
766 pr_crit("Ignoring memory at 0x%08llx outside 32-bit physical address space\n",
771 if (aligned_start + size > ULONG_MAX) {
772 pr_crit("Truncating memory at 0x%08llx to fit in 32-bit physical address space\n",
775 * To ensure bank->start + bank->size is representable in
776 * 32 bits, we use ULONG_MAX as the upper limit rather than 4GB.
777 * This means we lose a page after masking.
779 size = ULONG_MAX - aligned_start;
783 if (aligned_start < PHYS_OFFSET) {
784 if (aligned_start + size <= PHYS_OFFSET) {
785 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
786 aligned_start, aligned_start + size);
790 pr_info("Ignoring memory below PHYS_OFFSET: 0x%08llx-0x%08llx\n",
791 aligned_start, (u64)PHYS_OFFSET);
793 size -= PHYS_OFFSET - aligned_start;
794 aligned_start = PHYS_OFFSET;
797 start = aligned_start;
798 size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
801 * Check whether this memory region has non-zero size or
802 * invalid node number.
807 memblock_add(start, size);
812 * Pick out the memory size. We look for mem=size@start,
813 * where start and size are "size[KkMm]"
816 static int __init early_mem(char *p)
818 static int usermem __initdata = 0;
824 * If the user specifies memory size, we
825 * blow away any automatically generated
830 memblock_remove(memblock_start_of_DRAM(),
831 memblock_end_of_DRAM() - memblock_start_of_DRAM());
835 size = memparse(p, &endp);
837 start = memparse(endp + 1, NULL);
839 arm_add_memory(start, size);
843 early_param("mem", early_mem);
845 static void __init request_standard_resources(const struct machine_desc *mdesc)
847 phys_addr_t start, end, res_end;
848 struct resource *res;
851 kernel_code.start = virt_to_phys(_text);
852 kernel_code.end = virt_to_phys(__init_begin - 1);
853 kernel_data.start = virt_to_phys(_sdata);
854 kernel_data.end = virt_to_phys(_end - 1);
856 for_each_mem_range(i, &start, &end) {
857 unsigned long boot_alias_start;
860 * In memblock, end points to the first byte after the
861 * range while in resourses, end points to the last byte in
867 * Some systems have a special memory alias which is only
868 * used for booting. We need to advertise this region to
869 * kexec-tools so they know where bootable RAM is located.
871 boot_alias_start = phys_to_idmap(start);
872 if (arm_has_idmap_alias() && boot_alias_start != IDMAP_INVALID_ADDR) {
873 res = memblock_alloc(sizeof(*res), SMP_CACHE_BYTES);
875 panic("%s: Failed to allocate %zu bytes\n",
876 __func__, sizeof(*res));
877 res->name = "System RAM (boot alias)";
878 res->start = boot_alias_start;
879 res->end = phys_to_idmap(res_end);
880 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
881 request_resource(&iomem_resource, res);
884 res = memblock_alloc(sizeof(*res), SMP_CACHE_BYTES);
886 panic("%s: Failed to allocate %zu bytes\n", __func__,
888 res->name = "System RAM";
891 res->flags = IORESOURCE_SYSTEM_RAM | IORESOURCE_BUSY;
893 request_resource(&iomem_resource, res);
895 if (kernel_code.start >= res->start &&
896 kernel_code.end <= res->end)
897 request_resource(res, &kernel_code);
898 if (kernel_data.start >= res->start &&
899 kernel_data.end <= res->end)
900 request_resource(res, &kernel_data);
903 if (mdesc->video_start) {
904 video_ram.start = mdesc->video_start;
905 video_ram.end = mdesc->video_end;
906 request_resource(&iomem_resource, &video_ram);
910 * Some machines don't have the possibility of ever
911 * possessing lp0, lp1 or lp2
913 if (mdesc->reserve_lp0)
914 request_resource(&ioport_resource, &lp0);
915 if (mdesc->reserve_lp1)
916 request_resource(&ioport_resource, &lp1);
917 if (mdesc->reserve_lp2)
918 request_resource(&ioport_resource, &lp2);
921 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) || \
923 struct screen_info screen_info = {
924 .orig_video_lines = 30,
925 .orig_video_cols = 80,
926 .orig_video_mode = 0,
927 .orig_video_ega_bx = 0,
928 .orig_video_isVGA = 1,
929 .orig_video_points = 8
933 static int __init customize_machine(void)
936 * customizes platform devices, or adds new ones
937 * On DT based machines, we fall back to populating the
938 * machine from the device tree, if no callback is provided,
939 * otherwise we would always need an init_machine callback.
941 if (machine_desc->init_machine)
942 machine_desc->init_machine();
946 arch_initcall(customize_machine);
948 static int __init init_machine_late(void)
950 struct device_node *root;
953 if (machine_desc->init_late)
954 machine_desc->init_late();
956 root = of_find_node_by_path("/");
958 ret = of_property_read_string(root, "serial-number",
961 system_serial = NULL;
965 system_serial = kasprintf(GFP_KERNEL, "%08x%08x",
971 late_initcall(init_machine_late);
975 * The crash region must be aligned to 128MB to avoid
976 * zImage relocating below the reserved region.
978 #define CRASH_ALIGN (128 << 20)
980 static inline unsigned long long get_total_mem(void)
984 total = max_low_pfn - min_low_pfn;
985 return total << PAGE_SHIFT;
989 * reserve_crashkernel() - reserves memory are for crash kernel
991 * This function reserves memory area given in "crashkernel=" kernel command
992 * line parameter. The memory reserved is used by a dump capture kernel when
993 * primary kernel is crashing.
995 static void __init reserve_crashkernel(void)
997 unsigned long long crash_size, crash_base;
998 unsigned long long total_mem;
1001 total_mem = get_total_mem();
1002 ret = parse_crashkernel(boot_command_line, total_mem,
1003 &crash_size, &crash_base);
1007 if (crash_base <= 0) {
1008 unsigned long long crash_max = idmap_to_phys((u32)~0);
1009 unsigned long long lowmem_max = __pa(high_memory - 1) + 1;
1010 if (crash_max > lowmem_max)
1011 crash_max = lowmem_max;
1012 crash_base = memblock_find_in_range(CRASH_ALIGN, crash_max,
1013 crash_size, CRASH_ALIGN);
1015 pr_err("crashkernel reservation failed - No suitable area found.\n");
1019 unsigned long long start;
1021 start = memblock_find_in_range(crash_base,
1022 crash_base + crash_size,
1023 crash_size, SECTION_SIZE);
1024 if (start != crash_base) {
1025 pr_err("crashkernel reservation failed - memory is in use.\n");
1030 ret = memblock_reserve(crash_base, crash_size);
1032 pr_warn("crashkernel reservation failed - memory is in use (0x%lx)\n",
1033 (unsigned long)crash_base);
1037 pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
1038 (unsigned long)(crash_size >> 20),
1039 (unsigned long)(crash_base >> 20),
1040 (unsigned long)(total_mem >> 20));
1042 /* The crashk resource must always be located in normal mem */
1043 crashk_res.start = crash_base;
1044 crashk_res.end = crash_base + crash_size - 1;
1045 insert_resource(&iomem_resource, &crashk_res);
1047 if (arm_has_idmap_alias()) {
1049 * If we have a special RAM alias for use at boot, we
1050 * need to advertise to kexec tools where the alias is.
1052 static struct resource crashk_boot_res = {
1053 .name = "Crash kernel (boot alias)",
1054 .flags = IORESOURCE_BUSY | IORESOURCE_MEM,
1057 crashk_boot_res.start = phys_to_idmap(crash_base);
1058 crashk_boot_res.end = crashk_boot_res.start + crash_size - 1;
1059 insert_resource(&iomem_resource, &crashk_boot_res);
1063 static inline void reserve_crashkernel(void) {}
1064 #endif /* CONFIG_KEXEC */
1066 void __init hyp_mode_check(void)
1068 #ifdef CONFIG_ARM_VIRT_EXT
1071 if (is_hyp_mode_available()) {
1072 pr_info("CPU: All CPU(s) started in HYP mode.\n");
1073 pr_info("CPU: Virtualization extensions available.\n");
1074 } else if (is_hyp_mode_mismatched()) {
1075 pr_warn("CPU: WARNING: CPU(s) started in wrong/inconsistent modes (primary CPU mode 0x%x)\n",
1076 __boot_cpu_mode & MODE_MASK);
1077 pr_warn("CPU: This may indicate a broken bootloader or firmware.\n");
1079 pr_info("CPU: All CPU(s) started in SVC mode.\n");
1083 void __init setup_arch(char **cmdline_p)
1085 const struct machine_desc *mdesc = NULL;
1086 void *atags_vaddr = NULL;
1088 if (__atags_pointer)
1089 atags_vaddr = FDT_VIRT_ADDR(__atags_pointer);
1093 mdesc = setup_machine_fdt(atags_vaddr);
1095 memblock_reserve(__atags_pointer,
1096 fdt_totalsize(atags_vaddr));
1099 mdesc = setup_machine_tags(atags_vaddr, __machine_arch_type);
1101 early_print("\nError: invalid dtb and unrecognized/unsupported machine ID\n");
1102 early_print(" r1=0x%08x, r2=0x%08x\n", __machine_arch_type,
1104 if (__atags_pointer)
1105 early_print(" r2[]=%*ph\n", 16, atags_vaddr);
1106 dump_machine_table();
1109 machine_desc = mdesc;
1110 machine_name = mdesc->name;
1111 dump_stack_set_arch_desc("%s", mdesc->name);
1113 if (mdesc->reboot_mode != REBOOT_HARD)
1114 reboot_mode = mdesc->reboot_mode;
1116 init_mm.start_code = (unsigned long) _text;
1117 init_mm.end_code = (unsigned long) _etext;
1118 init_mm.end_data = (unsigned long) _edata;
1119 init_mm.brk = (unsigned long) _end;
1121 /* populate cmd_line too for later use, preserving boot_command_line */
1122 strlcpy(cmd_line, boot_command_line, COMMAND_LINE_SIZE);
1123 *cmdline_p = cmd_line;
1125 early_fixmap_init();
1126 early_ioremap_init();
1128 parse_early_param();
1131 early_mm_init(mdesc);
1133 setup_dma_zone(mdesc);
1137 * Make sure the calculation for lowmem/highmem is set appropriately
1138 * before reserving/allocating any mmeory
1140 adjust_lowmem_bounds();
1141 arm_memblock_init(mdesc);
1142 /* Memory may have been removed so recalculate the bounds. */
1143 adjust_lowmem_bounds();
1145 early_ioremap_reset();
1148 request_standard_resources(mdesc);
1151 arm_pm_restart = mdesc->restart;
1153 unflatten_device_tree();
1155 arm_dt_init_cpu_maps();
1159 if (!mdesc->smp_init || !mdesc->smp_init()) {
1160 if (psci_smp_available())
1161 smp_set_ops(&psci_smp_ops);
1162 else if (mdesc->smp)
1163 smp_set_ops(mdesc->smp);
1166 smp_build_mpidr_hash();
1173 reserve_crashkernel();
1175 #ifdef CONFIG_GENERIC_IRQ_MULTI_HANDLER
1176 handle_arch_irq = mdesc->handle_irq;
1180 #if defined(CONFIG_VGA_CONSOLE)
1181 conswitchp = &vga_con;
1185 if (mdesc->init_early)
1186 mdesc->init_early();
1190 static int __init topology_init(void)
1194 for_each_possible_cpu(cpu) {
1195 struct cpuinfo_arm *cpuinfo = &per_cpu(cpu_data, cpu);
1196 cpuinfo->cpu.hotpluggable = platform_can_hotplug_cpu(cpu);
1197 register_cpu(&cpuinfo->cpu, cpu);
1202 subsys_initcall(topology_init);
1204 #ifdef CONFIG_HAVE_PROC_CPU
1205 static int __init proc_cpu_init(void)
1207 struct proc_dir_entry *res;
1209 res = proc_mkdir("cpu", NULL);
1214 fs_initcall(proc_cpu_init);
1217 static const char *hwcap_str[] = {
1243 static const char *hwcap2_str[] = {
1252 static int c_show(struct seq_file *m, void *v)
1257 for_each_online_cpu(i) {
1259 * glibc reads /proc/cpuinfo to determine the number of
1260 * online processors, looking for lines beginning with
1261 * "processor". Give glibc what it expects.
1263 seq_printf(m, "processor\t: %d\n", i);
1264 cpuid = is_smp() ? per_cpu(cpu_data, i).cpuid : read_cpuid_id();
1265 seq_printf(m, "model name\t: %s rev %d (%s)\n",
1266 cpu_name, cpuid & 15, elf_platform);
1268 #if defined(CONFIG_SMP)
1269 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1270 per_cpu(cpu_data, i).loops_per_jiffy / (500000UL/HZ),
1271 (per_cpu(cpu_data, i).loops_per_jiffy / (5000UL/HZ)) % 100);
1273 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
1274 loops_per_jiffy / (500000/HZ),
1275 (loops_per_jiffy / (5000/HZ)) % 100);
1277 /* dump out the processor features */
1278 seq_puts(m, "Features\t: ");
1280 for (j = 0; hwcap_str[j]; j++)
1281 if (elf_hwcap & (1 << j))
1282 seq_printf(m, "%s ", hwcap_str[j]);
1284 for (j = 0; hwcap2_str[j]; j++)
1285 if (elf_hwcap2 & (1 << j))
1286 seq_printf(m, "%s ", hwcap2_str[j]);
1288 seq_printf(m, "\nCPU implementer\t: 0x%02x\n", cpuid >> 24);
1289 seq_printf(m, "CPU architecture: %s\n",
1290 proc_arch[cpu_architecture()]);
1292 if ((cpuid & 0x0008f000) == 0x00000000) {
1294 seq_printf(m, "CPU part\t: %07x\n", cpuid >> 4);
1296 if ((cpuid & 0x0008f000) == 0x00007000) {
1298 seq_printf(m, "CPU variant\t: 0x%02x\n",
1299 (cpuid >> 16) & 127);
1302 seq_printf(m, "CPU variant\t: 0x%x\n",
1303 (cpuid >> 20) & 15);
1305 seq_printf(m, "CPU part\t: 0x%03x\n",
1306 (cpuid >> 4) & 0xfff);
1308 seq_printf(m, "CPU revision\t: %d\n\n", cpuid & 15);
1311 seq_printf(m, "Hardware\t: %s\n", machine_name);
1312 seq_printf(m, "Revision\t: %04x\n", system_rev);
1313 seq_printf(m, "Serial\t\t: %s\n", system_serial);
1318 static void *c_start(struct seq_file *m, loff_t *pos)
1320 return *pos < 1 ? (void *)1 : NULL;
1323 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1329 static void c_stop(struct seq_file *m, void *v)
1333 const struct seq_operations cpuinfo_op = {