2 * arch/arm/kernel/probes.c
4 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
6 * Some contents moved here from arch/arm/include/asm/kprobes-arm.c which is
7 * Copyright (C) 2006, 2007 Motorola Inc.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <asm/system_info.h>
17 #include <asm/ptrace.h>
18 #include <linux/bug.h>
23 #ifndef find_str_pc_offset
26 * For STR and STM instructions, an ARM core may choose to use either
27 * a +8 or a +12 displacement from the current instruction's address.
28 * Whichever value is chosen for a given core, it must be the same for
29 * both instructions and may not change. This function measures it.
34 void __init find_str_pc_offset(void)
36 int addr, scratch, ret;
39 "sub %[ret], pc, #4 \n\t"
40 "str pc, %[addr] \n\t"
41 "ldr %[scr], %[addr] \n\t"
42 "sub %[ret], %[scr], %[ret] \n\t"
43 : [ret] "=r" (ret), [scr] "=r" (scratch), [addr] "+m" (addr));
48 #endif /* !find_str_pc_offset */
51 #ifndef test_load_write_pc_interworking
53 bool load_write_pc_interworks;
55 void __init test_load_write_pc_interworking(void)
57 int arch = cpu_architecture();
58 BUG_ON(arch == CPU_ARCH_UNKNOWN);
59 load_write_pc_interworks = arch >= CPU_ARCH_ARMv5T;
62 #endif /* !test_load_write_pc_interworking */
65 #ifndef test_alu_write_pc_interworking
67 bool alu_write_pc_interworks;
69 void __init test_alu_write_pc_interworking(void)
71 int arch = cpu_architecture();
72 BUG_ON(arch == CPU_ARCH_UNKNOWN);
73 alu_write_pc_interworks = arch >= CPU_ARCH_ARMv7;
76 #endif /* !test_alu_write_pc_interworking */
79 void __init arm_probes_decode_init(void)
82 test_load_write_pc_interworking();
83 test_alu_write_pc_interworking();
87 static unsigned long __kprobes __check_eq(unsigned long cpsr)
89 return cpsr & PSR_Z_BIT;
92 static unsigned long __kprobes __check_ne(unsigned long cpsr)
94 return (~cpsr) & PSR_Z_BIT;
97 static unsigned long __kprobes __check_cs(unsigned long cpsr)
99 return cpsr & PSR_C_BIT;
102 static unsigned long __kprobes __check_cc(unsigned long cpsr)
104 return (~cpsr) & PSR_C_BIT;
107 static unsigned long __kprobes __check_mi(unsigned long cpsr)
109 return cpsr & PSR_N_BIT;
112 static unsigned long __kprobes __check_pl(unsigned long cpsr)
114 return (~cpsr) & PSR_N_BIT;
117 static unsigned long __kprobes __check_vs(unsigned long cpsr)
119 return cpsr & PSR_V_BIT;
122 static unsigned long __kprobes __check_vc(unsigned long cpsr)
124 return (~cpsr) & PSR_V_BIT;
127 static unsigned long __kprobes __check_hi(unsigned long cpsr)
129 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
130 return cpsr & PSR_C_BIT;
133 static unsigned long __kprobes __check_ls(unsigned long cpsr)
135 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
136 return (~cpsr) & PSR_C_BIT;
139 static unsigned long __kprobes __check_ge(unsigned long cpsr)
141 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
142 return (~cpsr) & PSR_N_BIT;
145 static unsigned long __kprobes __check_lt(unsigned long cpsr)
147 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
148 return cpsr & PSR_N_BIT;
151 static unsigned long __kprobes __check_gt(unsigned long cpsr)
153 unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
154 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
155 return (~temp) & PSR_N_BIT;
158 static unsigned long __kprobes __check_le(unsigned long cpsr)
160 unsigned long temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
161 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
162 return temp & PSR_N_BIT;
165 static unsigned long __kprobes __check_al(unsigned long cpsr)
170 probes_check_cc * const probes_condition_checks[16] = {
171 &__check_eq, &__check_ne, &__check_cs, &__check_cc,
172 &__check_mi, &__check_pl, &__check_vs, &__check_vc,
173 &__check_hi, &__check_ls, &__check_ge, &__check_lt,
174 &__check_gt, &__check_le, &__check_al, &__check_al
178 void __kprobes probes_simulate_nop(probes_opcode_t opcode,
179 struct arch_probes_insn *asi,
180 struct pt_regs *regs)
184 void __kprobes probes_emulate_none(probes_opcode_t opcode,
185 struct arch_probes_insn *asi,
186 struct pt_regs *regs)
192 * Prepare an instruction slot to receive an instruction for emulating.
193 * This is done by placing a subroutine return after the location where the
194 * instruction will be placed. We also modify ARM instructions to be
195 * unconditional as the condition code will already be checked before any
196 * emulation handler is called.
198 static probes_opcode_t __kprobes
199 prepare_emulated_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
202 #ifdef CONFIG_THUMB2_KERNEL
204 u16 *thumb_insn = (u16 *)asi->insn;
205 thumb_insn[1] = 0x4770; /* Thumb bx lr */
206 thumb_insn[2] = 0x4770; /* Thumb bx lr */
209 asi->insn[1] = 0xe12fff1e; /* ARM bx lr */
211 asi->insn[1] = 0xe1a0f00e; /* mov pc, lr */
213 /* Make an ARM instruction unconditional */
214 if (insn < 0xe0000000)
215 insn = (insn | 0xe0000000) & ~0x10000000;
220 * Write a (probably modified) instruction into the slot previously prepared by
221 * prepare_emulated_insn
223 static void __kprobes
224 set_emulated_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
227 #ifdef CONFIG_THUMB2_KERNEL
229 u16 *ip = (u16 *)asi->insn;
230 if (is_wide_instruction(insn))
240 * When we modify the register numbers encoded in an instruction to be emulated,
241 * the new values come from this define. For ARM and 32-bit Thumb instructions
244 * bit position 16 12 8 4 0
245 * ---------------+---+---+---+---+---+
246 * register r2 r0 r1 -- r3
248 #define INSN_NEW_BITS 0x00020103
250 /* Each nibble has same value as that at INSN_NEW_BITS bit 16 */
251 #define INSN_SAMEAS16_BITS 0x22222222
254 * Validate and modify each of the registers encoded in an instruction.
256 * Each nibble in regs contains a value from enum decode_reg_type. For each
257 * non-zero value, the corresponding nibble in pinsn is validated and modified
258 * according to the type.
260 static bool __kprobes decode_regs(probes_opcode_t *pinsn, u32 regs, bool modify)
262 probes_opcode_t insn = *pinsn;
263 probes_opcode_t mask = 0xf; /* Start at least significant nibble */
265 for (; regs != 0; regs >>= 4, mask <<= 4) {
267 probes_opcode_t new_bits = INSN_NEW_BITS;
269 switch (regs & 0xf) {
272 /* Nibble not a register, skip to next */
276 /* Any register is allowed */
279 case REG_TYPE_SAMEAS16:
280 /* Replace register with same as at bit position 16 */
281 new_bits = INSN_SAMEAS16_BITS;
285 /* Only allow SP (R13) */
286 if ((insn ^ 0xdddddddd) & mask)
291 /* Only allow PC (R15) */
292 if ((insn ^ 0xffffffff) & mask)
297 /* Reject SP (R13) */
298 if (((insn ^ 0xdddddddd) & mask) == 0)
302 case REG_TYPE_NOSPPC:
303 case REG_TYPE_NOSPPCX:
304 /* Reject SP and PC (R13 and R15) */
305 if (((insn ^ 0xdddddddd) & 0xdddddddd & mask) == 0)
309 case REG_TYPE_NOPCWB:
310 if (!is_writeback(insn))
311 break; /* No writeback, so any register is OK */
312 /* fall through... */
315 /* Reject PC (R15) */
316 if (((insn ^ 0xffffffff) & mask) == 0)
321 /* Replace value of nibble with new register number... */
323 insn |= new_bits & mask;
335 static const int decode_struct_sizes[NUM_DECODE_TYPES] = {
336 [DECODE_TYPE_TABLE] = sizeof(struct decode_table),
337 [DECODE_TYPE_CUSTOM] = sizeof(struct decode_custom),
338 [DECODE_TYPE_SIMULATE] = sizeof(struct decode_simulate),
339 [DECODE_TYPE_EMULATE] = sizeof(struct decode_emulate),
340 [DECODE_TYPE_OR] = sizeof(struct decode_or),
341 [DECODE_TYPE_REJECT] = sizeof(struct decode_reject)
345 * probes_decode_insn operates on data tables in order to decode an ARM
346 * architecture instruction onto which a kprobe has been placed.
348 * These instruction decoding tables are a concatenation of entries each
349 * of which consist of one of the following structs:
358 * Each of these starts with a struct decode_header which has the following
365 * The least significant DECODE_TYPE_BITS of type_regs contains a value
366 * from enum decode_type, this indicates which of the decode_* structs
367 * the entry contains. The value DECODE_TYPE_END indicates the end of the
370 * When the table is parsed, each entry is checked in turn to see if it
371 * matches the instruction to be decoded using the test:
373 * (insn & mask) == value
375 * If no match is found before the end of the table is reached then decoding
376 * fails with INSN_REJECTED.
378 * When a match is found, decode_regs() is called to validate and modify each
379 * of the registers encoded in the instruction; the data it uses to do this
380 * is (type_regs >> DECODE_TYPE_BITS). A validation failure will cause decoding
381 * to fail with INSN_REJECTED.
383 * Once the instruction has passed the above tests, further processing
384 * depends on the type of the table entry's decode struct.
388 probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
389 const union decode_item *table, bool thumb,
390 bool emulate, const union decode_action *actions)
392 const struct decode_header *h = (struct decode_header *)table;
393 const struct decode_header *next;
394 bool matched = false;
397 insn = prepare_emulated_insn(insn, asi, thumb);
400 enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
401 u32 regs = h->type_regs.bits >> DECODE_TYPE_BITS;
403 if (type == DECODE_TYPE_END)
404 return INSN_REJECTED;
406 next = (struct decode_header *)
407 ((uintptr_t)h + decode_struct_sizes[type]);
409 if (!matched && (insn & h->mask.bits) != h->value.bits)
412 if (!decode_regs(&insn, regs, emulate))
413 return INSN_REJECTED;
417 case DECODE_TYPE_TABLE: {
418 struct decode_table *d = (struct decode_table *)h;
419 next = (struct decode_header *)d->table.table;
423 case DECODE_TYPE_CUSTOM: {
424 struct decode_custom *d = (struct decode_custom *)h;
425 return actions[d->decoder.action].decoder(insn, asi, h);
428 case DECODE_TYPE_SIMULATE: {
429 struct decode_simulate *d = (struct decode_simulate *)h;
430 asi->insn_handler = actions[d->handler.action].handler;
431 return INSN_GOOD_NO_SLOT;
434 case DECODE_TYPE_EMULATE: {
435 struct decode_emulate *d = (struct decode_emulate *)h;
438 return actions[d->handler.action].decoder(insn,
441 asi->insn_handler = actions[d->handler.action].handler;
442 set_emulated_insn(insn, asi, thumb);
450 case DECODE_TYPE_REJECT:
452 return INSN_REJECTED;