2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
3 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, version 2, as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 #include <linux/types.h>
23 #include <linux/psci.h>
24 #include <asm/ptrace.h>
26 #define __KVM_HAVE_GUEST_DEBUG
27 #define __KVM_HAVE_IRQ_LINE
28 #define __KVM_HAVE_READONLY_MEM
30 #define KVM_REG_SIZE(id) \
31 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
33 /* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */
34 #define KVM_ARM_SVC_sp svc_regs[0]
35 #define KVM_ARM_SVC_lr svc_regs[1]
36 #define KVM_ARM_SVC_spsr svc_regs[2]
37 #define KVM_ARM_ABT_sp abt_regs[0]
38 #define KVM_ARM_ABT_lr abt_regs[1]
39 #define KVM_ARM_ABT_spsr abt_regs[2]
40 #define KVM_ARM_UND_sp und_regs[0]
41 #define KVM_ARM_UND_lr und_regs[1]
42 #define KVM_ARM_UND_spsr und_regs[2]
43 #define KVM_ARM_IRQ_sp irq_regs[0]
44 #define KVM_ARM_IRQ_lr irq_regs[1]
45 #define KVM_ARM_IRQ_spsr irq_regs[2]
47 /* Valid only for fiq_regs in struct kvm_regs */
48 #define KVM_ARM_FIQ_r8 fiq_regs[0]
49 #define KVM_ARM_FIQ_r9 fiq_regs[1]
50 #define KVM_ARM_FIQ_r10 fiq_regs[2]
51 #define KVM_ARM_FIQ_fp fiq_regs[3]
52 #define KVM_ARM_FIQ_ip fiq_regs[4]
53 #define KVM_ARM_FIQ_sp fiq_regs[5]
54 #define KVM_ARM_FIQ_lr fiq_regs[6]
55 #define KVM_ARM_FIQ_spsr fiq_regs[7]
58 struct pt_regs usr_regs; /* R0_usr - R14_usr, PC, CPSR */
59 unsigned long svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */
60 unsigned long abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */
61 unsigned long und_regs[3]; /* SP_und, LR_und, SPSR_und */
62 unsigned long irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */
63 unsigned long fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */
66 /* Supported Processor Types */
67 #define KVM_ARM_TARGET_CORTEX_A15 0
68 #define KVM_ARM_TARGET_CORTEX_A7 1
69 #define KVM_ARM_NUM_TARGETS 2
71 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
72 #define KVM_ARM_DEVICE_TYPE_SHIFT 0
73 #define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
74 #define KVM_ARM_DEVICE_ID_SHIFT 16
75 #define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
77 /* Supported device IDs */
78 #define KVM_ARM_DEVICE_VGIC_V2 0
80 /* Supported VGIC address types */
81 #define KVM_VGIC_V2_ADDR_TYPE_DIST 0
82 #define KVM_VGIC_V2_ADDR_TYPE_CPU 1
84 #define KVM_VGIC_V2_DIST_SIZE 0x1000
85 #define KVM_VGIC_V2_CPU_SIZE 0x2000
87 /* Supported VGICv3 address types */
88 #define KVM_VGIC_V3_ADDR_TYPE_DIST 2
89 #define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
90 #define KVM_VGIC_ITS_ADDR_TYPE 4
92 #define KVM_VGIC_V3_DIST_SIZE SZ_64K
93 #define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
94 #define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
96 #define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
97 #define KVM_ARM_VCPU_PSCI_0_2 1 /* CPU uses PSCI v0.2 */
99 struct kvm_vcpu_init {
110 struct kvm_guest_debug_arch {
113 struct kvm_debug_exit_arch {
116 struct kvm_sync_regs {
117 /* Used with KVM_CAP_ARM_USER_IRQ */
118 __u64 device_irq_level;
121 struct kvm_arch_memory_slot {
124 /* If you need to interpret the index values, here is the key: */
125 #define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
126 #define KVM_REG_ARM_COPROC_SHIFT 16
127 #define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007
128 #define KVM_REG_ARM_32_OPC2_SHIFT 0
129 #define KVM_REG_ARM_OPC1_MASK 0x0000000000000078
130 #define KVM_REG_ARM_OPC1_SHIFT 3
131 #define KVM_REG_ARM_CRM_MASK 0x0000000000000780
132 #define KVM_REG_ARM_CRM_SHIFT 7
133 #define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
134 #define KVM_REG_ARM_32_CRN_SHIFT 11
136 #define ARM_CP15_REG_SHIFT_MASK(x,n) \
137 (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
139 #define __ARM_CP15_REG(op1,crn,crm,op2) \
140 (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \
141 ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \
142 ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
143 ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
144 ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
146 #define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
148 #define __ARM_CP15_REG64(op1,crm) \
149 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
150 #define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
152 #define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
153 #define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
154 #define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
156 /* Normal registers are mapped as coprocessor 16. */
157 #define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
158 #define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)
160 /* Some registers need more space to represent values. */
161 #define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
162 #define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
163 #define KVM_REG_ARM_DEMUX_ID_SHIFT 8
164 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
165 #define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
166 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
168 /* VFP registers: we could overload CP10 like ARM does, but that's ugly. */
169 #define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT)
170 #define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF
171 #define KVM_REG_ARM_VFP_BASE_REG 0x0
172 #define KVM_REG_ARM_VFP_FPSID 0x1000
173 #define KVM_REG_ARM_VFP_FPSCR 0x1001
174 #define KVM_REG_ARM_VFP_MVFR1 0x1006
175 #define KVM_REG_ARM_VFP_MVFR0 0x1007
176 #define KVM_REG_ARM_VFP_FPEXC 0x1008
177 #define KVM_REG_ARM_VFP_FPINST 0x1009
178 #define KVM_REG_ARM_VFP_FPINST2 0x100A
180 /* Device Control API: ARM VGIC */
181 #define KVM_DEV_ARM_VGIC_GRP_ADDR 0
182 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
183 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
184 #define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
185 #define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
186 #define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
187 #define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
188 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
189 #define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
190 #define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
191 #define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
192 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
193 #define KVM_DEV_ARM_VGIC_GRP_CTRL 4
194 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
195 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
196 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
197 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
198 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
199 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
200 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
201 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
202 #define VGIC_LEVEL_INFO_LINE_LEVEL 0
204 #define KVM_DEV_ARM_VGIC_CTRL_INIT 0
206 /* KVM_IRQ_LINE irq field index values */
207 #define KVM_ARM_IRQ_TYPE_SHIFT 24
208 #define KVM_ARM_IRQ_TYPE_MASK 0xff
209 #define KVM_ARM_IRQ_VCPU_SHIFT 16
210 #define KVM_ARM_IRQ_VCPU_MASK 0xff
211 #define KVM_ARM_IRQ_NUM_SHIFT 0
212 #define KVM_ARM_IRQ_NUM_MASK 0xffff
215 #define KVM_ARM_IRQ_TYPE_CPU 0
216 #define KVM_ARM_IRQ_TYPE_SPI 1
217 #define KVM_ARM_IRQ_TYPE_PPI 2
219 /* out-of-kernel GIC cpu interrupt injection irq_number field */
220 #define KVM_ARM_IRQ_CPU_IRQ 0
221 #define KVM_ARM_IRQ_CPU_FIQ 1
224 * This used to hold the highest supported SPI, but it is now obsolete
225 * and only here to provide source code level compatibility with older
226 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
229 #define KVM_ARM_IRQ_GIC_MAX 127
232 /* One single KVM irqchip, ie. the VGIC */
233 #define KVM_NR_IRQCHIPS 1
236 #define KVM_PSCI_FN_BASE 0x95c1ba5e
237 #define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
239 #define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
240 #define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
241 #define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
242 #define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
244 #define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
245 #define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
246 #define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
247 #define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
249 #endif /* __ARM_KVM_H__ */