1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/include/asm/io.h
5 * Copyright (C) 1996-2000 Russell King
8 * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
9 * constant addresses and variable addresses.
10 * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
11 * specific IO header files.
12 * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
13 * 04-Apr-1999 PJB Added check_signature.
14 * 12-Dec-1999 RMK More cleanups
15 * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
16 * 05-Oct-2004 BJD Moved memory string functions to use void __iomem
18 #ifndef __ASM_ARM_IO_H
19 #define __ASM_ARM_IO_H
23 #include <linux/string.h>
24 #include <linux/types.h>
25 #include <asm/byteorder.h>
26 #include <asm/memory.h>
27 #include <asm-generic/pci_iomap.h>
30 * ISA I/O bus memory addresses are 1:1 with the physical address.
32 #define isa_virt_to_bus virt_to_phys
33 #define isa_bus_to_virt phys_to_virt
36 * Atomic MMIO-wide IO modify
38 extern void atomic_io_modify(void __iomem *reg, u32 mask, u32 set);
39 extern void atomic_io_modify_relaxed(void __iomem *reg, u32 mask, u32 set);
42 * Generic IO read/write. These perform native-endian accesses. Note
43 * that some architectures will want to re-define __raw_{read,write}w.
45 void __raw_writesb(volatile void __iomem *addr, const void *data, int bytelen);
46 void __raw_writesw(volatile void __iomem *addr, const void *data, int wordlen);
47 void __raw_writesl(volatile void __iomem *addr, const void *data, int longlen);
49 void __raw_readsb(const volatile void __iomem *addr, void *data, int bytelen);
50 void __raw_readsw(const volatile void __iomem *addr, void *data, int wordlen);
51 void __raw_readsl(const volatile void __iomem *addr, void *data, int longlen);
53 #if __LINUX_ARM_ARCH__ < 6
55 * Half-word accesses are problematic with RiscPC due to limitations of
56 * the bus. Rather than special-case the machine, just let the compiler
57 * generate the access for CPUs prior to ARMv6.
59 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
60 #define __raw_writew(v,a) ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
63 * When running under a hypervisor, we want to avoid I/O accesses with
64 * writeback addressing modes as these incur a significant performance
65 * overhead (the address generation must be emulated in software).
67 #define __raw_writew __raw_writew
68 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
70 asm volatile("strh %1, %0"
71 : : "Q" (*(volatile u16 __force *)addr), "r" (val));
74 #define __raw_readw __raw_readw
75 static inline u16 __raw_readw(const volatile void __iomem *addr)
78 asm volatile("ldrh %0, %1"
80 : "Q" (*(volatile u16 __force *)addr));
85 #define __raw_writeb __raw_writeb
86 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
88 asm volatile("strb %1, %0"
89 : : "Qo" (*(volatile u8 __force *)addr), "r" (val));
92 #define __raw_writel __raw_writel
93 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
95 asm volatile("str %1, %0"
96 : : "Qo" (*(volatile u32 __force *)addr), "r" (val));
99 #define __raw_readb __raw_readb
100 static inline u8 __raw_readb(const volatile void __iomem *addr)
103 asm volatile("ldrb %0, %1"
105 : "Qo" (*(volatile u8 __force *)addr));
109 #define __raw_readl __raw_readl
110 static inline u32 __raw_readl(const volatile void __iomem *addr)
113 asm volatile("ldr %0, %1"
115 : "Qo" (*(volatile u32 __force *)addr));
120 * Architecture ioremap implementation.
123 #define MT_DEVICE_NONSHARED 1
124 #define MT_DEVICE_CACHED 2
125 #define MT_DEVICE_WC 3
127 * types 4 onwards can be found in asm/mach/map.h and are undefined
132 * __arm_ioremap takes CPU physical address.
133 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
134 * The _caller variety takes a __builtin_return_address(0) value for
135 * /proc/vmalloc to use - and should only be used in non-inline functions.
137 extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
139 extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
140 extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
141 void __arm_iomem_set_ro(void __iomem *ptr, size_t size);
142 extern void __iounmap(volatile void __iomem *addr);
144 extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
145 unsigned int, void *);
146 extern void (*arch_iounmap)(volatile void __iomem *);
149 * Bad read/write accesses...
151 extern void __readwrite_bug(const char *fn);
154 * A typesafe __io() helper
156 static inline void __iomem *__typesafe_io(unsigned long addr)
158 return (void __iomem *)addr;
161 #define IOMEM(x) ((void __force __iomem *)(x))
164 #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
165 #include <asm/barrier.h>
166 #define __iormb() rmb()
167 #define __iowmb() wmb()
169 #define __iormb() do { } while (0)
170 #define __iowmb() do { } while (0)
173 /* PCI fixed i/o mapping */
174 #define PCI_IO_VIRT_BASE 0xfee00000
175 #define PCI_IOBASE ((void __iomem *)PCI_IO_VIRT_BASE)
177 #if defined(CONFIG_PCI) || IS_ENABLED(CONFIG_PCMCIA)
178 void pci_ioremap_set_mem_type(int mem_type);
180 static inline void pci_ioremap_set_mem_type(int mem_type) {}
185 #define pci_remap_iospace pci_remap_iospace
186 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
189 * PCI configuration space mapping function.
191 * The PCI specification does not allow configuration write
192 * transactions to be posted. Add an arch specific
193 * pci_remap_cfgspace() definition that is implemented
194 * through strongly ordered memory mappings.
196 #define pci_remap_cfgspace pci_remap_cfgspace
197 void __iomem *pci_remap_cfgspace(resource_size_t res_cookie, size_t size);
199 * Now, pick up the machine-defined IO definitions
201 #ifdef CONFIG_NEED_MACH_IO_H
204 #if IS_ENABLED(CONFIG_PCMCIA) || defined(CONFIG_PCI)
205 #define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
207 #define IO_SPACE_LIMIT ((resource_size_t)0)
209 #define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
213 * IO port access primitives
214 * -------------------------
216 * The ARM doesn't have special IO access instructions; all IO is memory
217 * mapped. Note that these are defined to perform little endian accesses
218 * only. Their primary purpose is to access PCI and ISA peripherals.
220 * Note that for a big endian machine, this implies that the following
221 * big endian mode connectivity is in place, as described by numerous
224 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
225 * ARM: D24-D31 D16-D23 D8-D15 D0-D7
227 * The machine specific io.h include defines __io to translate an "IO"
228 * address to a memory address.
230 * Note that we prevent GCC re-ordering or caching values in expressions
231 * by introducing sequence points into the in*() definitions. Note that
232 * __raw_* do not guarantee this behaviour.
234 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
237 #define outb(v,p) ({ __iowmb(); __raw_writeb(v,__io(p)); })
238 #define outw(v,p) ({ __iowmb(); __raw_writew((__force __u16) \
239 cpu_to_le16(v),__io(p)); })
240 #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
241 cpu_to_le32(v),__io(p)); })
243 #define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
244 #define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
245 __raw_readw(__io(p))); __iormb(); __v; })
246 #define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
247 __raw_readl(__io(p))); __iormb(); __v; })
249 #define outsb(p,d,l) __raw_writesb(__io(p),d,l)
250 #define outsw(p,d,l) __raw_writesw(__io(p),d,l)
251 #define outsl(p,d,l) __raw_writesl(__io(p),d,l)
253 #define insb(p,d,l) __raw_readsb(__io(p),d,l)
254 #define insw(p,d,l) __raw_readsw(__io(p),d,l)
255 #define insl(p,d,l) __raw_readsl(__io(p),d,l)
259 * String version of IO memory access ops:
261 extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
262 extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
263 extern void _memset_io(volatile void __iomem *, int, size_t);
266 * Memory access primitives
267 * ------------------------
269 * These perform PCI memory accesses via an ioremap region. They don't
270 * take an address as such, but a cookie.
272 * Again, these are defined to perform little endian accesses. See the
273 * IO port primitives for more information.
276 #define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; })
277 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
278 __raw_readw(c)); __r; })
279 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
280 __raw_readl(c)); __r; })
282 #define writeb_relaxed(v,c) __raw_writeb(v,c)
283 #define writew_relaxed(v,c) __raw_writew((__force u16) cpu_to_le16(v),c)
284 #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
286 #define readb(c) ({ u8 __v = readb_relaxed(c); __iormb(); __v; })
287 #define readw(c) ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
288 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
290 #define writeb(v,c) ({ __iowmb(); writeb_relaxed(v,c); })
291 #define writew(v,c) ({ __iowmb(); writew_relaxed(v,c); })
292 #define writel(v,c) ({ __iowmb(); writel_relaxed(v,c); })
294 #define readsb(p,d,l) __raw_readsb(p,d,l)
295 #define readsw(p,d,l) __raw_readsw(p,d,l)
296 #define readsl(p,d,l) __raw_readsl(p,d,l)
298 #define writesb(p,d,l) __raw_writesb(p,d,l)
299 #define writesw(p,d,l) __raw_writesw(p,d,l)
300 #define writesl(p,d,l) __raw_writesl(p,d,l)
303 static inline void memset_io(volatile void __iomem *dst, unsigned c,
306 extern void mmioset(void *, unsigned int, size_t);
307 mmioset((void __force *)dst, c, count);
309 #define memset_io(dst,c,count) memset_io(dst,c,count)
311 static inline void memcpy_fromio(void *to, const volatile void __iomem *from,
314 extern void mmiocpy(void *, const void *, size_t);
315 mmiocpy(to, (const void __force *)from, count);
317 #define memcpy_fromio(to,from,count) memcpy_fromio(to,from,count)
319 static inline void memcpy_toio(volatile void __iomem *to, const void *from,
322 extern void mmiocpy(void *, const void *, size_t);
323 mmiocpy((void __force *)to, from, count);
325 #define memcpy_toio(to,from,count) memcpy_toio(to,from,count)
328 #define memset_io(c,v,l) _memset_io(c,(v),(l))
329 #define memcpy_fromio(a,c,l) _memcpy_fromio((a),c,(l))
330 #define memcpy_toio(c,a,l) _memcpy_toio(c,(a),(l))
336 * ioremap() and friends.
338 * ioremap() takes a resource address, and size. Due to the ARM memory
339 * types, it is important to use the correct ioremap() function as each
340 * mapping has specific properties.
342 * Function Memory type Cacheability Cache hint
343 * ioremap() Device n/a n/a
344 * ioremap_cache() Normal Writeback Read allocate
345 * ioremap_wc() Normal Non-cacheable n/a
346 * ioremap_wt() Normal Non-cacheable n/a
348 * All device mappings have the following properties:
349 * - no access speculation
350 * - no repetition (eg, on return from an exception)
351 * - number, order and size of accesses are maintained
352 * - unaligned accesses are "unpredictable"
353 * - writes may be delayed before they hit the endpoint device
355 * All normal memory mappings have the following properties:
356 * - reads can be repeated with no side effects
357 * - repeated reads return the last value written
358 * - reads can fetch additional locations without side effects
359 * - writes can be repeated (in certain cases) with no side effects
360 * - writes can be merged before accessing the target
361 * - unaligned accesses can be supported
362 * - ordering is not guaranteed without explicit dependencies or barrier
364 * - writes may be delayed before they hit the endpoint memory
366 * The cache hint is only a performance hint: CPUs may alias these hints.
367 * Eg, a CPU not implementing read allocate but implementing write allocate
368 * will provide a write allocate mapping instead.
370 void __iomem *ioremap(resource_size_t res_cookie, size_t size);
371 #define ioremap ioremap
374 * Do not use ioremap_cache for mapping memory. Use memremap instead.
376 void __iomem *ioremap_cache(resource_size_t res_cookie, size_t size);
377 #define ioremap_cache ioremap_cache
379 void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
380 #define ioremap_wc ioremap_wc
381 #define ioremap_wt ioremap_wc
383 void iounmap(volatile void __iomem *iomem_cookie);
384 #define iounmap iounmap
386 void *arch_memremap_wb(phys_addr_t phys_addr, size_t size);
387 #define arch_memremap_wb arch_memremap_wb
390 * io{read,write}{16,32}be() macros
392 #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
393 #define ioread32be(p) ({ __u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
395 #define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
396 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
399 #define ioport_map ioport_map
400 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
403 #define ioport_unmap ioport_unmap
404 extern void ioport_unmap(void __iomem *addr);
409 #define pci_iounmap pci_iounmap
410 extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
413 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
416 #define xlate_dev_mem_ptr(p) __va(p)
418 #include <asm-generic/io.h>
421 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
422 extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
423 extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
424 extern bool arch_memremap_can_ram_remap(resource_size_t offset, size_t size,
425 unsigned long flags);
426 #define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
430 * Register ISA memory and port locations for glibc iopl/inb/outb
433 extern void register_isa_ports(unsigned int mmio, unsigned int io,
434 unsigned int io_shift);
436 #endif /* __KERNEL__ */
437 #endif /* __ASM_ARM_IO_H */