1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/include/asm/atomic.h
5 * Copyright (C) 1996 Russell King.
6 * Copyright (C) 2002 Deep Blue Solutions Ltd.
8 #ifndef __ASM_ARM_ATOMIC_H
9 #define __ASM_ARM_ATOMIC_H
11 #include <linux/compiler.h>
12 #include <linux/prefetch.h>
13 #include <linux/types.h>
14 #include <linux/irqflags.h>
15 #include <asm/barrier.h>
16 #include <asm/cmpxchg.h>
18 #define ATOMIC_INIT(i) { (i) }
23 * On ARM, ordinary assignment (str instruction) doesn't clear the local
24 * strex/ldrex monitor on some implementations. The reason we can use it for
25 * atomic_set() is the clrex or dummy strex done on every exception return.
27 #define atomic_read(v) READ_ONCE((v)->counter)
28 #define atomic_set(v,i) WRITE_ONCE(((v)->counter), (i))
30 #if __LINUX_ARM_ARCH__ >= 6
33 * ARMv6 UP and SMP safe atomic ops. We use load exclusive and
34 * store exclusive to ensure that these are atomic. We may loop
35 * to ensure that the update happens.
38 #define ATOMIC_OP(op, c_op, asm_op) \
39 static inline void atomic_##op(int i, atomic_t *v) \
44 prefetchw(&v->counter); \
45 __asm__ __volatile__("@ atomic_" #op "\n" \
46 "1: ldrex %0, [%3]\n" \
47 " " #asm_op " %0, %0, %4\n" \
48 " strex %1, %0, [%3]\n" \
51 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
52 : "r" (&v->counter), "Ir" (i) \
56 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
57 static inline int atomic_##op##_return_relaxed(int i, atomic_t *v) \
62 prefetchw(&v->counter); \
64 __asm__ __volatile__("@ atomic_" #op "_return\n" \
65 "1: ldrex %0, [%3]\n" \
66 " " #asm_op " %0, %0, %4\n" \
67 " strex %1, %0, [%3]\n" \
70 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
71 : "r" (&v->counter), "Ir" (i) \
77 #define ATOMIC_FETCH_OP(op, c_op, asm_op) \
78 static inline int atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
83 prefetchw(&v->counter); \
85 __asm__ __volatile__("@ atomic_fetch_" #op "\n" \
86 "1: ldrex %0, [%4]\n" \
87 " " #asm_op " %1, %0, %5\n" \
88 " strex %2, %1, [%4]\n" \
91 : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Qo" (v->counter) \
92 : "r" (&v->counter), "Ir" (i) \
98 #define atomic_add_return_relaxed atomic_add_return_relaxed
99 #define atomic_sub_return_relaxed atomic_sub_return_relaxed
100 #define atomic_fetch_add_relaxed atomic_fetch_add_relaxed
101 #define atomic_fetch_sub_relaxed atomic_fetch_sub_relaxed
103 #define atomic_fetch_and_relaxed atomic_fetch_and_relaxed
104 #define atomic_fetch_andnot_relaxed atomic_fetch_andnot_relaxed
105 #define atomic_fetch_or_relaxed atomic_fetch_or_relaxed
106 #define atomic_fetch_xor_relaxed atomic_fetch_xor_relaxed
108 static inline int atomic_cmpxchg_relaxed(atomic_t *ptr, int old, int new)
113 prefetchw(&ptr->counter);
116 __asm__ __volatile__("@ atomic_cmpxchg\n"
120 "strexeq %0, %5, [%3]\n"
121 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
122 : "r" (&ptr->counter), "Ir" (old), "r" (new)
128 #define atomic_cmpxchg_relaxed atomic_cmpxchg_relaxed
130 static inline int atomic_fetch_add_unless(atomic_t *v, int a, int u)
136 prefetchw(&v->counter);
138 __asm__ __volatile__ ("@ atomic_add_unless\n"
139 "1: ldrex %0, [%4]\n"
143 " strex %2, %1, [%4]\n"
147 : "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
148 : "r" (&v->counter), "r" (u), "r" (a)
156 #define atomic_fetch_add_unless atomic_fetch_add_unless
158 #else /* ARM_ARCH_6 */
161 #error SMP not supported on pre-ARMv6 CPUs
164 #define ATOMIC_OP(op, c_op, asm_op) \
165 static inline void atomic_##op(int i, atomic_t *v) \
167 unsigned long flags; \
169 raw_local_irq_save(flags); \
171 raw_local_irq_restore(flags); \
174 #define ATOMIC_OP_RETURN(op, c_op, asm_op) \
175 static inline int atomic_##op##_return(int i, atomic_t *v) \
177 unsigned long flags; \
180 raw_local_irq_save(flags); \
183 raw_local_irq_restore(flags); \
188 #define ATOMIC_FETCH_OP(op, c_op, asm_op) \
189 static inline int atomic_fetch_##op(int i, atomic_t *v) \
191 unsigned long flags; \
194 raw_local_irq_save(flags); \
197 raw_local_irq_restore(flags); \
202 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
207 raw_local_irq_save(flags);
209 if (likely(ret == old))
211 raw_local_irq_restore(flags);
216 #define atomic_fetch_andnot atomic_fetch_andnot
218 #endif /* __LINUX_ARM_ARCH__ */
220 #define ATOMIC_OPS(op, c_op, asm_op) \
221 ATOMIC_OP(op, c_op, asm_op) \
222 ATOMIC_OP_RETURN(op, c_op, asm_op) \
223 ATOMIC_FETCH_OP(op, c_op, asm_op)
225 ATOMIC_OPS(add, +=, add)
226 ATOMIC_OPS(sub, -=, sub)
228 #define atomic_andnot atomic_andnot
231 #define ATOMIC_OPS(op, c_op, asm_op) \
232 ATOMIC_OP(op, c_op, asm_op) \
233 ATOMIC_FETCH_OP(op, c_op, asm_op)
235 ATOMIC_OPS(and, &=, and)
236 ATOMIC_OPS(andnot, &= ~, bic)
237 ATOMIC_OPS(or, |=, orr)
238 ATOMIC_OPS(xor, ^=, eor)
241 #undef ATOMIC_FETCH_OP
242 #undef ATOMIC_OP_RETURN
245 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
247 #ifndef CONFIG_GENERIC_ATOMIC64
252 #define ATOMIC64_INIT(i) { (i) }
254 #ifdef CONFIG_ARM_LPAE
255 static inline s64 atomic64_read(const atomic64_t *v)
259 __asm__ __volatile__("@ atomic64_read\n"
260 " ldrd %0, %H0, [%1]"
262 : "r" (&v->counter), "Qo" (v->counter)
268 static inline void atomic64_set(atomic64_t *v, s64 i)
270 __asm__ __volatile__("@ atomic64_set\n"
271 " strd %2, %H2, [%1]"
273 : "r" (&v->counter), "r" (i)
277 static inline s64 atomic64_read(const atomic64_t *v)
281 __asm__ __volatile__("@ atomic64_read\n"
282 " ldrexd %0, %H0, [%1]"
284 : "r" (&v->counter), "Qo" (v->counter)
290 static inline void atomic64_set(atomic64_t *v, s64 i)
294 prefetchw(&v->counter);
295 __asm__ __volatile__("@ atomic64_set\n"
296 "1: ldrexd %0, %H0, [%2]\n"
297 " strexd %0, %3, %H3, [%2]\n"
300 : "=&r" (tmp), "=Qo" (v->counter)
301 : "r" (&v->counter), "r" (i)
306 #define ATOMIC64_OP(op, op1, op2) \
307 static inline void atomic64_##op(s64 i, atomic64_t *v) \
312 prefetchw(&v->counter); \
313 __asm__ __volatile__("@ atomic64_" #op "\n" \
314 "1: ldrexd %0, %H0, [%3]\n" \
315 " " #op1 " %Q0, %Q0, %Q4\n" \
316 " " #op2 " %R0, %R0, %R4\n" \
317 " strexd %1, %0, %H0, [%3]\n" \
320 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
321 : "r" (&v->counter), "r" (i) \
325 #define ATOMIC64_OP_RETURN(op, op1, op2) \
327 atomic64_##op##_return_relaxed(s64 i, atomic64_t *v) \
332 prefetchw(&v->counter); \
334 __asm__ __volatile__("@ atomic64_" #op "_return\n" \
335 "1: ldrexd %0, %H0, [%3]\n" \
336 " " #op1 " %Q0, %Q0, %Q4\n" \
337 " " #op2 " %R0, %R0, %R4\n" \
338 " strexd %1, %0, %H0, [%3]\n" \
341 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
342 : "r" (&v->counter), "r" (i) \
348 #define ATOMIC64_FETCH_OP(op, op1, op2) \
350 atomic64_fetch_##op##_relaxed(s64 i, atomic64_t *v) \
355 prefetchw(&v->counter); \
357 __asm__ __volatile__("@ atomic64_fetch_" #op "\n" \
358 "1: ldrexd %0, %H0, [%4]\n" \
359 " " #op1 " %Q1, %Q0, %Q5\n" \
360 " " #op2 " %R1, %R0, %R5\n" \
361 " strexd %2, %1, %H1, [%4]\n" \
364 : "=&r" (result), "=&r" (val), "=&r" (tmp), "+Qo" (v->counter) \
365 : "r" (&v->counter), "r" (i) \
371 #define ATOMIC64_OPS(op, op1, op2) \
372 ATOMIC64_OP(op, op1, op2) \
373 ATOMIC64_OP_RETURN(op, op1, op2) \
374 ATOMIC64_FETCH_OP(op, op1, op2)
376 ATOMIC64_OPS(add, adds, adc)
377 ATOMIC64_OPS(sub, subs, sbc)
379 #define atomic64_add_return_relaxed atomic64_add_return_relaxed
380 #define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
381 #define atomic64_fetch_add_relaxed atomic64_fetch_add_relaxed
382 #define atomic64_fetch_sub_relaxed atomic64_fetch_sub_relaxed
385 #define ATOMIC64_OPS(op, op1, op2) \
386 ATOMIC64_OP(op, op1, op2) \
387 ATOMIC64_FETCH_OP(op, op1, op2)
389 #define atomic64_andnot atomic64_andnot
391 ATOMIC64_OPS(and, and, and)
392 ATOMIC64_OPS(andnot, bic, bic)
393 ATOMIC64_OPS(or, orr, orr)
394 ATOMIC64_OPS(xor, eor, eor)
396 #define atomic64_fetch_and_relaxed atomic64_fetch_and_relaxed
397 #define atomic64_fetch_andnot_relaxed atomic64_fetch_andnot_relaxed
398 #define atomic64_fetch_or_relaxed atomic64_fetch_or_relaxed
399 #define atomic64_fetch_xor_relaxed atomic64_fetch_xor_relaxed
402 #undef ATOMIC64_FETCH_OP
403 #undef ATOMIC64_OP_RETURN
406 static inline s64 atomic64_cmpxchg_relaxed(atomic64_t *ptr, s64 old, s64 new)
411 prefetchw(&ptr->counter);
414 __asm__ __volatile__("@ atomic64_cmpxchg\n"
415 "ldrexd %1, %H1, [%3]\n"
419 "strexdeq %0, %5, %H5, [%3]"
420 : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
421 : "r" (&ptr->counter), "r" (old), "r" (new)
427 #define atomic64_cmpxchg_relaxed atomic64_cmpxchg_relaxed
429 static inline s64 atomic64_xchg_relaxed(atomic64_t *ptr, s64 new)
434 prefetchw(&ptr->counter);
436 __asm__ __volatile__("@ atomic64_xchg\n"
437 "1: ldrexd %0, %H0, [%3]\n"
438 " strexd %1, %4, %H4, [%3]\n"
441 : "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
442 : "r" (&ptr->counter), "r" (new)
447 #define atomic64_xchg_relaxed atomic64_xchg_relaxed
449 static inline s64 atomic64_dec_if_positive(atomic64_t *v)
455 prefetchw(&v->counter);
457 __asm__ __volatile__("@ atomic64_dec_if_positive\n"
458 "1: ldrexd %0, %H0, [%3]\n"
459 " subs %Q0, %Q0, #1\n"
460 " sbc %R0, %R0, #0\n"
463 " strexd %1, %0, %H0, [%3]\n"
467 : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
475 #define atomic64_dec_if_positive atomic64_dec_if_positive
477 static inline s64 atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
483 prefetchw(&v->counter);
485 __asm__ __volatile__("@ atomic64_add_unless\n"
486 "1: ldrexd %0, %H0, [%4]\n"
490 " adds %Q1, %Q0, %Q6\n"
491 " adc %R1, %R0, %R6\n"
492 " strexd %2, %1, %H1, [%4]\n"
496 : "=&r" (oldval), "=&r" (newval), "=&r" (tmp), "+Qo" (v->counter)
497 : "r" (&v->counter), "r" (u), "r" (a)
505 #define atomic64_fetch_add_unless atomic64_fetch_add_unless
507 #endif /* !CONFIG_GENERIC_ATOMIC64 */