2 * arch/arm/include/asm/assembler.h
4 * Copyright (C) 1996-2000 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This file contains arm architecture specific defines
11 * for the different processors.
13 * Do not include any C declarations in this file - it is included by
16 #ifndef __ASM_ASSEMBLER_H__
17 #define __ASM_ASSEMBLER_H__
20 #error "Only include this from assembly code"
23 #include <asm/ptrace.h>
24 #include <asm/domain.h>
25 #include <asm/opcodes-virt.h>
26 #include <asm/asm-offsets.h>
28 #include <asm/thread_info.h>
33 * Endian independent macros for shifting bytes within registers.
38 #define get_byte_0 lsl #0
39 #define get_byte_1 lsr #8
40 #define get_byte_2 lsr #16
41 #define get_byte_3 lsr #24
42 #define put_byte_0 lsl #0
43 #define put_byte_1 lsl #8
44 #define put_byte_2 lsl #16
45 #define put_byte_3 lsl #24
49 #define get_byte_0 lsr #24
50 #define get_byte_1 lsr #16
51 #define get_byte_2 lsr #8
52 #define get_byte_3 lsl #0
53 #define put_byte_0 lsl #24
54 #define put_byte_1 lsl #16
55 #define put_byte_2 lsl #8
56 #define put_byte_3 lsl #0
59 /* Select code for any configuration running in BE8 mode */
60 #ifdef CONFIG_CPU_ENDIAN_BE8
61 #define ARM_BE8(code...) code
63 #define ARM_BE8(code...)
67 * Data preload for architectures that support it
69 #if __LINUX_ARM_ARCH__ >= 5
70 #define PLD(code...) code
76 * This can be used to enable code to cacheline align the destination
77 * pointer when bulk writing to memory. Experiments on StrongARM and
78 * XScale didn't show this a worthwhile thing to do when the cache is not
79 * set to write-allocate (this would need further testing on XScale when WA
82 * On Feroceon there is much to gain however, regardless of cache mode.
84 #ifdef CONFIG_CPU_FEROCEON
85 #define CALGN(code...) code
87 #define CALGN(code...)
91 * Enable and disable interrupts
93 #if __LINUX_ARM_ARCH__ >= 6
94 .macro disable_irq_notrace
98 .macro enable_irq_notrace
102 .macro disable_irq_notrace
103 msr cpsr_c, #PSR_I_BIT | SVC_MODE
106 .macro enable_irq_notrace
107 msr cpsr_c, #SVC_MODE
111 .macro asm_trace_hardirqs_off
112 #if defined(CONFIG_TRACE_IRQFLAGS)
113 stmdb sp!, {r0-r3, ip, lr}
114 bl trace_hardirqs_off
115 ldmia sp!, {r0-r3, ip, lr}
119 .macro asm_trace_hardirqs_on_cond, cond
120 #if defined(CONFIG_TRACE_IRQFLAGS)
122 * actually the registers should be pushed and pop'd conditionally, but
123 * after bl the flags are certainly clobbered
125 stmdb sp!, {r0-r3, ip, lr}
126 bl\cond trace_hardirqs_on
127 ldmia sp!, {r0-r3, ip, lr}
131 .macro asm_trace_hardirqs_on
132 asm_trace_hardirqs_on_cond al
137 asm_trace_hardirqs_off
141 asm_trace_hardirqs_on
145 * Save the current IRQ state and disable IRQs. Note that this macro
146 * assumes FIQs are enabled, and that the processor is in SVC mode.
148 .macro save_and_disable_irqs, oldcpsr
149 #ifdef CONFIG_CPU_V7M
150 mrs \oldcpsr, primask
157 .macro save_and_disable_irqs_notrace, oldcpsr
163 * Restore interrupt state previously stored in a register. We don't
164 * guarantee that this will preserve the flags.
166 .macro restore_irqs_notrace, oldcpsr
167 #ifdef CONFIG_CPU_V7M
168 msr primask, \oldcpsr
174 .macro restore_irqs, oldcpsr
175 tst \oldcpsr, #PSR_I_BIT
176 asm_trace_hardirqs_on_cond eq
177 restore_irqs_notrace \oldcpsr
181 * Assembly version of "adr rd, BSYM(sym)". This should only be used to
182 * reference local symbols in the same assembly file which are to be
183 * resolved by the assembler. Other usage is undefined.
185 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
186 .macro badr\c, rd, sym
187 #ifdef CONFIG_THUMB2_KERNEL
196 * Get current thread_info.
198 .macro get_thread_info, rd
199 ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT )
201 THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT )
202 mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
206 * Increment/decrement the preempt count.
208 #ifdef CONFIG_PREEMPT_COUNT
209 .macro inc_preempt_count, ti, tmp
210 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
211 add \tmp, \tmp, #1 @ increment it
212 str \tmp, [\ti, #TI_PREEMPT]
215 .macro dec_preempt_count, ti, tmp
216 ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
217 sub \tmp, \tmp, #1 @ decrement it
218 str \tmp, [\ti, #TI_PREEMPT]
221 .macro dec_preempt_count_ti, ti, tmp
223 dec_preempt_count \ti, \tmp
226 .macro inc_preempt_count, ti, tmp
229 .macro dec_preempt_count, ti, tmp
232 .macro dec_preempt_count_ti, ti, tmp
238 .pushsection __ex_table,"a"; \
244 #define ALT_SMP(instr...) \
247 * Note: if you get assembler errors from ALT_UP() when building with
248 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
249 * ALT_SMP( W(instr) ... )
251 #define ALT_UP(instr...) \
252 .pushsection ".alt.smp.init", "a" ;\
255 .if . - 9997b == 2 ;\
258 .if . - 9997b != 4 ;\
259 .error "ALT_UP() content must assemble to exactly 4 bytes";\
262 #define ALT_UP_B(label) \
263 .equ up_b_offset, label - 9998b ;\
264 .pushsection ".alt.smp.init", "a" ;\
266 W(b) . + up_b_offset ;\
269 #define ALT_SMP(instr...)
270 #define ALT_UP(instr...) instr
271 #define ALT_UP_B(label) b label
275 * Instruction barrier
278 #if __LINUX_ARM_ARCH__ >= 7
280 #elif __LINUX_ARM_ARCH__ == 6
281 mcr p15, 0, r0, c7, c5, 4
286 * SMP data memory barrier
290 #if __LINUX_ARM_ARCH__ >= 7
296 #elif __LINUX_ARM_ARCH__ == 6
297 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
299 #error Incompatible SMP platform
309 #if defined(CONFIG_CPU_V7M)
311 * setmode is used to assert to be in svc mode during boot. For v7-M
312 * this is done in __v7m_setup, so setmode can be empty here.
314 .macro setmode, mode, reg
316 #elif defined(CONFIG_THUMB2_KERNEL)
317 .macro setmode, mode, reg
322 .macro setmode, mode, reg
328 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
329 * a scratch register for the macro to overwrite.
331 * This macro is intended for forcing the CPU into SVC mode at boot time.
332 * you cannot return to the original mode.
334 .macro safe_svcmode_maskall reg:req
335 #if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
337 eor \reg, \reg, #HYP_MODE
339 bic \reg , \reg , #MODE_MASK
340 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
341 THUMB( orr \reg , \reg , #PSR_T_BIT )
343 orr \reg, \reg, #PSR_A_BIT
352 * workaround for possibly broken pre-v6 hardware
353 * (akita, Sharp Zaurus C-1000, PXA270-based)
355 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
360 * STRT/LDRT access macros with ARM and Thumb-2 variants
362 #ifdef CONFIG_THUMB2_KERNEL
364 .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
367 \instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
369 \instr\cond\()\t\().w \reg, [\ptr, #\off]
371 .error "Unsupported inc macro argument"
374 .pushsection __ex_table,"a"
380 .macro usracc, instr, reg, ptr, inc, cond, rept, abort
381 @ explicit IT instruction needed because of the label
382 @ introduced by the USER macro
389 .error "Unsupported rept macro argument"
393 @ Slightly optimised to avoid incrementing the pointer twice
394 usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
396 usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
399 add\cond \ptr, #\rept * \inc
402 #else /* !CONFIG_THUMB2_KERNEL */
404 .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
408 \instr\cond\()b\()\t \reg, [\ptr], #\inc
410 \instr\cond\()\t \reg, [\ptr], #\inc
412 .error "Unsupported inc macro argument"
415 .pushsection __ex_table,"a"
422 #endif /* CONFIG_THUMB2_KERNEL */
424 .macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
425 usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
428 .macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
429 usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
432 /* Utility macro for declaring string literals */
433 .macro string name:req, string
434 .type \name , #object
437 .size \name , . - \name
440 .macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
441 #ifndef CONFIG_CPU_USE_DOMAINS
442 adds \tmp, \addr, #\size - 1
443 sbcccs \tmp, \tmp, \limit
448 .macro uaccess_disable, tmp, isb=1
449 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
451 * Whenever we re-enter userspace, the domains should always be
454 mov \tmp, #DACR_UACCESS_DISABLE
455 mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register
462 .macro uaccess_enable, tmp, isb=1
463 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
465 * Whenever we re-enter userspace, the domains should always be
468 mov \tmp, #DACR_UACCESS_ENABLE
469 mcr p15, 0, \tmp, c3, c0, 0
476 .macro uaccess_save, tmp
477 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
478 mrc p15, 0, \tmp, c3, c0, 0
479 str \tmp, [sp, #S_FRAME_SIZE]
483 .macro uaccess_restore
484 #ifdef CONFIG_CPU_SW_DOMAIN_PAN
485 ldr r0, [sp, #S_FRAME_SIZE]
486 mcr p15, 0, r0, c3, c0, 0
490 .macro uaccess_save_and_disable, tmp
495 .irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
497 #if __LINUX_ARM_ARCH__ < 6
511 #ifdef CONFIG_THUMB2_KERNEL
516 #endif /* __ASM_ASSEMBLER_H__ */